The present invention relates to a digital-to-digital code converter, or decimator, which implements sinc.sup.3 processing. The input signal (X) to the code converter comprises a series of groups, each group including a series of N digital sample values occurring at high rate (1/.tau.) which are converted within the converter, using sinc.sup.3 processing, into a single digital value occurring at, for example, a (1/N).tau. rate for delivery to the converter output (Y). The code converter comprises three processing stages in cascade, where each stage includes separate accumulation means, each accumulation means arranged to add, during each series of N input sample values, the signal value received by that stage from the next preceding stage. Each of the three stages further includes a separate subprocessing means for processing the resultant accumulated digital value from the associated accumulation means at the end of each group period to produce a separated processed digital value which, when combined with the processed digital values from the other stages at the end of a group period, provides a single sinc.sup.3 processed digital value for the N input signal samples of each input group.
A digital resampling system is provided for converting a first digital signal to a second digital signal, where both signals represent the same analog signal but sampled at two different clock rates which are not phase-locked together. A filter is clocked by the first clock and outputs filtered samples at the first clock rate, optionally omitting samples which will not be used. A phase indicator determines the relative phase position of the first and second clocks and indicates an integer phase value and a fractional phase value which together indicate where a tick of the second clock falls among the ticks of the first clock. The integer phase value identifies a clock cycle of the first clock in which a tick of the second clock occurs, and the fractional phase value represents a fraction identifying a position of the tick of the second clock within the clock cycle of the first clock. A sample selector selects M filtered samples from those provided by the non-decimating filter based on the integer phase value. A weight generator generates M weights based on the fractional phase value, and a weight averager weights the M filtered samples by the M weights, and outputs a sum or an average of the weighted samples. The resampler is applicable to digital-to-digital resampling, as well as resampling in an analog-to-digital or digital-to-analog conversion system.
Fractional rate modulation conversion is accomplished by separating incoming data into frames of bits. Each frame is partitioned into bit words of unequal bit lengths. The words are divided by a modulus to obtain remainders. The remainders are then multiplexed into sequential bauds of common modulus. The apparatus can be used for data compression as well as efficient modulation in bandwidth restricted channels.
