A semiconductor memory device including a substrate having one conductivity type; read only memory element formed in the substrate for storing fixed information, the element having a control gate, a floating gate, a source region, and a drain region, both of the regions having an opposite conductivity type to that of the substrate; a first region having the above one conductivity type which surrounds the element; a light shield layer, connected to the source region and the first region, for covering the element; a second region having the opposite conductivity type which is located outside of the first region for taking out the drain region; and a well region having the opposite conductivity type, the well region linking the drain region and the second region, a part of the first region being formed in the well.
A semiconductor memory device having a redundancy memory cell array is disclosed. UV-PROM's are employed as a programming means in the redundancy control section. A first impurity region is formed in the substrate and the control gate electrode of the UV-PROM is led out through the first impurity region. A second impurity region is formed in the substrate and crosses the first impurity region, and the floating gate electrode of the UV-PROM is covered by a metallic film which is contacted to the second impurity region.
To avoid differentiation, in manufacture, between the random-access memory cells and read-only memory cells of the same memory array, the memory cells are all made by the same technology. These memory cells employ essentially floating gate transistors. The random-access memory cells are programmed, in a stand way, by injecting or not electronic charges in the floating gates of the transistors. The read-only memory cells are put in a programmed or an unprogrammed state by the selective implantation of impurities or not in the conduction channels of the floating gate transistors of these memory cells. There is an improved concealment of the content, which is designed to remain concealed, of these memory cells, at the same time, the conditions for making prototypes to order are improved.
A nonvolatile semiconductor memory device comprising a matrix array of memory cells, word lines for driving the rows of memory cells, bit lines for reading data from columns of memory cells, a plurality of first MOS transistors provided for these bit lines, respectively, a second MOS transistor having a source coupled to the bit lines by the first MOS transistors, a drain coupled to a VCC terminal, and a gate connected to receive a predetermined bias voltage, a row decoder for selecting one of the word lines in accordance with a row-address signal, and a column decoder for turning on one of the first MOS transistors in accordance with a column-address signal. The memory device further has a CE terminal for receiving a test-mode signal, an OE terminal for receiving first and second control signals, and a control circuit for detecting a test mode, thereby prohibiting the operation of the row decoder in response to the first control signal, and permitting the operation of the row decoder in response to the second control signal.
An unerasable memory cell (10) is formed in the face of a layer (22) of semiconductor of a first conductivity type and includes an erasable read-only memory cell (12) having a first source/drain region (16) and a second source/drain region (18) of a second conductivity type opposite the first conductivity type. First source/drain region (16) is spaced from second source/drain region (18) by a channel area (24). A floating gate conductor (20) is disposed insulatively adjacent channel area (24) and a control gate conductor (22) disposed insulatively adjacent floating gate conductor (20). A heavily doped moat (32) of the second conductivity type laterally surrounds memory cell (12). A load device (14/66) couples moat (32) with first source/drain region (16) of a memory cell (12). A shield (46/56) is provided having a first portion (47/64) spaced from and substantially parallel to the face of semiconductor layer (22) and a second portion (52/62) formed at an angle to the face and coupling the first portion (47/64) with moat (32). Shield (46/56) substantially encloses memory cell (12).
An integrated circuit chip includes a secure memory element that stores secret data, an opaque layer of material encapsulating the chip, and means for eliminating the secret data from the secure memory element in the event that the encapsulation material is removed from the chip. The eliminating means comprise a protective circuit encapsulated by the encapsulation material and coupled to the secure memory element. The protective circuit incldues a light sensitive element having a current characteristic that has a detectable change upon exposure to light; means for detecting said current change when the light sensitive element is exposed to light; and switching means coupled to the secure memory element and the detecting means for causing the secret data to be removed from the secure memory element in response to said current change produced by the light sensitive element when the light sensitive element is exposed to light, such that should the encapsulation material be removed from the chip, the secret data is eliminated from the memory element.
