Disclosed is a method utilizing dynamic masking for efficiently programming an N-bit memory array and, more generally, for mapping successive subsets of data segments into a succession of N-bit auxiliary bytes. When the number of programming bits in an incoming byte exceeds K, a mask maps the bit pattern of the incoming byte into sequential N-bit auxiliary bytes. A first auxiliary byte retains the bit pattern of the incoming byte up to the Kth programming bit, and the remaining bit positions of the first auxiliary byte exhibit a state complementary to the programming bits. A second auxiliary byte retains the bit pattern of the incoming byte starting with the first location after the Kth programming bit and continuing up to the Kth additional programming bit (if any); all remaining bit positions of the second auxiliary byte (including the bit positions that contained programming bits in the first auxiliary byte) exhibit the complementary state. Further auxiliary bytes can be created to accommodate all K programming bits, if necessary.

A memory for storing a reorganizing array of an initial array of data of binary ones and zeros to enable decoding of the reorganized array to reproduce the information content of the initial array, and the method of reorganizing the initial array. The memory includes a data circuit array that has a plurality of memory cells arranged in rows and columns for storing the reorganized array. The memory also has a plurality of flag memory cells and a row of XOR gates and inverters. The initial array is divided into sections. Each row of each section of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. Each column of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. This is repeated until each row in each section and each column has at least as many ones as zeros, producing the reorganized array. The reorganized array is stored in the data circuit array, and the flag bits corresponding to each row of each section are stored in the flag memory cells. Each XOR gate is connected to one column of the memory cells and to the column of the flag memory cells that correspond to the column of memory cells. An inverter is connected only to the columns whose corresponding flag bit is a one. In an alternative embodiment, the memory contains XOR gates and flag memory columns but not the inverters. In another alternative embodiment, the memory contains inverters but not the XOR gates or flag memory cells. A memory for storing the reorganizing array reduces the number of ones stored in the memory, reducing the memory's power consumption and increasing its access time.

A memory cell array of high density, enabling high speed read-out. Diffusion wires columnwise extending in a block in the array serve as bit and ground lines alternately disposed and gate wires parallel to each other are formed perpendicularly to the diffusion wires. Channels are defined in regions between the adjacent diffusion wires under the gate wires, whereby MOS transistors are formed. A memory circuit has such a memory cell array and a decoder connected thereto. Paired adjacent bit lines are connected through a bit line select transistor to a contact, and the contact is connected through a metal line columnwise connecting between blocks, via a transistor of decoder to a main bit line. Paired adjacent ground lines are connected through a ground line select transistor to a contact for ground line, and the contact is connected through a metal line columnwise connecting between blocks, via a transistor of decoder to a main ground line.

In certain exemplary embodiments, a memory device with optimized write sectors has a plurality P of memory write sectors and N memory spare sectors Cumulatively, the memory write sectors correspond to the specified storage capacity of the memory. The number N of spares is approximately equal to the number of write sectors expected to be decommissioned within an operational lifetime of the memory, which can be determined by empirical measurement. A method, by way of non-limiting example, of making memory includes specifying a plurality P of write sectors which define a specified storage capacity of a memory device, determining a number N of spare sectors, and making a memory device with about P write sectors and about N spare sectors. The number N can be determined, by way of example, by summing the infant mortality with the random failure of write sectors. One exemplary tool to determine infant mortality and random failure is to empirically create a cycle-based bathtub curve having infant mortality, random failure, and wear out regions.

A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.