A system for updating an ECC code over a line in a data store when only part of the line has been updated is described. The system receives the update and its address, decodes the address to generate a first signal identifying the part of the line to be updated and a second signal identifying an un-updated part of the section. The data of the update and the first signal are used to generate a first partial error code. Data from the un-updated part of the line is read as the update is written to the store. The data from the un-updated part of the section and the second signal are used to generate a second partial error code. Finally, the first and second partial error codes are combined to generate the updated error code.
A multiplicity of independently operating disk drive subsystems are coupled to a read/write interface containing error circuitry and data organizer circuitry. The data organizer circuitry organizes read/write data for read/write communication with the disk drive subsystems via the error circuitry such that the overall system appears as a large, high capacity disk drive system having an unusually high fault tolerance and a very high bandpass. Caching is additionally provided in the read/write interface in a manner which takes advantage of the organization provided by the data organizer to significantly improve overall performance. Advantage is also taken of the conventionally provided error detection capability of each disk drive subsystem to enhance the capability of the error circuitry.
The invention relates to a method and apparatus for checking data integrity in a data communications system in which plural data streams can be intermixed and wherein the data streams have a frame transmission format in which the frame is different than the logical block length of the data stream components. The integrity of the transmission process is checked without requiring system processor involvement, unless errors are detected. A first incoming data stream, composed of logical blocks, is received; and a running longitudinal redundancy check is calculated. If the data stream is interrupted at other than the end of a block, the intermediate value of the LRC is stored in a context storage associated only with that data stream. When the data stream continues, and this may occur after other data streams have been received, the intermediate value of the LRC is recalled from the context storage and the running longitudinal redundancy check calculation is continued. The storage and calculation steps continue each time the data stream is interrupted other than at a logical termination of a logical block for the data stream. The communications process is particularly applicable to mass storage subsystems in which the data streams are directed to and from the storage media.
A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.
A method and apparatus are provided for improving write throughput in a redundant array of mass storage devices using a cache memory to store redundant terms or code words generated when data is written to one or more devices in the array. The cache memory improves the write-throughput performance of the array by eliminating the need to perform a read-modify-write operation on check data stored in the mass storage devices of the array each time a write request is made. As a result, write-throughput of the system, particularly at peak demand periods, is improved.
In one embodiment, a system comprises a source configured to provide data and a source error correction code (ECC) generated according to a source ECC scheme; a circuit comprising an ECC transform unit configured to generate a target ECC from the data, detect an error in the data responsive to the source ECC, and correct the error in the data, wherein the target ECC is generated according to a target ECC scheme different from the source ECC scheme, and wherein the ECC transform unit is configured to continuously protect the data with at least one of the source ECC and the target ECC; and a target coupled to receive the data and the target ECC from the circuit.
