The present invention provides a novel system and method that permits a "mask" to be directly incorporated into an image during image processing. This is accomplished by processing binary images or image data which are encoded using two bits rather than the usual one. The second bit is defined to be a "mask enable", which directs a processor to pass the original data through to the output image regardless of the processing result for that pixel. The present invention also provides a means of automatically providing background data to the processor for pixels outside the original image so that the result image is always the same size as the original image. For binary images, the background may be defined to have a value of "0" or "1", and this value is provided to the processing engine in place of all of the pixels which lie outside the original image. For gray-scale images, the minimum or maximum possible value is provided to the processing engine in place of all of the pixels which lie outside of the original image, effectively eliminating these values from consideration when the minimum or maximum of the neighborhood pixels is computed. The determination of whether a pixel is outside of the original image is implemented using the framing signals provided by a data flow controller along with the image data.

A method for high speed morphological processing in a computerized image processing system starts by acquiring a binary image and selecting feature and height values corresponding to a desired morphological processing of an image. The image is scanned in a raster scanning sequence so as to produce a scanned image including a plurality of pixels. A sequential labeling transformation is performed on each of the plurality of pixels of the scanned image so as to produce a transformed image. A thresholding operation is performed on the transformed image. The resultant image is translated.

An image processing system and method are provided which use a selectively ccessed detector array comprised of subarrays. Regions of image activity are located within the detection array through readout of the activity determining elements. Each subarray is evaluated to determine whether any image activity has been detected by the corresponding subarray. Data is only read for the active subarrays. Thus, the activity indicator allows efficient transfer of relevant data from the detector array without requiring previous information. This results in reduced data flow and generally shorter readout cycles. The activity determination can be a non-destructive process so that data contained in the detection array remains available for sensor readout. This eliminates the need to perform one detector exposure cycle to determine activity and a second cycle to read out data from the detector.

The present invention provides a novel system and method that permits a "mask" to be directly incorporated into an image during image processing. This is accomplished by processing binary images or image data which are encoded using two bits rather than the usual one. The second bit is defined to be a "mask enable", which directs a processor to pass the original data through to the output image regardless of the processing result for that pixel. The present invention also provides a means of automatically providing background data to the processor for pixels outside the original image so that the result image is always the same size as the original image. For binary images, the background may be defined to have a value of "0" or "1", and this value is provided to the processing engine in place of all of the pixels which lie outside the original image. For gray-scale images, the minimum or maximum possible value is provided to the processing engine in place of all of the pixels which lie outside of the original image, effectively eliminating these values from consideration when the minimum or maximum of the neighborhood pixels is computed. The determination of whether a pixel is outside of the original image is implemented using the framing signals provided by a data flow controller along with the image data.

In an image processor system, a processor includes a first two-dimensional look-up table for receiving first and second digital data as an address, a second two-dimensional look-up table for receiving an output digital data of the first two-dimensional look-up table and a third digital signal as an address, and a latch circuit for temporarily storing the output digital data of the second look-up table. The processor is flexible and the functions thereof can be varied by changing the contents of the look-up tables.