The invention relates to a security device (1) prohibiting the execution of at least one function of an electronic data processing unit (2) after a first cutoff of its electric power even in the case of a resumption of supply voltage. This device includes a first means (8) that functions only once in the course of a period beginning at the instant (T.sub.0) of a first connection to voltage by the power supply (3), and finishing prior to the instant (T.sub.2) of a first cutoff of this power supply, and a second means (10) connected to the output of the first means (8) and furnishing an inhibiting signal having a first level that authorizes the function of the unit, from the instant (T.sub.0) of the first connection to voltage until the instant (T.sub.2) of the first cutoff, this inhibiting signal having a second level that prohibits said execution of said function beginning at the instant (T.sub.2) of the first cutoff, this inhibiting signal maintainin this second level even in the case of a resumption of voltage.
Systems for interchanging information, for example, obtaining cash from a terminal by use of a portable device such as a credit card are well-known but suffer from being vulnerable to fraud. In the invention a highly secure information interchange system is achieved by utilizing an intelligent card as the portable device which verifies that the terminal is a valid one and the terminal in turn verifies that the card is valid. Unauthorized users are screened out by means of a physical characteristic scan of the user such as a fingerprint which is then compared with comparable data stored on the portable device. If an invalid terminal attempts to communicate with the card, the card erases the data and programs from its memory. All programs and data in the terminal are stored in memory which loses its contents when power is interrupted, thus improving the security of the system by making unauthorized use of a terminal very difficult. The terminal can only be brought back up by authorized personnel with their own access portable devices. Both a system and a method are claimed.
A microcontroller communicating via a data path and an address path with a memory block containing encrypted contents, the microcontroller including the capability for detecting resets effectuated in the wake of an unauthorized attempt to gain access to the encrypted contents and the capability of evading such an unauthorized attempt.
A method, system and computer readable medium containing programming instructions for detecting a tamper event in a computer system having an embedded security system (ESS), a trusted operating system, and a plurality of devices is disclosed. The method, system and computer readable medium of the present invention provide for receiving a tamper signal in the ESS, and locking the tamper signal in the ESS. According to the method, system and computer readable medium of the present invention, the trusted operating system is capable of detecting the tamper signal in the ESS.
A system and method for monitoring a security state of a portable electronic device (PED), such as a personal digital assistant (PDA), are provided. A security state may be determined by physical or electronic characteristics of the PED. The relative position of PED pieces, the position of a latch, and/or the status of a software application may determine a security state. Furthermore, a PED may have open, closed, and partially open security states. Information about a current security state of a PED may be transmitted to a point-of-sale device (POS), system processor, and/or financial institution. The PED or any of these other devices may use this information to determine whether to allow or restrict a financial transaction involving the PED. Additionally, a software program on the PED may be allowed or restricted from running depending on the information about the current security state.
A protected configuration space is implemented as at least one range of memory addresses that are mapped to logic external to system memory. The memory addresses access logic that performs control and status operations pertaining to a protected operating environment. Some of the addresses may access protected configuration registers. Commands having destination addresses within the protected configuration space may not be completed if the commands are not issued by a processor, or if the commands are not part of a group of one or more designated protected commands. A separately addressable non-protected configuration space may also be implemented, accessible by processors, non-processors and/or non-protected commands.