A video display system is provided which compensates for video processing delays in multiple, inter-coupled video processing subsystems. The video display system is comprised of multiple video processing subsystems, each having a video bus for coupling video data between individual ones of the multiple subsystems. Each subsystem is adapted to receive one or more video data inputs and to selectively and programmably process the one or more video data inputs to provide a video data output. Each subsystem is comprised of a video delay subsystem coupled to an external video source and to the video bus. The video delay subsystem adds a programmable time delay to its respective external video source input data prior to coupling it to its respective processor for processing of video data contained within that respective video processing subsystem. The programmable delay adequately compensates and time correlates its external video source input and the video bus coupled video input prior to providing those data signals to be selectively processed (blend, fade, mix, etc.) to provide its respective video data output, responsive to control signals received from either the video bus or the main computer bus. The external video source can be any of a number of video sources. Video data output from a first subsystem is coupled via the video bus to one or more other subsystems. The video bus couples video data and control signals amongst the multiple video processing subsystems.

When dividing a video signal composed of horizontal H pixels and vertical V pixels into blocks of (m.times.n) pixels composed of horizontal m pixels and vertical n pixels, when the number of horizontal pixels or the number of vertical pixels is not equal to an integer multiple of m or n, respectively, the video signal is first divided into blocks of (m.times.n) pixels and sub-blocks of a smaller size. Then, a plurality of sub-blocks are put together to make up a block of (m.times.n) pixels.

The invention describes a processor system suitable for processing video signal samples on a real-time basis. Signals are derived from the samples for driving an imaging unit. For this purpose, one or more processor modules are provided with processor elements, operating in parallel in time, which are connected to a crossbar switch. A module contains at least one arithmetic/logic processor element and at least one memory processor element. Moreover, there is a clock device, the frequency of which bears a fixed relationship to the frequency with which the video signal samples are obtained.

Reference frames are generated by selectively filtering blocks of decoded video frames. The decision whether to filter a block is based on a comparison of an energy measure value generated for the block and an energy measure threshold value corresponding to the quantization level used to encode the block. The energy measure threshold value for a given quantization level is selected by analyzing the results of encoding and decoding training video frames using that quantization level. The reference frames are used in encoding and decoding video frames using interframe processing.

The complexity of a plurality of signals in a first domain are characterized. A transform is selected in accordance with the complexity of the plurality of signals, wherein the selected transform is one of a plurality of transforms having differing complexities. The selected transform is applied to the plurality of signals to generate a plurality of transformed signals in a second domain.