A mask ROM of the invention discharges bit lines selectively before a bit line precharge operation in response to an externally applied command. A column decoder selects one of bit lines in response to column select signals. A discharge control circuit generates a first discharge control signal in response to the command. A discharge predecoder generates a plurality of second discharge control signals by logically combining the first discharge control signal with the column select signals. A bit line discharge circuit selectively discharges the bit lines in response to the second discharge control signals. The mask ROM is free from bit line coupling due to the selection of particular memory cells, the cell selection sequence and the programmed states of the selected cells, leading to an improvement in read speed.

A CMOS DRAM has an array in a well which is pumped to a voltage greater than the power supply voltage. The transfer devices of the memory cells in the array are of a conductivity type opposite to that of the well. The transfer devices each have a source/drain of the opposite conductivity type to that of the well which is connected to a bit line. The bit line will tend to rise in voltage at power-up which has the potential of forward biasing the PN junction between the source/drain and the well. The bit line rise is due to a word-line rise the rate of which is controlled so that the bit line rise does not exceed the rise in array voltage. The bit lines are ensured of being separated in voltage at the beginning of the first active cycle by enabling the N channel portion of the sense amplifier during power-up. The P channel portion of the sense amplifier is disabled during power-up to avoid too rapid of a rise in voltage on the bit lines. Equalization of the bit lines is suppressed during the first cycle to avoid having the sense amplifier face the high current drain condition of little or no voltage differential at low voltage.

A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

A sense amplifier circuit for use in a ROM comprises, an excess charge detecting circuit for producing a detection output when a potential of a bit line exceeds a normal value, and an excess charge discharging circuit which operates in response to said excess charge detecting circuit for discharging a bit line charge and for returning the bit line potential to the normal value. The excess charge detecting circuit and the excess charge discharge circuit can be realized by a diode connected transistor connected between the bit line and an inverter of the sense amplifier. When the bit line potential is about to exceed the predetermined value, the transistor turns on to prevent the bit line potential from exceeding the predetermined value.