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Description  |
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BACKGROUND OF THE INVENTION
This invention relates to a method and system for displaying visual
information on a screen by line by line and point by point sweeping.
Some methods and systems of this type are described in the following
patents and patent applications:
FR No. 2 406 250, EP No. 0 055 167, EP No. 0 056 207, EP No. 0 055 168, EP
No. 0 054 490, and U.S. applications Ser. No. 583,072 filed Feb. 23, 1984
and assigned to Texas Instruments Incorporated, U.S. Pat. No. 4,623,986
issued Nov. 11, 1986 and assigned to Texas Instruments Incorporated, and
U.S. Pat. No. 4,620,289 issued Oct. 28, 1986 and assigned to Teas
Instruments Incorporated.
These prior systems teach a method for displaying visual information on a
screen by line by line and point by point frame sweeping, including:
(a) Controlling all the operations of image display and composition by
means of related address and data fields provided by a programmed central
processing unit, this central processing unit cooperating with a memory
and a video processor by a multiplexed time sharing data and address bus
for preparing each frame and displaying it on said screen.
(b) Controlling access to said memory as a function of predetermined
priorities with a dynamic access circuit for the memory.
(c) Assigning to certain addresses in said address fields an instruction
function for the video processor so that it can utilize the consecutive
data field at this address for its own needs.
(d) Distributing the consecutive data fields, as a function of the address
field assignment, either to the memory or to said video processor.
In the method described in the above cited patent application No. 83 03
142, a data field, following an address field interpreted as an
instruction for the video processor can be reused as many times as
necessary without the intervention of the central processing unit, the
video processor operating on a series of consecutive addresses from the
initially provided address, calculating them in its own calculation unit.
Such a repetitive operation can be useful, for example, in preparing in
the memory a page to be displayed in which a large portion is made up of a
single background color. In these conditions, the data representing this
color can be loaded into the adjacent emplacements of the memory by
increasing each time the address by a unit, all of this being controlled
by the memory dynamic access control circuit.
This procedure entails the considerable advantage of discharging the
central processing unit from a part of its task and thereby gaining a
considerable amount of processing time. A central processing unit
consisting of a microprocessor has a cycle time in the order of one
microsecond, while the access time to the memory, if it is effected by the
video processor, is about one hundred nanoseconds.
It would therefore be desireable to release the central processing unit of
all of its "secondary" tasks, which are not directly connected with the
control of the system, as, for example, the animation of a part of the
image, changing a form, rotating a part of an image, etc.
SUMMARY OF THE INVENTION
The invention has therefore, as an object, an improvement in the method
described above whereby there is an augmentation in the image processing
and composition possibilities by the video processor and thus an even
greater liberation of the central processing unit so that the CPU can
concentrate practically exclusively on system control.
The invention has therefore, as an object, such a method which is
characterized in that it also includes:
(a) Determining, from the value of the address field itself, if this
address is an instruction code for the video processor or a direct access
address from the central processing unit to the memory.
(b) Assigning, to certain of said values, an operation mode called a
"foreground" mode, by means of which the central processing unit can place
the consecutive data into said video processor with a higher priority
determined by said access control circuit.
(c) Assigning, to certain others values of the address field interpreted as
an instruction, an operation mode called "background" mode by means of
which said central processing unit effects, based on the contents of the
consecutive data field, a series of memory cycles to be executed by the
video processor with a lower priority determined by said control circuit,
with addresses which this processor itself processes from data previously
provided to it from the central unit.
(d) Interrupting the execution of said series of cycles in the video
processor when said central unit again provides an address field, the
contents specifying the "foreground" operation mode.
Because of these characteristics, it is possible to process data and data
groups in the video processor at its own speed without intervention of the
central processing unit which retains initiative over system control by
interrupting the execution of a series of operations in progress in the
video processor if the CPU, itself, wishes to access the processor.
According to another aspect of the invention, the method also consists,
during the interruption in execution of a series of operations of the
background mode type, in memorizing the last address and data fields in
the process of execution in the video processor and continuing this
execution after termination of a control cycle by said central unit in a
foreground mode.
In this case as well, the video processor has total control over the
execution of a series of operations without the intervention of the
central unit.
According to another aspect of this invention, the method includes loading
in advance a series of instructions into said memory and executing these
instructions in a background mode in the video processor without the
intervention of the central unit.
This particularly useful feature allows program loops in a mode called a
"task" mode at the processing speed of the video processor while the
central unit operates independently with its own program, for example, in
effecting figure displacements on the screen, incrustations, and other
manipulations relating directly to system management.
The invention also has as its object a visualization system on a video
screen in a graphic mode in which the visual information to be displayed
is defined on the screen by line by line and point by point sweeping of a
frame, this system including:
a memory with direct access to at least one zone in which is stored at any
given instant the information necessary for the display of a frame.
a central processing unit for composing the information to be displayed.
a video display processor for processing a part of the information provided
by said central unit and for preparing display images from this
information with said memory.
a communication bus interconnecting said memory, said central unit, and
said video display processor.
a control circuit for dynamic access to said memory for time allocating all
of the accesses to the memory as well as the transfer of information on
said communication bus.
an interpretation means for interpreting the information provided by the
central processing unit so that certain of said address fields are
interpreted as instructions for the video display processor,
including the means for transforming a field in question either into a
foreground instruction, the execution of which is ordered immediately as a
function of a priority order for memory accessing determined by said
control circuit, or into an instruction of the background type entailing a
plurality of successive access cycles to the memory but whose execution is
ordered with a lower priority after execution of all foreground
instructions, said access control circuit being capable of interrupting
the execution of a series of cycles of the background type when a cycle of
the foreground type is to be executed.
The invention will be more completely described in the description which
follows, given as an example, and in reference to the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified schematic of a data visualization system on a video
screen according to the invention.
FIG. 2a and FIG. 2b are more detailed schematics of this system.
FIG. 3 is a diagram showing the address field which circulates over the
central processing unit bus.
FIGS. 4a and 4b are timing diagrams illustrating the operation of the
foreground and background modes assigned to information from the central
processing unit.
FIGS. 5 to 9 are much simplified diagrams of the system according to the
invention illustrating circulation of the address and data information in
the various system configurations.
FIG. 10 illustrates direct access of the central processing unit for
writing data into the general system memory.
FIGS. 11 and 12 are time diagrams illustrating the operation of the direct
access represented in FIG. 10.
FIG. 13 is a diagram analogous to that of FIG. 10 illustrating the
operation of a writing access to the address processor by the central
processing unit.
FIGS. 14 and 15 are time diagrams illustrating the operation of FIG. 13.
FIG. 16 is a much simplified schematic of a system according to the
invention illustrating indirect access of the central processing unit to
the general system memory.
FIG. 17 is a diagram of address progression in a general access of the
system memory.
FIG. 18 is a diagram analogous to that of FIG. 10 showing the circulation
of information during an access to the general memory in accordance with
FIG. 17.
FIGS. 19 and 20 are time diagrams relating to the operation of an access
according to FIG. 18.
FIG. 21 is a diagram analogous to that of FIG. 10 representing the
operation during the loading of a background instruction into the central
processing unit interface.
FIGS. 22 and 23 are time diagrams illustrating the operation of FIG. 21.
FIG. 24 is a diagram schematically depicting the preparation of the display
of an image zone in the memory.
FIG. 25 is a diagram representing a part of the inventive system at the
initialization of a memory zone of the point processor.
FIG. 26 is a time diagram relating to the operation seen in FIG. 25.
FIG. 27 is a flow chart.
FIG. 28 illustrates the "task" operation mode of the video processor, VDP.
FIG. 29 is a time diagram illustrating the "task" mode.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows a much simplified schematic of a display system using the
point processor according to the invention. This system includes several
units, namely:
A central processing unit 1, CPU, which controls all the operations of the
system by means of a program stored in the CPU's memory.
A video display processor 2, VDP, which communicates with the CPU by bus 3
and control line 4, the address and data information circulation on bus 3
being time multiplexed according to the process described in French patent
application No. 83 03 142, filed Feb. 25, 1983, by the instant applicant.
A dynamic random access memory 5, DRAM, which communicates with the other
units of the system by bus 6 in time sharing, this bus being connected to
CPU 1 over interface 7.
A display unit 8 which can be a conventional television or a conventional
monitor, this unit being adapted to display the visual information process
in the system according to the invention by means of, for example, a
cathode ray tube.
An external unit 9, or didon, by means of which the inventive system
communicates with an external information source which might be, for
example, a teletext emitter connected to the system by, for example, a
radio transmitted television channel, or by a telephone line, or
otherwise. The external unit 9 loads the information into memory 5 to
effect, after processing in the system, the display of the information on
the screen of display unit 8.
The video display processor includes an address process 10, a point
processor 11 for operating on the points of the screen of unit 8, to
obtain, for example, changes in the image form, and a display processor
12, these units all communicating over time sharing bus 6, and bus 13,
over which only data can circulate.
Buses 6 and 13 are connected to DRAM memory 5 over interface 14 which
multiplexes the data and addresses destined for DRAM 5. There is also
provided a control unit 15 with dynamic access to DRAM memory 5. This unit
is described in detail in French Pat. No. FR -A-2 406 250 and in French
patent application No. 83 03 143, filed Feb. 25, 1983, by the instant
applicant, and this unit will be referred to, hereinafter, as DMA circuit
15. In addition, there is provided a time base circuit BT associated with
the display processor and communicating with DMA 15, television monitor 8,
and the display processor itself. There is a detailed description of the
display processor in French patent application No. 83 06 741 filed Apr.
25, 1983, pk by the applicant.
It has been indicated above that CPU 1 communicates with VDP 2 over a
single multiplex bus 3 which carries information under control of the
signals themselves transmitted on line 4 in such a way that the addresses
which are transmitted over this bus can be used, on the one hand, as
addresses for DRAM memory 5 when CPU 1 communicates directly with this
memory, and by means of which the consecutive data field is utilized to
read or write in the memory, or, on the other hand, as an instruction
field placing VDP 2 into a particular configuration for processing the
data contained in the consecutive data field.
More specifically, in the said French patent application No. 83 03 142, the
information which passes over bus 3 each have two information fields, the
first, enabled by signal AL (address latch), transports either an address
for the direct accessing of DRAM 5 or an instruction which is adapted to
be interpreted by VDP 2. The second field enabled by the signal EN
(enable) contains data which traverses the bus in one of two directions,
the direction being determined by signal RW (read/write). With the first
field, (address for the memory or interpreted instructions), the data can
be sent to the memory or can come from it, or can be utilized by VDP 2
placing it in one of its two processing configurations.
DRAM 5, in the system here described, is a composite memory having a
plurality of zones, addressed starting from a base address. This memory is
composed of at least a page memory 5a, memories for the control of lines
and columns 5b and 5c (see, in this regard, the patent application filed
the same day as the instant application in the name of the instant
applicant for a "Display System for Video Images on a Screen by Line by
Line and Point by Point Sweeping), at least one zone memory 5d, at least
one form memory 5e, typographic character memories 5f, a buffer memory 5g,
which adapts the various processing speeds to each other, in particular,
that of central processing unit 1 and external channel 9 (see, in this
regard, EP-A N0. 00054490), and, optionally, a memory 5h programmed in
assembly language, for CPU 1, etc.. All of these memory zones can be
accessed by the internal units of VDP 2 and by CPU 1, these accesses being
controlled either by the CPU 1 itself or by the device for dynamic access
to memory 15 (see, in this regard, FR No. 83 06 741). In order more easily
to understand following description, it is useful briefly to review the
operation of DMA circuit 15.
This circuit distributes access times to DRAM 5 depending upon the priority
of the users of the system, that is, CPU 1 and the various units of VDP 2.
DMA circuit 15 can be requested by each of these users to access the
memory, either in a single cycle (monocycle) or in a series of consecutive
accesses (multicycle). In this latter case, DMA 15 can control a
particular number of accesses to the memory by a column access signal
(CAS), while utilizing only a single row access signal (RAS). This is
particularly useful, for example, when this system prepares the display of
an entire page on the screen, and it is necessary to access a very large
number of memory positions, which are contiguous, and in regard to which,
it is only necessary to increment the column address each time by a single
unit, with the row address remaining the same for all accesses of this
row. It is to be noted that all access procedures of memory 5 are
determined by DMA circuit 15.
There will now be examined in more detail the schematics seen in FIGS. 2a
and 2b.
Interface 7 selectively connects CPU 1 to VDP 2 for indirect accessing, or
to DRAM 5 for direct accessing. It is capable of interpreting each address
field.
FIG. 3 shows an example of the 16 address field distribution with 16 bits.
When the field value is between (in hexadecimal) >0000 and >FEFF, this is
a direct access to DRAM 5; however, when this value is between >FFOO and
>FFFF, the field is interpreted as an instruction enabling the registers
for writing or reading via a vis the consecutive data field.
In this regard, the interface includes decoder 16 connected to bus 3 and
having 16 outputs, 4 of which, namely, those corresponding to the two
least significant bits, are used to enable the four registers of the
interface. These registers are:
Address transfer register 17 enabled by signal ENCPUA.
A data transfer register 18 enabled by signal ENCPUD.
A state register 19 (status) enabled by signal ENST.
A control register 20 enabled by signal ENCT.
These four registers are controlled for reading and writing by signal R/W
(for writing R/W=0) which is applied to their corresponding control
inputs.
Consequently, when there is a direct access to CPU 1, decoder 16 generates
address transfer signals ACLPU and ENCPU. For writing (R/W=0), the
consecutive data field is transferred to register 18 while, for reading
(R/W=1), the contents of this register are transferred at the cycle end on
bus 3 so that CPU 1 can access the corresponding data read in DRAM 5.
Decoder 16 also includes an output REQCPUF which requests, in DMA 15, an
access cycle to DRAM 5. This output is connected to DMA 15 to allocate a
memory cycle (signals RAS and CAS) to CPU 1. This cycle provides for
transfers between CPU 1 and DRAM 5 over bus 6.
In the second case, if the address field has a value between >FF00 and
>FFFF, the field is interpreted as an instruction.
These instructions can be principally divided into two groups called
foreground instructions and background instructions, respectively
abbreviated as FG and BG.
It has been seen that, among the interpreted addresses, four addresses
selectively designate the four register 17 to 20 of interface 7. For this,
the last two bits of the address field can be used according to the
following truth table:
______________________________________
RCTL WCTL 00 Register 20
RST WST 01 Register 19
RCD WCD 10 Register 18
RCA WCA 11 Register 17
______________________________________
(R designates a read signal and W a write signal).
The other instructions resulting from an interpreted address, which are
256-4=252 in number, with the least significant 8 bits of the address
field (FIG. 3), are adapted to execute cycles FG by register FG 21 which
is a part of interface 7 and which is connected between certain outputs of
decoder 16 and address processor 10 and to the address inputs of read only
memory CROM 22 which is a part of this processor.
Register 23 of interface 7, called register BG, is loaded with instructions
BG when it is designated by an address field, the interpretation of which
calls upon one or several BG cycles. The designation of this register is
made by the three least significant bits of the address field and,
specifically, when these bits have the value 111. (Address field >FFO7).
When register BG 23 is selected, the consecutive data field contains a 16
bit instruction which places the VDP into a configuration for the
execution of a large number of memory cycles under control of DMA circuit
15, these cycles being processed successively unless the instructions FG
interrupt this process. In this case, the DMA allocates one or FG cycles
which are executed and then cycles BG are resumed where they had been
interrupted, the process of interpretation as a function of the access
priority to the memory being described in the above cited patent
application No. 83 03 143.
The address processor, besides memory CROM 22, includes two register stacks
24 and 25 called NRAM and PRAM which are loaded and read in 16 bits via
transfer register 26 connected to time sharing bus 6. Each stack is
connected to arithmetic and logic unit ALU 27, which is itself connected
directly to bus 6 by transfer register 26 and to two 16 bit buses 28 and
29, N and P. The address processor is used principally to provide and
calculate all of the address generated by the VDP for accessing memory 5.
Memory 22, when it is addressed by a part of the instruction contained
either in register 21 FG or in register 23 BG, selects a microinstruction
here stored to enable one or more registers of stacks 24 and 25, an
arithmetic or logical operation in ALU 27, and transfer by register 26.
The operations of ALU 27 are controlled by five bits of the
microinstructions which can select the remainder (Cl=0,1, or 2) and an
addition or subtraction operation on bus P or N, 28,29, or between these
two buses.
Control memory CROM 22 also provides the signals for controlling the other
units of VDP 2 for the transfer of data and addresses between the various
buses and registers. The microinstructions addressed in CROM 22 are
enabled in time sharing by DMA 15 on line 30 for establishing a relative
priority order for memory accessing. In the case here discussed, six
priorities are established in the order:
1. CPU - FG
2. External path (didon 9)
3. Display control
4. Display (display processor 16)
5. Reload memory 5
6. CPU BG.
From the above it is seen that the foreground cycle FG is used by CPU 1 for
direct access to the memory, or to access the internal registers of VDP 2,
for exchanging, with the memory, a single 16 bit word at a time. This is
illustrated in FIG. 4a.
Background cycle BG is executed with a lower priority, that is, when VDP 2
does not have other cycles to execute for other users. The BG cycle is
started either by the CPU by cycle FG (FIG. 4b), or by VDP 2. When it is
the CPU which starts such a cycle or group of cycles, there can be, for
example, a displacement of a group of words in memory 5, this operation
being executed without the CPU intervening again after the cycle FG, so
that the CPU can continue to process FG during the execution of the BG
cycles, all of this being controlled by DMA 15 in the established priority
(in this case there will be an interruption and then a restarting of the
execution of the BG cycles).
The considerable advantage of this arrangement is that various users can
work and communicate at their own speed, without being interferred with by
other users, the DM effecting the appropriate priority in all cases.
Interface 14 of DRAM 5 includes two transfer registers 31 and 32 controlled
by the signals provided by the microinstructions of memory CROM 22 and by
signals RAS and CAS from circuit DMA 15 to transfer the data and address
fields of bus 6 to the DRAM or vice versa. The data can also be
transferred directly into memory 5 from bus 13 to addresses transferred
over bus 6 and register 32 from address processor 10.
There will now be described the various operation modes of the system
according to the invention with reference to FIGS. 5 through 9.
Thereafter, FIGS. 10 through 24 will illustrate a certain number of
concrete examples of information processing and the exchange between
various units of the system.
In FIGS. 5 to 9, data and addressing streams are indicated by arrows.
FIG. 5 shows direct access to DRAM memory 5 without utilizing the 256
instructions of the address field reserved for the VDP. This operation
mode allows the CPU directly to execute a program written in assembly
language or directly to access the data contained in DRAM 5.
The access address comes directly from address registers of CPU 1 which
starts its cycle as if DRAM 5 were directly connected to the CPU bus. The
access cycle of DRAM 5 is directly generated by DMA cicuit 15, FIG. 2a, by
decoder 16 and signal REQ CPUF, the path selected being that of the
highest priority (cycle CPUFG).
FIG. 6 illustrates access by CPU 1 to registers of VDP 2. The reserved
field of 256 addresses in the address field is interpreted as an
instruction for VDP 2 and allows accessing for reading or writing to all
of the internal registers of the VDP. CPU 1 can thus prepare for future
accesses to the DRAM (executed, in particular, in BG cycles) by loading
the registers of the VDP with the pointer values, the address increments,
the comparison addresses, etc.. It is also possible to program the
parameters of the time base BT (FIG. 2b), for example to adapt them to the
television norms to be utilized, the base colors of the color palette of
the display processor 12, and others, in order to prepare an image to be
displayed on the screen for initializing the VDP at the start of
operations.
FIG. 7 illustrates an indirect access mode to the memory by a pointer of
address processor 10. Certain instructions of VDP 2 (interpreted address
field) access DRAM 5 utilizing these pointers. The instruction interpreted
by decoder 16 selects a pointer by CROM memory 22 (FIG. 2a) which contains
the access address to DRAM 5. During the execution of the cycle, the
address processor 10 calculates the next access address as a function of
the interpretation of the instruction code and the incrementation
paramaters which are programmed by the CPU.
In writing, the data sent by CPU 1 is loaded into DRAM 5 at the selected
address. In reading, the value read in the DRAM at the indicated address
is transferred at the end of the cycle on bus 3 to CPU 1.
This access also uses the path CPU-FG of DMA circuit 16.
FIG. 8 illustrates access in the BG mode (background).
In these three cases (FIGS. 5 to 7), each instruction or access processes a
single word of 16 bits in a monocycle utilization. For example, to copy or
transfer a block of 16 words of 16 bits, the code of the instruction
generated by CPU 1 must be repeated 16 times.
The access mode BG executes instructions relating to a series of words by
generating, by means of CPU 1, only a single instruction. For example, one
can load 10 words of 16 bits with a constant value, or with a frame
contained in the point processor 12, or one can displace a memory zone to
a different address, by means of a single instruction FG ordering a BG
procedure.
Before executing the instruction, the parameters must be loaded into VDP 2.
Instructions in the BG mode are executed with the lowest priority, that is,
all of the accessing request of a higher priority interrupt their
execution.
Generally, instructions utilize point processor 12 to effect data
transfers.
It is recalled that the operation mode BG allows the increasing of the
image processing speed and reduces the work load of the CPU.
FIG. 9 shows another possibility obtained with a particular arrangement of
the inventive system. In the preceding cases, each instruction, which
executed operations of several cycles, was generated by CPU 1. Be each
execution, new instruction parameters must be generated and loaded into
VDP 2 by this CPU. The program execution mode VDP (task) illustrated in
FIG. 9 executes a program in VDP language directly under control of
address processor 10. For this, a program is preloaded into DRAM 5 by CPU
1 or is contained in program library zones, or in a ROM in one portion of
system memory 5 which the CPU can call upon (this portion not illustrated
in the figures).
An instruction code generated by the CPU transmits, to VDP 2, the program
start address and the execution commencement order.
The address processor obtains VDP instructions from program pointer PC and
successively executes BG type instructions.
These programs or tasks can be called upon to execute operations which
occur often in the system control. They allow the obtainment of a
considerable time saving and reduce the CPU load.
Other ways of accessing DRAM 5 are possible, particularly by the external
path (FIG. 9), or by the time base for display. These modes are not
described in detail here
There will now be examined FIGS. 10 to 11 which show a specific example of
direct access of DRAM 5 by CPU 1. As mentioned above, such an access
commences when the contents of an address field on bus 3, enabled by
singals AL, EN, and R/W is between >0000 and >FEFF. Circuit DMA 15
controls such as access.
In the example of FIG. 10, the value >5555 is written at address >F37E.
This operation procedes as follows.
Signal AL, which accompanies the address field on bus 3, generates signal
ALCPU by decoder 16 for address register 17 to which address F37E is
therefore transferred. Decoder 16 also generates signal, WCPUD, which is
applied to register 18 upon the appearance of sign | | |
