Semiconductor defect monitor for diagnosing processing-induced defects

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a semiconductorprocessing defect monitor for diagnosing processing-induced defects.

2. Background Art

An ongoing concern in semiconductor technology, as well as any manufacturing technology, is the maximization of manufacturing yield. One phenomenon contributing to less than optimum manufacturing yields in semiconductor fabrication is that of processing-induced defects. These processing-induced defects cause within semiconductor circuits physical defects which, in turn, cause product failure. By way of example, these processing-induced defects have often been found to cause circuit failure due to open circuits in conductive lines, short-circuits between adjacent conductive lines, and short-circuits between overlying conductive lines at different planar levels. The causes of these processing defects are numerous, e.g., temperature variation, dust contamination in the work area, insufficient disposition of insulation layers, etc.

Analysis of processing-induced defects can be very useful in the prediction and improvement of manufacturing yield. It was found that the use of actual semiconductor products was not practical for the analysis of processing defects, because, in this era of Very Large Scale Integrated Circuits (VLSIC), a semiconductor device typically must undergo an extensive and complex testing procedure before it is found defective. Other than labeling the device as defective, this testing procedure typically yields little additional information as to the number of processing defects which have occurred, and, more important, yields little additional information as to where the defects can be located and visually inspected.

As a result of the above shortcomings, the trend in the semiconductor industry is to fabricate specialized semiconductor-processing defect monitors which have no use other than for the diagnosis of processing defects. Such defect monitor circuits are typically constructed separately from actual VLSIC devices and are discarded once useful defect information has been extracted from them. Typically, one of two approaches may be taken in utilizing these defect monitors.

A first manufacturing approach is periodically to process semiconductor wafers which are dedicated solely to the fabrication of defect monitors. These dedicated wafers are processed in the same processing environment as actual VLSIC devices (although at different times), and are then subjected to diagnosis to determine the defect density and the particular types of induced defects.

A second, more accurate manufacturing approach is the fabrication of defect monitors on the same wafers on which actual VLSIC devices are fabricated. The advantage of this approach is that the device monitors are fabricated in exactly the same processing environment and at exactly the same time as actual VLSIC devices. Thus, the processing defects induced on these defect monitors will be more accurately indicative of the processing defects induced in the actual products. In this approach, the defect monitors are typically fabricated within the kerf or discardable portion of the semiconductor wafer.

The design of a semiconductor-processing defect monitor can be varied in a number of ways to test for different failure types resulting from processing-induced defects.

As a first example, FIG. 1A shows a defect monitor having a simplified continuity-monitoring pattern. A line 6, which is shown connected to test contact pads 2 and 4, is made of a conductive material and is configured in a serpentine layout. After the fabrication this continuity-monitoring pattern by semiconductor-processing, electrical connections can be made to the test contact pads to test for continuity between the pads. If a processing variation has caused an open circuit defect along line 6, then an electrical discontinuity between the test contact pads will be indicated. In the design of the continuity-monitoring pattern of FIG. 1A, it should be noted that statistical calculations are often used to choose a length and width of line 6 such that there is a high probability of only one defect occurring along the line, thereby maintaining a one-to-one correspondence between the occurrence of a defect and the occurrence of a monitor failure so that the defect distribution density across a semiconductor wafer can be accurately determined. Finally, it should be noted that FIG. 1A is a simplified illustration of a continuity-monitoring pattern; i.e., a practical continuity-monitoring pattern would typically encompass a much greater length and complex serpentine structure, and would occupy a large area of a semiconductor layer.

As a second example, a defect monitor can also be designed to include a short-circuit monitoring pattern as shown in FIG. 1B. In FIG. 1B, test contact pads 10 and 14 are shown connected to bus bars 12 and 16, respectively, which in turn, are shown are connected to finger projections 11, 13, 15 and 17, 19, 21, respectively. These structures are all formed of a conductive material and are typically on the same planar level. In the construction of such a short-circuit monitoring pattern, the main objective is to test for processing-induced short-circuits between closely spaced parallel lines. If the processing variation has induced a short-circuit defect between two adjacent finger projections, the defect will be indicated by electrical continuity between the test contact pads 10 and 14. The space 18 represents a "minimum ground rule" spacing between adjacent finger projections 11 and 17. Similar minimum ground rule spacings are provided between the other adjacent finger projections. Statistical calculations can again be used to design an appropriate number of finger projections and to determine the minimum ground rule spacings, so that there is a high probability that only one process defect will occur per short-circuit monitoring pattern, thereby maintaining a one-to-one correspondence between the occurrence of a defect and the occurrence of a monitor failure to permit an accurate determination of the defect distribution density across the semiconductor wafer. Finally, it should also be noted that FIG. 1B is a simplified illustration of a short-circuit monitoring pattern; i.e., a practical short-circuit monitoring pattern would typically encompass a tremendous number of finger projections and would occupy a substantial semiconductor layout area.

As a third example, a semiconductor-processing defect monitor can also be constructed, as shown in FIG. 1C, to monitor for short-circuits between conductive lines on different planar levels. In Figure 1C, there is shown an upper conductive level 22 separated from a lower conductive level 20 by an insulating layer 24. The main object of such a defect monitor construction is to test for processing-induced short-circuits between overlying conductive levels. Typical insulating layer defects which can be induced during processing include localized thinning or absence of insulating material, porosity and/or pin holes in the insulating layer. If the processing variation induces a defect in the insulating layer 24 such that a short-circuit occurs, electrical continuity will be found to exist between the upper and lower conductive levels 22 and 20. Finally, it should again be noted that the defect monitor shown in FIG. 1C is a simplified illustration; i.e., a practical defect monitor would typically be much more complex to provide for testing for short-circuit occurrences between numerous planar levels.

The above semiconductor-procesing defect monitors are disclosed and further described in IBM Technical Disclosure Bulletin, Volume 17, No. 9, dated February 1975, and authored by Ghatalia and Thomas.

In addition, there are numerous other prior art references directed towards the construction and use of semiconductor-processing defect monitors.

For example, U.S. Pat. No. 3,983,479--Lee et al, assigned to the current assignee, discloses a defect monitor using a combination of continuity and short-circuit test patterns along with diode-mode FET amplifiers, such that testing can be made for defects without interference between adjacent patterns.

IBM Technical Disclosure Bulletin, Volume 20, No. 8, dated January 1978, and authored by Hallis, Levine and Scribner, discloses parallel serpentine test patterns having a first portion which is horizontally oriented, and a second portion which is vertically oriented, such that the defect monitor is sensitive to defects induced in the horizontal as well as the vertical direction.

IBM Technical Disclosure Bulletin, Volume 17, No. 12, dated May 1975, and authored by Cassani and Thomas, discloses a defect diagnostic circuit composed of an orthogonal array of metal lines and diffusion lines which can be diagnostically tested for various defects by selectively activating different transistors associated with each of said lines.

Additional references providing background for this technology include: U.S. Pat. No. 4,459,694-Ueno et al; U.S. Pat. No. 4,320,507-Fukushima et al; U.S. Patent No. 4,471,483-Chamberlain; U.S. Pat. No. 4,454,750-Tatematsu; U.S. Pat. No. 4,428,068-Baba; U.S. Pat. No. 4,061,908-de Jonge et al; U.S. Pat. No. 4,393,475-Kitagawa et al; U.S. Pat. No. 4,458,338-Giebel et al; U.S. Pat. No. 4,466,081-Masuoka; U.S. Pat. No. 4,468,759-Kung et al; Japanese Patent No. 97,334; and Japanese Patent No. 111,184.

The state of the semiconductor art is such that, if individual defects can be visually examined, diagnosis of the processing variation which caused the defect can be made to determine the appropriate corrective action. However, it should be stressed that, in order to facilitate this diagnosis, accurate location and visual observation of known defects are of key importance. As a further requirement, the location and visual observation operations should be readily and quickly implementable in order quickly to provide feedback data to prevent continued manufacturing under low yield processing conditions. Meeting these requirements is not an easy task, considering the fact that a typical processing-induced defect is of a submicron size, and can be located anywhere in a semiconductor circuit.

Although the defect monitors previously discussed typically produce good defect density data, these defect monitors usually produce little additional information as to where on the defect monitor circuit a particular defect has occurred. Instead, these testing approaches, simply utilizing continuity and/or conductivity measurements, produce only pass/fail data. Thus, if one of these defect monitors were found to be adversely affected by a processing defect, the entire defect monitor must be visually scanned with magnification instruments to locate and visually observed the defect. As test patterns typically occupy a substantial layout area of a semiconductor layer, it becomes a very tedious, or even impossible, task to use magnification instruments visually to scan the patterns for submicroscopic defects. Furthermore, as such visual scanning requires an exorbitant amount of time to produce diagnostic data, manufacturing yield is still negatively affected because of the substantial continued manufacting under low yield processing conditions.

Consequently, there has long existed a need for a semiconductor-processing defect monitor in which the location and visual observation of defects can be easily and readily implemented in order quickly to provide corrective feedback data.

SUMMARY OF THE INVENTION

Thus, it is an object of the present invention to provide a semiconductor-processing defect monitor in which the approximate location of individual defects can be quickly and easily determined to facilitate visual examination of the defects.

Another object of the invention is to provide a semiconductor-processing defect monitor which includes continuity test structures to test for open-circuit induced defects.

Another object of the present invention is to provide a semiconductor-processing defect monitor which includes short-circuit test structures, to rest for short-circuit induced defects between adjacent conductive lines.

A further object is to provide a semiconductor-processing defect monitor which includes insulation layer short-circuit test structures, to test for short-circuits induced defects between overlapping conductive layers.

These and other objects of the present invention are realized, in one term of the invention, in a semiconductor-processing defect monitor having a matrix array of test cells arranged in columns and rows, and at least one serpentine conductive line connected at various locations along its length to the individual test cells of the matrix array. Each test cell has at least one transistor connected to a row and column line such that the row line, column line and transistor can be used to connect the test cell to the serpentine line. Since each individual test cell is connected at a different location along the serpentine line, selective access of individual test cells can be used to facilitate selective electrical access to different lengths of the conductive lines.

In regard to defect monitioring, the serpentine line can be continuity-tested for open-circuit induced defects. If a defect has been induced, its location can be easily determined using the matrix array of test cells selectively to access different lengths of the conductive lines. In another testing operation, the row and column lines can be defect tested by applying a voltage potential to the serpentine line and then each individual test cell is selectively activated in an attempt to access the voltage potential. By conducting the above two testing operations, pass/fail data can be analyzed using a bit map approach to determine the type and approximate location of a known defect. In a third testing operation, testing for short-circuit induced defects between different planar levels can be conducted by applying continuity tests between the respective individual row, column, and serpentine lines which normally should be isolated from one another. Finally, to facilitate testing for short-circuit induced defects between conductive lines on the same planar level, each test cell is additionally provided with conductive lines "finger" structures which are parallel to the row, column, and the serpentine lines.

Accordingly, the present invention relates to a semiconductor-processing defect monitor comprising:

a conductive line;

a plurality of column lines connectable to column decoder circuitry;

a plurality of row lines connectable to row decoder circuitry; and

a plurality of test cells, each respective test cell being provided at a different location along the length of said conductive line, each said respective test cell having transistor means connected to said conductive line, one of said row lines, and one of said column lines, such that said row lines, said column lines and said transistor means of said test cells can be used to facilitate selective electrical access to different lengths of said conductive line.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other structures and teachings of the present invention will become more readily apparent upon a detailed description of the preferred embodiment for carrying out the invention as rendered below. In the description to follow, reference will be made to the accompanying drawings, in which;

FIGS. 1A through 1C are simplified topographical and perspective diagrams of prior art semiconductor-processing defect monitors.

FIG. 2 is a simplified circuit diagram of one embodiment of a semiconductor-processing defect monitor of the present invention.

FIG. 3 is a simplified schematic diagram of one embodiment of a test cell of the present invention.

FIG. 4 illustrates the manner in which bit map analysis is used approximately to locate an open-circuit defect induced in a long conductive line of the defect monitor of FIG. 2.

FIG. 5 illustrates the manner in which bit map analysis is used approximately to locate an open-circuit defect induced in a matrix row line of the defect monitor of FIG. 2.

FIG. 6 illustrates the manner in which bit map analysis is used to approximately locate an open-circuit defect induced in a matrix column line.

FIGS. 7A and 7B are simplified block diagrams of row decoder circuitry, and column decoder and sensing circuitry which can additionally be combined with the circuit of FIG. 2.

FIG. 8 is a simplified circuit diagram of a preferred embodiment of a semiconductor-processing defect monitor of the present invention.

FIG. 9 is a simplified schematic diagram of a preferred embodiment of a test cell of the present invention.

FIG. 10 is a topographical diagram of the semiconductor layout pattern to fabricate a preferred embodiment test cell of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

One embodiment of the present invention is shown in FIGS. 2 and 3. It should be understood that, in a preferred manufacturing approach, this semiconductor-processing defect monitor would be a semiconductor circit fabricated in the kerf area of a semiconductor wafer.

In FIG. 2, there is shown a serpentine line 220 having its ends terminated with the test contact pads 222 and 224. The serpentine line 220 is a line of conductive material which is formed at one of the planar levels of a semiconductor circuit; for example, serpentine line 220 can be of a doped polysilicon, of a diffusion level, or of a metal material formed as a wiring structure on top of the semiconductor substrate. The test contact pads 222 and 224 are also formed of a conductive material and, in a practical arrangement, are formed on the top surface of the semiconductor wafer to facilitate mechanical/electrical connection to the serpentine line 220.

At this point, it is useful to note that the serpentine line 220, along with its test contact pads 222 and 224, represents a continuity defect monitor. More specifically, once the serpentine line 220 and the test contact pads 222 and 224 have been fabricated in the semiconductor wafer, mechanical/electrical contact can be made to the contacts 222 and 224 to test for electrical continuity therebetween. If the processing environment were such as to induce an open circuit defect along the serpentine line 220, continuity would not exist between the test contact pads 222 and 224.

It should be noted that, standing alone, the serpentine line 220 does not permit easy determination of the approximate location of known defects. More specifically, continuity testing using the test contact pads 222 and 224 provides only pass/fail test data. Thus, the semiconductor-processing defect monitor of the present invention includes further constructions.

In FIG. 2, there is shown a matrix array of test cells T.sub.1 through T.sub.12 which are arranged in a row and column fashion similar to that used for semiconductor memory devices. As an example, row 1 includes the test cells T.sub.1, T.sub.4, T.sub.7, and T.sub.10, and column 1 includes the test cells T.sub.1, T.sub.2, and T.sub.3. It should be noted that the test cell array of FIG. 2 has been limited to twelve test cells for the sake of simplicity of illustration. The defect monitor of the present invention is very versatile in that the test cells represent building blocks or segments which can be used to construct any size array. By way of example, a very small defect monitor, such as the twelve cell array in FIG. 2, could be constructed, or a defect monitor array could easily be designed to match the cell capacities of modern memory devices.

One aspect, which is dependent on the size of an array, should be noted. Once a monitor has been fabricated, connection must be made to the defect monitor in order to conduct testing operations and to extract test data from the array. Two approaches are available.

With smaller arrays (such as the twelve cell array illustrated in FIG. 2), a first approach can be used whereby each of the row and column lines is provided with a test contact pad. Interfacing with the defect monitor is obtained using mechanical/electrical contact to the appropriate test contact pads 203, 205, 207, 213, 215, 217, 219, 222 and/or 224. This mechanical/electrical contact is typically made by using a probe card having tiny pin structures which are appropriately aligned to make contact to the respective test contact pads. The probe card is thus used as a vehicle for providing an interface between the defect monitor and remote support circuitry, for example, row and column decoder circuitry which are used to selectively access individual test cells. The external testing circuitry can also include microprocessor means and memory means for storing a program, such that a series of continuity and short-circuit tests are automatically performed on the semiconductor-processing monitor. Finally, in using this approach, the resultant test data can be fed directly from the probe card to a computer to provide quick analysis and determination of the approximate location of known defects, thereby providing for prompt visual observation and a quick determination of the appropriate corrective action.

As array size increases, the above approach becomes impractical for a number of reasons. First, with larger arrays, the pitch (or spacing) between lines becomes extremely small with respect to the much larger size required for a practical test contact pad. A point is reached where there is insufficient silicon area to include a test contact pad for each of the row or column lines. As a second constraint, a probe card has a practical limitation as to the number of probe pins which can be included.

A second, preferred approach is the fabrication of desired support circuitry along with the fabrication of the defect monitor. This approach is applicable to both large and small defect monitor arrays. One advantage of using this approach is that only a small number of additional test contact pads must be included to provide interfacing with the support circuitry.

By way of example of one preferred embodiment, FIG. 2 is illustrated along with block diagrams representing several support circuitries which are highly desirable. One portion of this preferred embodiment is represented by FIG. 7A which comprises a row decoder circuit 200 having terminals 203', 205', and 207'. In an actual semiconductor fabrication, these terminals 203', 205', and 207', would be connected to the row lines 202, 204 and 206, respectively. A second portion of this preferred embodiment is represented in FIG. 7B which comprise a column decoder and sensing circuit 210. This column decoder and sensing circuit includes terminals 213', 215', 217' and 219', which in a semiconductor fabrication would be connected to the column lines 212, 214, 216 and 218, respectively. The internal circuitry of the row decoder 200 and the column decoder circuit 210 is not shown as these devices, per se, are not the subject matter of the present invention, and numerous possible circuit configurations are well known in the art. Although not shown, an appropriate number of test contact pads would be further included to provide interfacing with these support circuits.

With smaller arrays, test contact pads for each of the row and column lines can further be included to serves as backup connections to the defect monitor, should any of the fabricated support circuits become defective due to processing-induced defects. To minimize the possibility of any such failure, the support circuits should be designed to have a high tolerance to processing-induced defects.

Each of the test cells T.sub.1 through T.sub.12 is provided with a unique combination of a row line and column line in a manner similar found in memory array constructions. Thus, as should now be apparent, the purpose of the row lines 202, 204 and 206, the column lines 212, 214, 216, and 218, and the test contact pads 203, 205, 207, 213, 215, 217 and 219 is to provide a means for accessing each of the individual test cells T.sub.1 through T.sub.12.

A very important aspect of the defect monitor of FIG. 2 is that the serpentine line 220 is fabricated so that it crosses or passes in close proximity to each of the individual test cells T.sub.1 through T.sub.12. As will become more clearly apparent with respect to the illustration of FIG. 3, the serpentine line 220 is connected to each of the test cells T.sub.1 through T.sub.12. As can be noted from FIG. 2, the connection of each of the individual test cells T.sub.1 through T.sub.12 occurs at a different location along the serpentine line 220. Thus, in effect, the serpentine line 220 is electrically divided into differnt lengths by the connections to the test cells T.sub.1 through T.sub.12.

Before the operation of the defect monitor of FIG. 2 is described, a more detailed description of the test cell construction is in order. In FIG. 3, there is shown a simplified schematic diagram of one embodinent of a test cell 300 of the present invention. For simplicity of illustration, only one test cell has been shown in detail. It should be noted that the test cell 300 could easily correspond to any of the individual test cells T.sub.1 through T.sub.12. For example, if the test cell 300 were to correspond to the test cell T.sub.1 in FIG. 2, then column line 312, row line 302 and serpentine 320 would correspond to the column line 212, the row line 202, and the serpentine line