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Description  |
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FIELD OF THE INVENTION
The present invention relates generally to image recording systems, and
more particularly to an image recording system comprising a video camera
and a photographic film camera synchronized to capture substantially
identical images of a subject during a single flash illumination.
BACKGROUND OF THE INVENTION
In many applications, it is desirable to record substantially identical
photographic film and electronic video images of a subject. The recorded
video images can then be used, for example, as electronic "proofs" of the
picture composition before the expense of developing and printing the
photographic negatives is incurred. As is well known to those skilled in
the art, flash illumination is required for most indoor, and some outdoor,
photographic opportunities. During such a flash exposure, the film camera
lens remains open for a predetermined period of time, while the flash
illumination is provided during a window of time within this predetermined
period. Because the flash illumination substantially entirely defines the
exposure onto the photographic film, and because the flash illumination
time is short, the operation of the film and video cameras must be
carefully synchronized to obtain substantially identical images. This
synchronization is not believed to be satisfactorily provided by currently
known imaging systems.
European Patent Application No. 0 196 009 shows a still camera wherein a
photosensitive film and a solid state imaging element are positioned in a
single camera body to record substantially identical views of a subject.
Apparatus is provided for viewing the stored video images, for example to
preview the film images, on a small, attached display. This patent suffers
from the disadvantage, however, that while a conventional electronic flash
"shoe" attachment is shown, no suggestion is made as to how the film
exposure and video recording are synchronized to a flash illumination.
U.S. Pat. No. 4,635,123 to Masunaga et al. shows an electronic imaging
system incorporating a solid state image pick-up device, including a
photoelectric conversion portion and a memory portion, operating in
synchronization with a flash. The system operates to record a full frame
video image of a subject subsequent to the triggering of the flash. The
patent shows several methods of synchronizing the flash with the pick-up
device such that flash illumination is inhibited during the transfer of
charge from the photoelectric conversion portion to the memory portion.
The patent further shows several electronic imaging systems wherein the
illumination provided is based on the accumulation of charge within the
image device, so as to obtain a proper exposure of the pick-up device.
The Masunaga et al. patent does not show or suggest the synchronization of
the electronic imaging system with a photographic film camera. Further,
the synchronization of the flash to the video components of the imaging
system inherently produces undesirable results in the recording of the
video image. More specifically, because the flash illumination is delayed
during the transfer of charge within the pick-up device, a time period of
up to 1/60 of a second, the image recorded will not be exactly what the
operator intended to record. This period of time may be sufficient, for
example, for a human subject to blink and alter the intended image.
U.S. Pat. No. 4,366,501 to Tsunekawa et al. shows a video image recording
system synchronized to operate with an electronic flash so as to record a
full frame video image of a subject pursuant to the actuation of a release
and the triggering of the flash. In a first mode of operation a solid
state imager accumulates untransferred dark current between picture
recordings. Upon activation of the release, a frame of charge is
transferred from the imager to "clear" it in preparation for recording.
The flash is then triggered, and the next two consecutive fields of video
information are recorded in a frame store. In a second mode of operation,
the imager is operated in a "movie" mode, that is, it is read periodically
at an NTSC compatible data rate. When the flash is used, the release is
actuated, and the triggering of the flash is delayed to coincide with the
completion of a charge transfer within the imager.
The Tsunekawa et al. patent does not show or suggest any synchronizing of
the video image recording system with a film camera. Further, similarly to
the Masunaga et al. patent discussed above, the operation of the flash is
synchronized to the operation of the video camera. This necessitates the
above described delay of at least one video field (i.e. 1/60th of a
second), and possibly one frame (1/30th of a second), between the
activation of the release button and the triggering of the flash to
illuminate the subject. As described above, such delays are inherently
undesirable in the operation of imaging systems.
Systems are known in which separate photographic film and video cameras are
arranged to synchronously record a substantially identical subject image
during a single illumination of an electronic flash. These systems, one
example of which is the Noritsu model VSS-2, are typically NTSC
compatible, with the recorded video image being displayable on a
conventional NTSC video display. These systems suffer, however, from the
disadvantage that only one half of the NTSC video frame (i.e. one field)
is recorded in synchronization with the flash illumination. The resulting
video images are substantially lacking in detail, especially when they are
displayed on high resolution video monitors.
SUMMARY OF THE INVENTION
It is a principle object of the present invention to provide a method and
apparatus for recording images of a subject in electronic and
photosensitive mediums wherein film and video cameras are synchronized to
capture substantially identical film and full frame video images with a
single flash illumination.
Another object of the present invention is to provide a method and
apparatus of the above-described type wherein the flash illumination is
distributed relatively equally between two fields of video information
comprising the full frame video image.
A further object of the present invention is to provide a method and
apparatus of the above described type wherein the flash illumination can
be substantially immediately initiated in a random (i.e. asynchronous)
manner with respect to the operation of the video components of the
system.
Another object of the present invention is to provide a method and
apparatus of the above described type which is NTSC compatible.
A further object of the present invention is to provide a method and
apparatus of the above-described type which can be implemented using
substantially conventional film and video cameras.
In accordance with the present invention, a method is provided for
recording an image including the step of illuminating a subject with a
flash illumination. A photographic image of the subject is captured on a
photosensitive medium, and a full frame video image of the subject is
recorded in two consecutive fields of video data. The recording of the
full frame video image is synchronized to the capturing of the
photographic image such that the flash illumination is relatively equally
distributed between the two consecutive fields of video data.
In a preferred embodiment of the invention, substantially identical views
of the subject are directed to both the film and video cameras. The video
camera includes a solid-state imager operating in a movie mode with a
periodic transfer of charge from photosites to shift registers. The flash
illumination is provided substantially immediately upon the request of an
operator--i.e. asynchronously to the operation of the video camera. The
recording of the full frame video image is performed by inhibiting, during
the flash illumination, any charge transfer from photosites to shift
registers in the video imager. Upon termination of the flash illumination,
the two consecutive fields of video data are transferred to the shift
registers, and subsequently to a permanent storage medium, whereby to
record the full video frame containing the subject of interest.
BRIEF DESCRIPTION OF THE DRAWINGS
While the specification concludes with claims defining the features of the
invention that are regarded as novel, it is believed that the invention,
together with further objects thereof, will be better understood from a
consideration of the following description in conjunction with the drawing
figures, in which:
FIG. 1 is a block diagram of an image recording system constructed in
accordance with the present invention;
FIG. 2 is a block diagram of the image recording system of FIG. 1 showing
further detail;
FIG. 3 is a block diagram of the video image capturing means of FIG. 2
showing further detail;
FIG. 4 is a schematic diagram of the interline transfer imaging device used
in the video camera of FIG. 3;
FIG. 5 is a block diagram of the synchronization means of FIG. 2 showing
further detail;
FIG. 6 is a timing diagram showing signal conditions when a simulated flash
duration pulse occurs between the occurrence of modified transfer gate
signal pulses;
FIG. 7 is a timing diagram showing signal conditions when the trailing edge
of a simulated flash duration pulse overlaps with the occurrence of a
modified transfer gate signal pulse; and
FIG. 8 is a timing diagram showing signal conditions when the leading edge
of a simulated flash duration pulse occurs during the occurrence of a
modified transfer gate signal pulse.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIG. 1, an image recording system 15 is shown including a
beamsplitter 24 situated to direct light reflected from a subject 20 to
both a photographic film camera 26 and a video image capturing means 28.
Film camera 26 comprises, for example, A Mamiya model RB67, while video
image capturing means 28 is described in further detail below.
Beamsplitter 24 is preferably positioned such that the images of subject
20 directed to photographic film camera 26 and video image capturing means
28 are substantially identical.
A synchronization means 30 is connected to the shutter release button (not
shown) of film camera 26 by a mechanical, shutter activation cable 38, and
to the "PC" electrical connector of the camera by an electrical connection
40. As is known to those skilled in the art, film camera 26 generates a
flash request (FRQT) signal over connection 40 when its shutter is
activated. It will be understood that, while electrical connections
between system components are typically drawn as a single line, they may
actually comprise multiple signal lines as is conventional in the art or
described herein.
Synchronization means 30 is connected to video image capturing means 28 via
four signal connections 29A, 29B, 29C, 29D. Signal connections 29A-D
conduct, respectively, a move aperture (MA) signal, an inhibit transfer
gate signal (IXSG), a synchronization signal (SYNC), and a grab frame
signal (GFRM). The operation of synchronization means 30, and the function
of these signals, is explained in detail below. Synchronization means 30
is further electrically connected to an electronic flash 22 via a flash
"PC" cord connector 42. Flash 22 comprises, for example, the commercially
available Speedotron System, available from Speedotron Corp.
A video monitor 32, for example a Sony model PVM 1910, is electrically
connected to video image capturing means 28 by an electrical connection
33. A mass storage device 34, for example a Winchester hard disc of the
type available from Quantum Corp. as model Q280, is electrically connected
to video image capturing means 28 and synchronization means 30 via an
appropriate, general purpose disc interface bus 35. Such an interface
could comprise, for example, the Small Computer Systems Interface as
defined by proposed ANSI standard X3T9.2. A user interface 36, adapted for
operation by a human operator, is electrically connected to
synchronization means 30 via connection 37 for permitting the operator to
set selectable system parameters. User interface 36 comprises, for
example, an alpha numeric keyboard with a liquid crystal display (LCD). An
optional still video floppy recorder 17, for example a Kodak model SV7400,
is shown connected to video image capturing means 28 via connection 33,
and to synchronization means 30 via a connection 19. Recorder 17 receives
NTSC video data from connection 33, and control data from connection 19.
Referring now to FIG. 2, video image capturing means 28 is seen to comprise
a video camera 44 and a frame store 46. Video camera 44 comprises, for
example, a conventional NTSC standard video camera such as a Sony model
DXC102 modified to permit control of a transfer frame signal (in a manner
described in detail below), while frame store 46 comprises, for example,
an AT&T Co. model Targa 24. Video camera 44 is electrically connected to
frame store 46 via connection 47 for sending video image signal
information to the latter. Video camera 44 receives signals MA, IXSG, and
SYNC from synchronization means 30 along respective signal connections
29A, 29B, 29C. Frame store 46 receives the GFRM signal from
synchronization means 30 via signal connection 29D. Video synchronization
generator 56 is connected to synchronization electronics 54 via a
connection 55 for sending the NTSC vertical blanking signal (VBLK)
thereto.
Continuing to describe FIG. 2, synchronization means 30 comprises a
pressure actuable image capture button 48, a camera trigger module 50, a
flash driver circuit 52, a synchronization electronics circuit 54, a video
sync generator 56, and a central processing unit (CPU) 58. Video
synchronization generator 56 comprises a standard NTSC synchronization
signal generator, for example a Fairchild 3262A NTSC sync. generator
integrated circuit (IC). Image capture button 48 is mechanically connected
to film camera trigger module 50 by a cable 49, the trigger module in turn
being mechanically connected to photographic film camera 26 via mechanical
cable release 38. Film camera trigger module 50 is electrically connected
to video image capturing means 28 via connection 29A for sending move
aperture signal MA. Flash driver circuit 52 comprises, for example, a
silicon controlled rectifier (SCR) switch circuit of a type well known to
those skilled in the art.
Flash driver 52 is electrically connected to flash 22 via connection 42,
and to synchronization electronics 54 via connection 53. As will be
described in further detail hereinbelow, responsive to a flash request
FRQT signal from camera 26, synchronization electronics 54 generates a
flash trigger signal FTGR for activating flash 22 to illuminate subject
20.
Continuing to describe FIG. 2, synchronization means 30 further includes a
computer, or central processing unit (CPU) 58 electrically connected to
synchronization electronics 54 via INTR and READY signal connections 39,
57, respectively. CPU 58 is further connected to frame store 46 via
connection 29D, user interface 36 via connection 37 and mass storage
device 34 via interface bus 35.
Referring now to FIG. 3, video camera 44 is seen to include a lens
mechanism 59 including a diaphragm 60, a solid-state imager 62, a signal
processing circuit 64, a clock driver 66, a video camera timing generator
68, a logic gate 70, and a diaphragm driver 72. Diaphragm 60, controlled
by mechanically connected diaphragm driver 72, which is in turn controlled
by move aperture control signal MA via connection 29A from synchronization
means 30, functions to regulate the amount of light impinging upon imager
62. Imager 62 is electrically connected to signal processing circuit 64
via connection 63 for transmitting image information thereto.
Video camera timing generator 68 generates and transmits an original
transfer gate signal (OXSG) via connection 69 to one input of logic gate
70. Video camera timing generator 68 also produces phasing (XVI-XV4, XH)
and timing signals which are synchronized to the synchronization signal
SYNC of video sync generator 56. Video camera timing generator 68 provides
these phasing signals (XVI-XV4, XH) to clock driver 66 via signal
connections 71A, 71B, respectively, and the timing signals to signal
processing circuit 64 via signal connection 73. Clock driver 66 is
electrically connected to imager 62 for sending image transfer gate (XSG)
signal and phasing signal (XVI-XV4, XH) information on connections 65A,
65B, 65C, respectively. Logic gate 70 has two inputs--the original
transfer gate signal OXSG from video camera timing generator 68 and the
inhibit transfer gate signal IXSG from synchronization means 30. The
inhibit transfer gate signal IXSG is utilized by synchronization means 30
to prevent transfer gate signal XSG of video capturing means 28 from going
logically low. Logic gate 70 has one output signal line which connects to
clock driver 66 via connection 75 for sending a transfer gate signal
(XSG).
Frame store 46, as shown in FIG. 3, receives video signal information from
signal processing circuit 64 via an electrical connection 77. In addition,
frame store 46 receives synchronization signal SYNC from video
synchronization generator 56 via connection 29C. Instructions for grabbing
a frame of video information are received by frame store 46 on GFRM signal
connection 29D, which originates from synchronization means 30. The
detailed operation of video camera timing generator 68 and clock driver 66
will be described below with respect to the timing diagrams in FIGS. 6-8.
Referring now to FIG. 4, a block diagram view of imager 62 is shown,
including features well known to those skilled in the art. It will be
understood that imager 62 comprises a conventional interline-transfer
image sensor, for example Sony model ICX-018. Imager 62 includes a
plurality of photosites 102 for collecting charge in accordance with the
pattern of light reflected from image 20 (FIGS. 1, 2). Imager 62 further
includes a horizontal shift register 104 responsive to phasing signal XH,
and four vertical shift registers 106A, 106B, 106C, 106D responsive to
phasing signals XV1-XV4. Four transfer gates, 108A, 108B, 108C, and 108D,
are disposed between corresponding photosites and vertical shift registers
106A-D for controlling the transfer of charge accumulated at the
photosites to the shift registers. Transfer gates 108A-D are responsive to
transfer gate signal XSG for controlling this transfer of the charge.
In operation, when transfer gate signal XSG is low, the image charge
packets that have collected in photosites 102 transfer through adjoining
transfer gates 108A-D to a corresponding vertical charge-coupled device
(CCD) shift register 106A-D. Once the charge packets are registered in
vertical shift registers 106A-D, the vertical phasing signals XV1-XV4
operate to transfer the charge packets to horizontal CCD shift register
104, from which they are transferred off the image sensor under the
control of horizontal phasing signal XH. Vertical and horizontal transfers
are accomplished by biasing the registers with the respective phasing
signals to form an array of independent potential wells, which are then
shifted by varying the bias levels of the phasing signals in tandem.
Referring now to FIG. 5, synchronization electronics 54 comprises: three
one-shots, 74, 76, 78, the latter two being serially connected, and a
synchronization logic control circuit 80. Synchronization logic control
circuit 80 comprises, for example, a digital state machine or a central
processing unit (CPU) programmed to function in accordance with the
detailed operation described below. One shot 74 receives a flash request
(FRQT) signal from photographic film camera 26 via film camera "PC" cord
40. The 4 millisecond duration flash simulation signal PC of one shot 74
is sent to synchronization logic control circuit 80 by way of connection
81. One shot 76 receives the vertical blanking signal VBLK from video sync
generator 56 on connection 55. The output signal from one shot 76 is
connected to the input of one shot 78 via electrical connection 83. One
shot 78 produces an modified transfer gate signal MXSG, representing a
simulated modified transfer gate signal (i.e. a modified XSG signal), and
is connected to an input of synchronization logic control circuit 80 via
an MXSG signal connection 85. Synchronization logic control circuit 80 is
further connected to CPU 58 via connections 39, 57. It will be understood
that modified transfer gate signal MXSG is generated because the original
transfer gate signal OXSG is not readily available from video camera 28.
The same function, however, could be accomplished by modifying video
camera 28 to provide the original gate transfer signal OXSG to
synchronization logic control circuit 80.
Output signals from synchronization logic control circuit 80 include the
inhibit transfer gate signal IXSG on connection 29B to video image
capturing means 28, flash trigger signal FTGR on connection 53 to flash
driver circuit 52, and the interrupt signal INTR on connection 39 to CPU
58. The exact operation of synchronization logic control circuit 80 will
be described with respect to the timing diagrams in FIGS. 7-9 below.
Continuing to describe FIG. 5, film camera trigger module 50 comprises a
camera trigger light source 82 and a camera trigger light sensor 84. Light
source 82 is optically coupled to light sensor 84 such that actuation of
image capture button 48 results in decoupling of light source 82 and light
sensor 84. As a result of the optical decoupling, move aperture signal MA
is sent from camera trigger module 50 to video image capturing means 28 on
connection 29A.
In operation, image recording system 15 records substantially identical
images of subject 20 in a film medium (not shown) situated in film camera
26, and electronically in video image capturing means 28, responsive to a
single illumination of flash 22. Referring to FIGS. 1-5, subject 20 is
situated relative to image recording system 15, and, in a manner well
known to those skilled in the art, photographic film camera 26 is preset
to perform flash photography. To initiate the recorded images, an operator
actuates image capture button 48, and mechanical cable release 38 actuates
the shutter of photographic film camera 26 to begin a flash exposure
sequence. As part of its flash operating sequence, after a short delay
during which the electrical and mechanical systems of photographic film
camera 26 are activated, the film camera sends a flash request signal FRQT
(a high to low signal transition) along the photographic film camera "PC"
cord 40 to one shot 74 of synchronization electronics 54. Responsive to
the flash request signal FRQT, one shot 74 generates logical low-going PC
pulse for a 4 msec duration, the duration being selected to simulate the
maximum illumination duration of typical studio flash 22. It will be noted
by the reader that the terms signal and pulse are used interchangeably.
To understand the synchronization of film camera 26 and video image
capturing means 28, it is first necessary to understand the operation of
the latter as the PC pulse is being generated. Referring back to FIGS. 3
and 4, video image capturing means 28 normally operates in a "movie mode",
with diaphragm 60 functioning to regulate the amount of light reflected
from subject 20 which impinges on image sensor 62. In the movie mode,
diaphragm 60 is held at an open, ambient setting, and the photosensitive
region (i.e. photosites 102) of imager 62 is continuously irradiated by
scene ambient light (typically referred to as modeling light). The video
signal generated by image sensor 62 is converted into a line sequential
color signal by signal processing section 64. Video camera timing
generator 68 synchronizes signal processing circuit 64 with image sensor
62. In particular, the timing generator 68 produces the original transfer
gate signal OXSG, and the phasing signals XVI . . . XV4 and XH.
Appropriate synchronization timing signals are generated in video camera
timing generator 68 and transferred to signal processing circuit 64 via
connection 73. Because the exposure time of imager 62 is fixed to accord
with the standard NTSC video image rates (i.e. 30 frames/second and 60
fields/second--each frame comprising consecutive `odd` and `even` fields),
the imager is repetitively processed at a corresponding image frequency of
30 frames/second. That is, 30 full frames/second of video information are
read from imager 62 and processed by signal processing circuit 64 under
the control of video camera timing generator 68. The video signal is
continuously displayed on video monitor 32 and, at the appropriate time,
is recorded in frame store 46 and stored on mass storage device 34.
In summary, prior to the initiation of a recorded image by the actuation of
image capture button 48, video monitor 32 is displaying a constant, motion
picture of subject 20 as sensed by imager 62 in video camera 44.
(Alternatively, as described in detail below, after the recording of a
video image, monitor 32 can be controlled to display the last-recorded
image in frame store 46).
It will be appreciated that the operation of video image capturing means 28
is generally conventional. More information regarding the operation of
another appropriate video camera (i.e. in addition to the Sony camera
referenced above), including operation of an imager, can be found by
referring to U.S. patent application Ser. No. 882,121, entitled
"Asynchronous Still timing for A Video Camera Producing Movie or Still
Images", filed in the name of R. M. Vogel on July 3, 1986, assigned to the
assignee of the present invention, and incorporated herein by reference.
It will also be understood that a different CCD frame/interline type
imager, or an MOS photodiode array type imager, could be substituted for
imager 62 with appropriate changes in timing.
FIGS. 6, 7, and 8 show timing diagrams which, when considered in
combination with FIGS. 1-6 above, describe in detail the operation of
video imaging system 15. It will be understood that, for purposes of
explanation and readability, the various pulses shown in these timing
diagrams have not been drawn to scale. While the origin and destination of
all of the signals depicted in FIGS. 6-8 have been shown and described
above, for the purpose of convenience, the signal origins will now be
briefly reviewed in the order in which the signals appear. Vertical
blanking signal VBLK originates from video sync generator 56. One shot 76
of sync electronics 54 produces signal OS1. Modified transfer gate signal
MXSG is produced from one shot 78 of sync electronics 54. Video sync
generator 56, one shot 76, and one shot 78 are all shown in FIG. 5. Video
camera timing generator 68 of video camera 44 produces original transfer
gate signal OXSG. Transfer gate signal XSG is output from logic gate 70 of
video camera 44. Both video camera timing generator 68 and logic gate 70
are shown in FIG. 3. One shot 74 of sync electronics 54 produces the flash
simulation signal PC. Synchronization logic control 80 of sync electronics
54 produces inhibit transfer gate signal IXSG, flash trigger signal FTGR,
and interrupt signal INTR. Ready signal READY is output from CPU 58. Note
that synchronization electronics 54, one shot 74, synchronization logic
control circuit 80, and CPU 58 are all shown in FIG. 5.
Image recording system 15 operates in one of four possible modes depending
on the time a simulated flash signal PC is generated relative to the
occurrence of a modified transfer gate pulse MXSG. More specifically, the
generation of a transfer gate pulse XSG is inhibited during the
illumination interval of flash 22. Charge accumulating on photosites 102
of imager 62 is thereby prevented from being transferred to shift register
108 during the period of illumination of flash 22.
It will be understood that a frame of video comprises two consecutive video
fields, an ODD field and an EVEN field. In accordance with the present
invention, the light energy of flash 22 is substantially entirely
contained within a single frame, and relatively equally divided between
the ODD and EVEN fields comprising a frame. If charge accumulated on
photosites 102 of imager 62 was transferred during the illumination of
flash 22, part of the light energy of the flash would be divided between
two ODD or two EVEN fields. Thus, any given frame (one ODD and one EVEN
field) would include fields containing unequal light energy. This unequal
distribution of light energy would degrade the quality of the frame so as
to cause interlace flickering.
As stated above, there are four modes of operation which must be
considered. The first is a "normal" mode of operation wherein a simulated
flash duration pulse PC is generated between occurrences of modified
transfer gate pulses MXSG. This normal mode of operation is shown in the
timing diagram of FIG. 6. The second mode is a "trailing edge" mode
wherein the trailing edge of a simulated flash duration pulse PC occurs
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