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Description  |
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FIELD OF THE INVENTION
This disclosure relates to peripheral controllers which are used to manage
the transfer of data between a main computer system and a plurality of
peripheral devices such as disk drive units.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to a co-pending application entitled
"Self-Testing Peripheral-Controller System", filed Sept. 27, 1985, as U.S.
Ser. No. 780,762 by inventor Ronald S. Coogan.
Additionally, this application is related to another co-pending application
entitled "Data Transfer System Using Dual-Ported Peripheral Units", filed
Dec. 6, 1985 as U.S. Ser. No. 805,649, by inventors Ronald S. Coogan and
Toan Dinh Dang.
BACKGROUND OF THE INVENTION
A continuing area of developing computer technology involves the transfer
of data between a main host computer system and one or more peripheral
terminal units. To this end, there have been developed I/O subsystems
which are used to relieve the monitoring and housekeeping problems of the
main host computer and to assume the burden of controlling peripheral
terminal units and to control the execution of data transfer operations
which need to occur between the peripheral terminal units and the main
host computer system.
A particular series of I/O subsystems has been developed which uses
peripheral controllers known as "data link processors" whereby initiating
commands from the main host computer are forwarded to the data link
processor which manages the data transfer operations with one or more
peripheral units. In these systems, the main host computer provides a
"data link word" which identifies each task that has been initiated for
the data link processor. After the completion of the given task, the data
link processor will notify the main host computer system with a
result-descriptor word to inform it as to the completion, incompletion, or
problem involved in that particular task.
These types of data link processors or peripheral controllers have been
described in a number of patents issued to the assignee of the present
disclosure and these patents are included herein by reference as follows:
U.S. Pat. No. 4,106,092 issued Aug. 8, 1978 entitled "Interface System
Providing Interfaces to Central Processing Unit and Modular
Processor-Controllers for an Input Output Subsystem", inventor D. A.
Millers, II.
U.S. Pat. No. 4,074,352, issued Feb. 4, 1978, entitled "Modular Block Unit
for Input-Output Subsystem", inventors D. J. Cook and D. A. Millers, II.
U.S. Pat. No. 4,162,520, issued July 24, 1979, entitled "Intelligent
Input-Output Interface Control Unit for Input-Output Subsystem", inventors
D. J. Cook and D. A. Millers, II.
U.S. Pat. No. 4,189,769, issued Feb. 19, 1980, entitled "Input-Output
Subsystem for Digital Data Processing System", inventors D. J. Cook and D.
A. Millers, II.
U.S. Pat. No. 4,280,193, issued July 21, 1981, entitled "Data Link
Processor for Magnetic Tape Data Transfer System", inventors K. W. Baun
and J. G. Saunders.
U.S. Pat. No. 4,313,162, issued Jan. 26, 1982, entitled "I/O Subsystem
Using Data Link Processors", inventors K. W. Baun and D. A. Millers, II.
U.S. Pat. No. 4,390,964, issued June 28, 1983, entitled "Input-Output
Subsystem Using Card Reader-Peripheral Controller", inventors J. F. Horky
and R. J. Dockal. This patent discloses the use of a distribution card
unit used to connect and disconnect the data link processor (peripheral
controller) to/from a host computer as required to accommodate data
transfer operations.
The above referenced patents, which are included herein by reference,
provide a background and understanding of the use of the type of
specialized peripheral-controllers known as "data link processors" (DLP)
which are used in data transfer networks between a main host computer and
various types of peripheral terminal units.
The present peripheral-controller called the storage module device-data
link processor (SMD-DLP) provides features and solutions which were not
available in earlier versions of similar data link processors.
For example, some peripheral-controllers (DLP's) required an "Emergency
Request" cycle from DLP to the host computer to establish a communication
channel for data transfer service when conditions of overload or underload
occurred. This was especially so in systems using magnetic tape
peripherals.
In the present situation, using disk drive modules, this need for an
"Emergency Request" cycle is eliminated since the disk data can easily be
accessed or not on the next turn of the disk and the amount of data in a
sector is of a limited quantity.
Another feature in the present system is the use of "one logical address"
to select an area of two physical sectors of data wherein the least
significant bit (LSB) of the address field will select either the first or
second physical sector.
To handle the situation of different characteristics of various disk drive
units, an attribute table in a PROM is used to provide information to the
SMD-DLP as to characteristics of the selected disk drive module. This PROM
table informs the DLP as to sector numbers, beginning addresses, ending
addresses, number of track-heads available in a particular disk unit, and
the number of bytes per track in each unit. Thus, rapid and accurate
sector location and data transfer operations can occur.
Since two sets of interface unit cards are used to communicate with two
groups of disk drives (each group handling four (4) disk drive modules),
the selection of one interface card is accomplished through a unit select
logic circuit after verification that only one disk unit has properly
responded for use in data transfer oprations.
The handling of up to eight disk drives by one data link processor (DLP) is
facilitated by a gueue file section in buffer memory which can store up to
eight I/O commands for later execution. However, the system also provides
for immediate execution of an I/O command even while commands remain
stored in the gueue file.
These and other features are provided by the described data link processor
for multiple disk drive modules.
SUMMARY OF THE INVENTION
The present disclosure involves a data transfer network wherein a data link
processor is used to manage and control data transfers between a main host
computer and a multiplicity of disk drive storage units.
The storage module device-data link processor described herein provides for
data communication between a main host computer and up to eight separate
disk drive units. The data link processor includes three functional
sections known as the host adapter unit, the formatter unit and the
peripheral interface unit which, in combination, function to monitor and
control data transfer operations between any one selected disk drive unit
and the main host computer system.
The host adapter unit receives the I/O command descriptors from the host
system, verifies their correctness and checks their parity, and provides a
queue list in a buffer memory of the host adapter, which indicates the
jobs or tasks to be accomplished with each of the eight disk drive units.
The command task information is processed and conveyed to the formatter
unit which formats information from an attribute table in the formatter in
order to provide address data as to the particular cylinder, track-head,
and sector to be accessed in a selected disk drive unit. This information
is passed on through the periperal interface card which communicates
directly to the selected disk drive unit.
Unit select logic in the peripheral interface card insures that only one
selected disk drive unit will be communicated with at any given time.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a network drawing showing how the disclosed data link processor
interfaces the host system to a plurality of disk drive units;
FIG. 2, comprising FIGS. 2A and 2B is a block diagram of the section of the
data link processor called the host adapter unit;
FIG. 3, comprising FIGS. 3A and 3B is a block diagram of the section of the
data link processor called the formatter card unit;
FIG. 4, comprising FIGS. 4A and 4B is a block diagram of the interface card
unit of the data link processor;
FIG. 5 is a schematic diagram of the three sub-units of the data link
processor and their cable connections to a plurality of disk drive units;
FIG. 6 is a schematic diagram of the data buffer RAM of the host adapter
unit of the data link processor;
FIG. 7 is a schematic layout drawing showing the format that is used for
track/sector control in the disk drive unit of the network.
FIG. 8 is a drawing showing a layout of the bit locations for the cylinder
address, track address, and sector address.
Referring to FIG. 1, there is seen a data transfer network system, whereby
the main host computer designated as host system 10 communicates over a
set of buses designated as DLI/MLI (data link interface-message level
interface) to a peripheral controller herein called a data link processor
and specifically a storage module device-data link processor (SMD-DLP)
200.sub.d. The output of the data link processor includes an interface
which has bus connections to a series of disk drives D.sub.0 through
D.sub.7. Thus, the network provides for data transfer operations between
eight disk drive units and the host system 10 by means of the
peripheral-controller 200.sub.d.
As will be seen in FIG. 5, the storage module device-data link processor
(SMD-DLP) is made up of three separate units which are seen as the host
adapter unit 2, the formatter unit 3 and the interface unit 4 which may be
formed of first and second interface boards 4.sub.a and 4.sub.b.
A series of disk drives designated as D.sub.0 through D.sub.7 are shown
connected to the data link processor through different sets of cables.
Referring to FIG. 5, the A cable may connect the formatter 3 to each and
everyone of the disk drive units D.sub.0 through D.sub.7 on a daisy chain
connection basis.
Likewise, the first interface 4.sub.a may use the B.sub.x cable to connect
to disk drives D.sub.0 through D.sub.3. Then the cable designated as the
B.sub.y cable can be used to connect the second interface 4.sub.b over to
the disk drives D.sub.4 through D.sub.7.
An "M bus" (FIGS. 2, 3) is used to connect the host adapter 2 to the
formatter card unit 3. Then a cable B' (FIG. 5) is used to connect the
formatter 3 to the interface card unit 4.sub.a and to the second interface
unit 4.sub.b.
Host Adapter Card Unit 2
Shown in FIG. 2 is a block diagram of the host adapter unit which connects
the host computer system 10 to the data link processor 200.sub.d.
As seen in FIG. 2, a transceiver 20 connects to the host system 10 by means
of a data link interface bus designated DATAAx. The transceiver 20
connects to an I/O bus 20.sub.s which has a terminal transceiver 70. The
transceiver 70 connects to an M bus designated DATxx which connects to the
formatter card unit 3.
A RAM buffer 22 is connected to the I/O bus 20.sub.s in order to
temporarily hold data words which are being transferred between the host
system and the disk systems. A more detailed exposition of the buffer RAM
22 will be later described in connection with FIG. 6.
The general purpose of the data link processor 200.sub.d, as effectuated by
its three sub-unit cards, is to select one of the eight disk drive units,
then to address certain areas of the selected disk and execute a data
transfer routine either in the read direction or in the write direct-on
and at the same time to concurrently assure that data integrity is
maintained so that error free data transfers will occur in all instances.
The basic purpose of the host adapter card unit 2 (FIG. 2) is to receive
I/O descriptor commands from the host system 10 and verify the command to
make sure that it is correct, including the making of parity checks. The
host adapter card unit 2 will place the I/O descriptor command from the
host system into its RAM buffer 22 into the queue area (FIG. 6) starting
at the hex address FOO. Thus, I/O descriptor commands are placed into
eight separate areas, each of which involves a command function to be
executed with respect to each of the eight disk drives connected to the
system. Thus, the queue area of the buffer memory 22 shown in FIG. 6 can
store up to eight basic data transfer commands which will subsequently be
executed by the data link processor 200.sub.d.
The commands for operators which are stored in the queue file blocks are
designated as "queueable OPs". However, there is also provision for an
"immediate OP", whereby the execution of a command may be effectuated
without going through the queue of the buffer memory 22.
In operation, the data link processor will do a "seek" function, whereby an
operator OP will be taken from the queue area and placed into the area
known as the device control block or DCB. As seen in FIG. 6, there are
eight DCB areas or device control block areas designated as DCB0 up to
DCB7. These occupy the hex addresses from E00 up to the beginning of the
queue area at hex F00. Each of the device control blocks consists of 32
words which are sent to the formatter 3 which will then develop the
track/sector format which is illustrated in FIG. 7.
The OP information in the DCB of buffer 22 that is selected will be used to
"wake up" the formatter into action.
Referring to FIG. 2 and the host adapter card unit 2, a series of input
signals are fed to the sequencer 26 to select microcode from the host
control store 30. The host control store 30 is the main engine for
controlling and operating the data link processor 200.sub.d. The sequencer
26 receives various data signals which are multiplexed into the host
control store 30 in order to select routines which permit decisions for
which branch operations are to be performed by the microcode of the
control store 30.
The sequencer 26 receives signals from the OP register 46 and OP decoder
48, burst carry signals from the burst counter 50, "command received"
signals from the line 33 to the multiplexor test-input 24 (T-Way) and also
from the PROM scan 28, in addition to signals from the control store 30
which are fed back on lines 24 and 25.
The status input signals to the test-input multiplexor 24 involves a
multiple number of test points connected throughout the host adapter unit
2. These test points include connections for buffer memory management
control, ALU status, counter status (of elements 50, 52, 54), DLI
interface control, M-bus monitoring and handshaking, and status of
operator (OP) types.
The stack counter 60 counts the locations in the RAM buffer 22 that point
to branch addresses in the control store 30.
The host access counter 62 is a counter for the RAM buffer 22 which is used
to count data words transferred to/or from the host system and the buffer
22.
The peripheral counter 64 is a counter used to count the number of data
words transferred between the RAM buffer 22 and a selected one of the disk
file units of FIG. 1.
The word counter 52 is used as a "block counter" which will count up a
specific number of words such as 256 words in order to signify the
counting of a block of data. This counter provides an output "CNTZ" which
is fed to the control store 30 via MUX 24.
The address multiplexor 66 receives input data from the host counter and
the peripheral counter, in addition to address data from the formatter
card unit 3. This count data is fed to the RAM buffer 22 in order to
address various locations in the RAM buffer 22.
The peripheral counter 64 is operated so as to count only up to the number
4,000 which is equivalent to the address DFF (hex) which can be seen in
FIG. 6 in the data buffer section which holds 16.times.256 words (with
parity). The section designated DB1 through DB14 represents 14 blocks of
words, each having 256 data words in it. At the address DFF, the address
pointer will return to the first block at 000.
The burst counter 50 is used to count blocks of data words (each block is
256 data words) which provides a carry signal BCCRY which is sent to the
host control store 30 to indicate that a block of data has been sent to
the host 10.
The time-out counter 54 is used to put a time-out data signal to the
control store 30 if certain conditions do not occur by a preset time.
The OP register 46 and the OP decoder 48 will receive an operator signal
(OP) from the control store 30. The OP register 46 provides an address to
the OP decoder 48 which is a PROM which will provide signal data to
sequencer 26 for the control store 30.
The arithmetic logic units 42 receive microcode signals from the control
store 30 which can be used to process data such as performing various
logical operators and/or shifting and manipulating data which can then be
returned back to the I/O bus 20.sub.s. This processed data can be sent
onto the M bus of FIG. 2.
The D latch 44 is a pipeline register which can receive data from a disk
drive unit and formulate a longitudinal parity word for error checking
purposes. Thus, data from a selected disk file will be transferred to the
buffer RAM 22 and then placed in the D latch 44, after which it can be
transferred to the transceiver 20 for transmission to the host 10 which
can then verify the longitudinal parity word.
The PROM scan unit 28 is used to tri-state the sequencer 26 and acts as a
downcounter in order to deliver address data for the control store 30, so
that PROM parity check unit 35 can verify the correctness of data from
control store 30.
The circuit block designated PROM parity check 35 is used as a parity
checker to verify odd parity.
The constant register 32 is used to provide a data field for the control
store 30 so as to provide a basic data pattern for initialization
operations.
The secondary pipeline register 34 is used for interface purposes to the
host system 10 to provide handshake operations. This provides extra
control in conjunction with the control store 30.
The peripheral control store 38 is used to control the M bus and the
interface to the formatter card unit 3. This is done through a gate 40. A
sequencer 36 receives various input data in order to select microcode
routines in the control store 38. The sequencer 36 receives data from the
slave case 37 on the line OPx and also receives data from the control
store 30 on line S.sub.x in addition to feedback data on line 41 and
select signals from receiver 39.
A series of driver gates, FIG. 2, will be seen to connect to the formatter
card unit 3 in order to provide bi-directional transfers. The gates 67 and
68 connect the address lines to and from the formatter unit 3. The gates
39 and 40 connect the control line data between the formatter unit 3 and
the host adapter.
The address lines ADRXX in FIG. 2 are the "wake up" lines which are used to
activate the system to read the selected data control block (DCB.sub.x) in
the buffer memory 22 of FIG. 6.
In FIG. 2, the transceiver 70 connects the M bus between the formatter unit
3 and the host adapter 2. This provides a bi-directional connection for
data words to be transferred between the two units.
The multiplexor test signal unit 24, designated "T-Way" can be considered
as a "test input" unit, whereby certain status data inputs are multiplexed
into the sequencer 26, as were previously enumerated.
The pipeline register 41, designated as D latch, is a data register used to
store input data to ALU 42 (FIG. 2). This unit type is described in a
publication entitled "Bipolar Microprocessor Logic Interface" at page
5-166, and published by the Advanced Microdevices, Inc. of 901 Thompson
Place, Sunnyvale, Ca. 94088.
It should be noted that the data link processor 200.sub.d is provided with
self-test routines which allow internal operation of the various card
units to be checked before actual data word transfer operations are
initiated.
The slave case 37 is a PROM unit which is used for restricting any invalid
operators which come from the formatter card unit 3. Thus, if any invalid
command and address data from the formatter 3 are received, the slave unit
37 will operate to prevent any execution and to inform the host of such an
invalid operator, via the result/descriptor.
The Formatter Card Unit 3
The formatter card unit has the purpose of selecting a disk drive to be
communicated to and providing data whereby selected areas of the
particulary selected disk drive may be accessed for either Read operations
or for Write operations.
As seen in FIG. 3 data words are transferred between the formatter 3 and
the host adapter 2 by means of a transceiver 70.
Address data between the host adapter and the formatter is transferred
through the transceiver 70, which is controlled by the M bus controller 76
which receives control signals through the control line monitored by gates
74 and 75. The M bus controller 76 can also transmit information through
gate 74 to the control line of FIG. 3.
Similarly to the host adapter card unit, the formatter card 3 has a control
store 90 which receives input addresses from a microprogram controller
sequencer 88. The sequencer 88 receives various data from test circuitry
(82, 84, 86), from the control store 90, and from masking circuitry 77, 78
and 79. The vector RAM 89 is a counter similar to the stack counter 60 of
FIG. 2 which provides address data to the control store 90.
In FIG. 3, a set of arithmetic logic units 80 are provided to the data bus
in order that processing and data manipulation can occur for any data
words on the data bus line.
The mask circuitry is composed of a mask register 77, a mask unit 78, and
an encoder 79, which are used to eliminate unnecessary data and to pass
required data to the vector RAM 89 to develop addresses for control store
90.
The test circuitry (82, 84, 86) receives 16 bits of data from the formatter
RAM buffer 22.sub.2 in order to perform status tests and provide signal
data to the sequencer 88 for the control store 90.
The constant multiplexors 92 and 94 are used as a repository of reset and
initialization data patterns which are used to reset and initialize
various circuitry after clearing operations.
An address register 96 is used to provide addresses both to the formatter
buffer RAM 22.sub.2 and also to an attribute table 97. The attribute table
97 is a specific table of data which provides information as to sector
numbers, beginning addresses, end addresses, the number of heads per drive
and the number of bytes per track for each of the eight separate disk
drive units.
The formatter buffer RAM 22.sub.2 is used as a data buffer to temporarily
hold data words being transferred from the selected disk drive over to the
host access adapter 2 card unit.
The unit, designated as sector format 98, has 84 sectors and 42 records to
provide a pattern of zeros as required for the sector format protocol. It
provides the pattern timing necessary for the formatting of a record
containing two (2) sectors.
The micro-decoder 99 is used to decode the microcode received from the
control store 90, and to select the sector format from unit 98, and to
provide control data to M bus control circuit 76.
The register 100 is a first-in first-out register (FIFO) which is used for
serial to parallel translation or from parallel to serial translation so
that serial data received from the disk unit is translated into parallel
form for transmission to the host and vice versa, whereby parallel data
from the host is transferred into serial data for transmission to the
selected disk drive.
The shift register 101 is used to transmit read data (which comes from the
interface 4 through gate 112, gate 113 and register 101) into the FIFO 100
which data is then placed on the data bus. The unit 102 is a gate which
feeds data to the cyclic redundancy checker and error correction code unit
103. Here, every data field is checked for accuracy and corrected by an
error correction code if necessary.
Gate 104, flip-flop 110 and gate 111 are for retransmission of Write data
from the FIFO 100 over to the interface 4 for transmission to the selected
disk drive unit.
Gate 105 is for enabling the "unit select" (identification) signal from
interface 4 into the formatter 3.
Register 106 and gate 107 permit data words to be transferred from the
formatter data bus on the A cable (FIG. 5) to a selected disk drive as
commands to be performed.
Register 108 and driver gate 109 permit data from the microcode decoder 99
to be transferred to interface unit 4 (FIG. 3).
Gate 104 and flip-flop 110 control the synchronization of data transfers by
using the write clock signal from the disk drive.
Gate 109 is designated as driver (DRV) tags and will provide tag
information data to the disk drive.
Format for Disk Drive Units (FIG. 7): The disk packs which are used with
the storage module device data link processor can be of the type which
contain four and six platters respectively. The bottom side of the lowest
disk is pre-written at the factory with reference servo patterns. Each
pack is indexed from a signal derived from the servo track which denotes
the beginning of a track. Data is stored in a 180 bytes per sector format.
Sector addresses are stored on the pack in binary notation through the
controller by means of the initialization function. The drive is preset in
a soft-sectored mode which means that sector pulses are derived from
variable byte counters synchronized to an index.
Each record is divided into three areas: (i) the control address area and
(ii) the "two data" areas.
The control area is used to:
(1) Establish bit sync and character frame for the sector address;
(2) Contain the sector address;
(3) Contain delays (gaps) for head switching;
(4) Establish bit sync and character frame for the data;
(5) Contain error codes for address error detection.
The two data areas (ii) each contain the user data storage area on the
track. All data areas are separated by control areas.
There are N spare records per cylinder located at the end of each cylinder,
i.e., the last five records on the head with the highest number. The value
of N, which can be different for each drive type, is specified in the
device attribute table 97 which was described in connection with FIG. 3 on
the formatter card unit. For example, in one type of disk drive the value
of N is equal to "five" spare records.
The last cylinder of each unit is reserved for drive maintenance. The
beginning and the ending sector addresses of the maintenance area are
provided in the device attribute table 97.
Format Description: The disk pack will use the track/sector format which is
shown in FIG. 7. A track is divided into 42 records (physical sectors),
each record containing two parts of 180 bytes (logical) sectors. Each
record consists of a beginning-of-record (BOR) gap, a header, two sectors
(each with a beginning of sector gap) and an end-of-record (EOR) gap.
The Header (FIG. 7): The header consists of: an address sync byte (19 HEX),
and address field. The address field is further sub-divided into: (i) a
flag field, (ii) a cylinder address field, (iii) a track address field,
(iv) a sector address field, and (v) an address-cyclic redundancy check
(CRC) field. A four bit flag field contains a flag bit designated "bad
sector", and also contains a flag bit designated "relocated sector", in
addition to two reserved bits (which are always 0).
Sector (FIG. 7): Each sector consists of:
A beginning-of-sector (BOS) gap;
A data sync byte (19 HEX); this is a "binary" 0001 1001;
A 180 byte data area;
A data error correction code (ECC) field.
The "gaps" contain all zeros. The size of the end-of-record (EOR) gap is
different for the last sector of each track.
As seen in FIG. 7, each field can be defined as follows:
(1) GAP 1: 16 bytes--this is required to allow for head selection (5
microseconds minimum).
(2) VFO Sync: 11 bytes--this contains all zeros. This allows the variable
frequency oscillator (VFO) in the disk drive to synchronize to new data
transitions and the speed of the disk. It is contained in the BOR and also
in the GAP 2.
(3) ADDRESS SYNC: 1 byte--this identifies the beginning of the address
field and synchronizes the byte counters in the controller. It is a Hex 19
pattern.
(4) ADDRESS FIELD: 6 bytes--this consists of a four bit flag field, a 12
bit cylinder address field, an eight bit track or head address, then eight
bits (1 byte) of sector address and two bytes of CRC (cyclic redundancy
check) error codes for address error detection.
(5) GAP 2: 19 bytes--this contains all zeros. This includes one byte for
WRITE splice which allows time for the WRITE driver turn-on and 11 bytes
minimum for the VFO sync. The rest is required by controller delays.
(6) DATA SYNC: 1 byte--this identifies the beginning of the data field and
synchronizes the byte counters in the controller. This is a Hex 19
pattern.
(7) Data Field: 180 bytes--this is the user data field.
(8) Data ECC Field: 4 bytes--the data error detection and correction code.
ECC is encoded by the correction controller 103 for each 180 bytes of data
field and is subsequently decoded.
(9) GAP 3: --this constitutes 46 bytes for records 0-40, and constitutes 30
bytes for record 41. This EOR (end-of-record) gap contains all zeros at
the beginning and then transits to the WRITE gate turn-off. There must be
a minimum of four bytes of zeros to prevent WRITE turn-off transients from
causing errors, and there must be a byte (8 bits) of zeros for delay times
due to WRITE encoding/READ decoding. This may be juggled with GAP 1
depending on the pulse timing of the WRITE gate to sector pulse timing.
As seen in FIG. 8, the cylinder address uses 1.5 bytes (12 bits) of data
bits. The track address uses one byte of eight bits of data while the
sector address uses eight bits (1 byte) of data. The least significant bit
(LSB) in the sector address (which is not contained in the field written
on the disk platter) can be a 0 or 1 in order to select either the first
or the second physical sector of data located by the single sector address
SSSSSSS0.
Interface Card Unit
Referring to FIG. 4, there is seen the interface card unit 4. Each card
unit 4.sub.a and 4.sub.b follows the pattern of FIG. 4.
Connections to four disk drive units (D.sub.0, D.sub.1, D.sub.2, D.sub.3)
are shown with data transfer line connections for the Write operation
(designated as WT) by passage through drivers D. Likewise, data transfer
operations on a Read operation are effectuated through the receiver gates,
designated R. Each one of the disk drive units also has unit select lines
which pass through the receivers marked R.sub.S.
The major purpose of the interface card 4 is to receive the unit select
signal (USS) of a given disk drive unit for connection to the formatter
card 3 so that appropriate data transfer operations, either Read or Write,
can be effectuated.
The unit select signal can come from any one in a group of eight signal
lines.
The unit select signal (USS) is originated from two sources:
(i) a disk drive unit;
(ii) a single one of a group of jumpers.
The unit select signal is transmitted via driver 105 (FIG. 3) to unit
select logic in 115. The select logic in 115 then decides which "function"
is requested, that is, if it is a Read unit type (jumpers) or Read unit
type (disk drive).
The unit type function uses all of the eight USS lines (0-7) while the unit
select function uses only a selected one line of the eight lines.
The jumper information tells the formatter unit 3 what "type" of disk drive
is connected, that is, to say, what manufacturer type it is and thus its
cylinder, track and sector capacity as seen, for example, in FIG. 7 which
shows two types of Memorex disks, the 214 and the 226.
From the jumper identification, the formatter 3 can then address the
attribute table 97, FIG. 3, to access specific information regarding the
characteristics usable for that specific type of disk drive.
Thus, any data words received from a selected drive unit will be
transferred through the receiver gate on the data line marked RD and
passed onto the formatter 3, and into buffer 22.sub.2.
Similarly, Write data on data line WR can be received from buffer 22.sub.2
in the formatter 3 and passed onto the gate drivers D for transit to the
selected drive unit.
Driver gates 117, 119, 121 and 123 are made to work in conjunction with
jumpers to provide signals to the unit select line which goes to formatter
3. The jumpers operate to identify a disk drive unit as to its type.
Driver gates 116, 118, 120 and 122 are used to convey the unit select
signals to the formatter 3. The unit select logic 115 also receives
signals from the PROM 97 and the unit select gate R.sub.S in order to send
a signal to the formatter 3 to indicate that only one unit has been
selected.
The driver gates 125, 127, 129 and 131 are used to enable any Read
operations on the RD data line. These gates are controlled by 115.
The power detect logic unit 150 provides a channel ready signal to sense if
there is a power supply problem in any of the selected disk units. If a
power supply problem is detected in a disk module, then that particular
disk interface will be shut off.
There is also a clock line from the disk drive to formatter 3 as indicated
in FIG. 4. This line is called the WR drive clock line and is used to
provide clock operations during the writing and reading of data of the
disk that is selected.
The unit select logic 115 (FIG. 4) receives inputs from each disk drive
module (D.sub.0, D.sub.1, D.sub.2 . . . D.sub.7) and operates to scan
these inputs to see whether only one disk module has responded (normal) or
whether multiple numbers of disk modules have responded (error). If two or
more disk modules have responded, then logic 115 will output an error
signal to the formatter unit 3. The formatter will report the error
(multiple response) t | | |
