Apparatus for processing images which have been sampled on a rectangular grid and which have been binary digitized with one bit per pixel, each pixel being considered in relation to at least some of the eight surrounding pixels in the rectangular grid. The apparatus includes a control unit (4), a random access memory (5) for storing the pixel bits, and a feedback loop connecting the image memory output to its input via at least one feedback assembly (6) comprising shift register unit (6A, 6B), a function memory (7) and a selector (8). The shift register units comprises at least one write unit (6A) and at least one read unit (6B), with the read unit being connected to the output of the image memory and being connected to supply nine bits simultaneously to the input of the function memory. The nine bits correspond to a pixel under examination and to the eight surrounding pixels, and are changed at each shift of the shift register units. The function memory provides new values for the bit of the pixel under examination on the basis of thenine bits applied to its inputs and in accordance with a plurality of predetermined criteria. The selector receives the new values from the function memory and selects one under control of the control unit. The selected on of the bits is then written back into the image memory via the write unit.
A photon signal received on a CCD is digitized and coupled to a 3.times.3 pixels data analysis array (DAA). The digital signals read out from the penultimate three pixels of the DAA are used to address a first look up table held in a memory, the digital signals read out from the last three pixels of the DAA are used to address a second look up table held in a memory. The data stored at the two addressed locations are then read out and logically ANDed to produce an output signal only when both ANDed data correspond to a valid photon event. The output signal thus defines the position of the center of the photon signal at a high level of precision.
An image coding apparatus and method are disclosed. The method and apparatus are applicable to coding any array of arbitrary dimension. The apparatus utilizes FIR filters which generate three or more sets of coefficients from linear arrays generated from the array being coded. Each set of coefficients represents spatial frequency information of different frequencies. The filters utilize coefficient sets which are preferrably orthogonal.
An image to be smoothed is represented by a matrix of pixels arranged in a plurality of adjacent scan lines. Each pixel under examination is changed to the value of a predetermined number of pixels in a 3.times.3 pixel neighborhood surrounding the pixel under examination. The image pixels are represented by a sequence of 16 bit digital words, each bit representing a corresponding pixel. The bits of three adjacent words on three adjacent scan lines are accumulated in 16 counters, respectively, with the words shifted so that the 9 bits of each of sixteen 3.times.3 neighborhoods are simultaneously accumulated in the sixteen counters. Each counter is constructed so that when a predetermined number of ONEs is accumulated from the 3.times.3 neighborhoods, the most significant counter stage goes to ONE and remains at ONE irrespective of further accumulation. One of the three words is the word to be smoothed. The most significant stages of the sixteen counters contain the smoothed word corresponding to the word to be smoothed.
Each of plural image processing means is informed of address information of storage means in which image data to be read is stored upon request of the image data to be read by each of the plural image processing means. Consequently, each of the image processing means can read each of image data to be read directly from the storage means based on the informed address information so as to subject it to predetermined image processing. Thus, it is possible to perform plural independent image processing in parallel at a high speed with the simple configuration.
This invention provides a feature extracting circuit including a shift register section arranged to store an image for a predetermined number of lines, the image consisting of a predetermined number of bits, and then to shift the image; a look-up table section for transforming a set of partial image data for a predetermined number of pixels supplied from the shift register section into a direction index and then for outputting the direction index; and a counter section for counting the direction index output from the look-up table section. The feature extracting circuit receives a binary digital image and extracts, as a feature of the image, a direction index which indicates the direction in which the boundary between adjacent black and white pixels extends.
