A new differential amplifier circuit including two current mode logic circuits, each comprising a pair of transistors whose emitters are connected to a common current source. The differential amplifier circuit receives three input signals, with a transistor in both of the current mode logic circuits being controlled by one of the input signals. The collector outputs of the two transistors controlled by a single input signal are connected together, and the collector outputs of the two transistors controlled by the other two input signals are also connected together, in both cases to form summing junctions. The summing junctions are connected to an output buffer to generate a pair of signals constituting differential output signals.
A tunable quadrature phase shifter including two branches each constituted by the cascade connection of a filter, an amplifier and a summing circuit, and two cross-connections constituted by amplifiers interconnecting the filter of one branch to the summing circuit of the opposite branch. An accurate 90 degrees phase shift between the two output signals is obtained by controlling the tail currents of the four amplifiers. The phase shifter used in mobile telecommunication transceivers may be easily and accurately tuned because the signals used in the summing circuits all have a similar amplitude. It is further adapted to operate with only a 3 Volt battery supply as used in wireless phones. The bandwidth of the amplifiers is increased by using double differential pair amplifiers which behave as cascode arrangements.
An output circuit is provided which exhibits a waveform having a higher edge rate, with less ringing and power consumption than many conventional differential amplifier output driver circuits. A pre-driver stage using a current-mode logic (CML) design eliminates the frequency dependent transfer characteristics associated with emitter follower amplifiers used with emitter-coupled logic (ECL)-pre-drivers. The final stage CML circuit has been modified to eliminate the Miller-effect capacitance, using cascode transistors to maintain a constant voltage at the collectors of the final stage CML circuit transistors. The cascode transistors isolate the switching noise of the final stage CML transistor pair. Further, the bases of the final stage CML transistors present a smaller load to the pre-driver stage output, permitting the pre-driver stage to be a CML rather than an ECL design. A method of amplifying a differential signal in accordance with the principles of the above-described circuit is also provided.
A transconductor stage for high-frequency filters operated on a low voltage supply, being of a type which comprises an input circuit portion having signal inputs, further comprises a pair of interconnected differential cells (2,3) being associated each with a corresponding signal input. Each cell incorporates at least one pair of bipolar transistors (Q1,Q2;Q3,Q4) having at least one corresponding terminal thereof (e.g. the emitter terminal) connected in common.
An operational amplifier is provided and includes at least two input terminals of one polarity and another input terminal of the opposite polarity. The amplifier includes an amplifying portion which comprises a differential section for receiving input signals applied to the input terminals. The differential section includes at least two differential amplifiers which form difference signals from the input signals. A summing section receives the difference signals and forms a sum result therefrom. A multiplying section provides an amplification gain to the sum result to form an output signal of desired gain. The amplifier is also provided with a feedback for applying an input signal to one of the input terminals, the output signal. The amplifier can be configured to provide amplification gains of 2, 1/2, -1 and 1. In view of the amplification gains equal to 2 and 1/2 respectively, there is also provided an analog to digital converter and a digital to analog converter both of which comprise a cascaded series of operational amplifiers.
A memory system (10) is disclosed including a memory array (14), decoder circuit (16), and sensing circuit (17). The memory array includes a plurality of two-port CMOS memory cells (42) arranged in columns and rows that are selectively addressed by the decoder circuit. The bipolar sensing circuit responds to data stored in an addressed memory cell in the following manner. A column decoder (28) in the decoder circuit provides information to a source select multiplexer (30) and a column read access port (18) to selectively couple information stored in the memory cell to an output stage (20). At the output stage a comparison is made between the stored data and a reference voltage provided by a threshold circuit (38) to produce an output indicating the sensed level. The memory cells are preferably asymmetrically designed for hysteretic operation. The resultant bipolar/CMOS memory system advantageously combines the attributes of high density, high speed, and low power consumption.
