A microprocessor which can simultaneously execute a plurality of instructions (predetermined number of instructions, i.e., m-instructions which are transferred to a plurality of registers. When the instructions within the m-instructions are transferred to the registers, the instructions are executed in order of the executable state of the instructions regardless of order of the transfer. Further, when n-instructions (n>m) are simultaneously set to the executable state for every one clock cycle, the n-instructions are executed in order of the transfer of the instructions. Accordingly, it is possible to realize high speed and effective execution of instructions.

A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Entries in a reservation station are efficiently scanned to find data-ready instructions for dispatch. A pseudo-FIFO scheduling approach is implemented wherein, rather than scanning every entry in the reservation station, the reservation station is segmented into groups of entries with each entry being scanned to determine which has the oldest entry in it. It is from the group of entries having the oldest entry that a ready pointer is cycled to search for data-ready instructions for dispatch to waiting execution units.

A super-scalar microprocessor performs operations upon a plurality of instructions at each of its fetch, decode, execute, and write-back stages. To support such operations, the super-scalar microprocessor includes a dispatch arrangement including an instruction cache for fetching blocks of instructions including a plurality of instructions and an instruction decoder which decodes and dispatches the instructions to functional units for execution. The instruction decoder applies a dispatch criteria to selected instructions of each block of instructions and dispatches the selected instructions which satisfy the dispatch criteria. The dispatch criteria includes the requirement that the instructions be dispatched speculatively in order, that supporting operands be available for the execution of the instructions, or tagged values substituted that will be available later, and that the functional units required for executing the instructions be available. The operation of the instruction decoder and the instruction cache is coordinated by a preset protocol which assures that the instructions are dispatched in ascending consecutive order and that blocks of instructions are efficiently fetched for decode and dispatch by the instruction decoder.

A processor having multiple functional units. The processor is capable of executing multiple instructions concurrently. An instruction issuing unit is connected to a mechanism for handling an interrupt of the processor. The interrupt handler has an instruction window (IW), which includes a vector element number (VEN) field that indicates the uncompleted elements to be executed. Upon termination of the interrupt, normal processing of the instruction issuing unit continues.