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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sampling waveform digitizer and more
particularly to a sampling waveform digitizer which is suitable for the
production testing of high performance analog and data conversion
components.
2. Description of the Prior Art
One of the most challenging requirements facing a supplier of high speed,
precision data conversion components is the accurate and efficient
measurement of dynamic performance parameters.
Important dynamic characteristics are usually determined via rather
painstaking laboratory evaluation of a few randomly selected devices.
Often, the procedure involves the use of several different fixtures, and
requires skilled technicians to operate the instruments and record the
results properly. The performance specifications are then published as
"typical", or "guaranteed but not 100% tested", neither of which is very
satisfactory from the customer's point of view.
Some measurements, such as settling time of a fast current output
digital-to-analog converter (DAC), are traditionally so difficult to
perform that the published specification is in fact only a "best guess"
which the customer must verify by observing the device's apparent
performance in his particular circuit.
Therefore, it is becoming increasingly desirable to perform these difficult
dynamic measurements on a production basis as well as in the design
laboratory. This requires that several different characteristics,
including settling time, slew rate, bandwidth, time delay, and the like
must be tested quickly, reliably, and with minimal socket changing or
operator intervention.
These requirements became abundantly clear to the present inventors during
the early development stages of a family of high speed data conversion
components; namely, two fast-settling digital-to-analog converters and a
high speed sample and hold amplifier. The digital-to-analog converters,
both ECL and TTL input versions, were required to settle to 0.01% accuracy
in 40 nanoseconds and the sample and hold amplifier was required to
acquire a 10 volt signal to the same accuracy in approximately 250
nanoseconds. Because the most important design choices were those that
affected the speed and accuracy performance, it was necessary to be able
to measure the dynamic parameters reliably and verifiably. Also required
was a technique suitable for medium to high volume production testing as
well as one that customers could use for performance evaluation and
incoming inspection.
Various other techniques or alternate approaches exist in the prior art,
including (1) high speed clipping amplifiers with oscilloscope viewing of
the output; (2) sampling oscilloscopes; (3) window comparator techniques;
and (4) commercial waveform digitizers.
Conventional wideband oscilloscopes are suitable for measuring the dynamic
characteristics to only 1 or 2% accuracy, at most. Precise settling time
measurements cannot be made directly because the very large dynamic range
of the signal overloads the oscilloscope amplifiers. Therefore, test
circuits have been developed specifically to prevent overloading within
the oscilloscope.
By clipping the test waveform with diodes or special "clipping amplifiers",
it is possible to display the waveform on the most sensitive scale without
severe overloading. However, the measurement accuracy still depends on
several high speed, open loop amplifiers between the signal source and the
display screen. The clipping circuit and amplifiers are themselves prone
to thermal tails, ground loops and signal distortion.
Another prior art technique to prevent oscilloscope overloading is to sum
the settling waveform with a step generator of the same amplitude but
opposite polarity, so that the large signal excursions are cancelled out.
This method requires that the settling time of the step generator itself
be significantly shorter than that of the device under test, presenting a
problem of test verification. If the settling characteristic of the step
generator could be measured, the capability of making the original
settling time measurement would already exist. Therefore, the step
generator is assumed to settle well-based on theoretical circuit
calculations rather than experimental verification.
Signal clipping and step generator techniques have been used successfully
to measure current-mode DAC settling up to 12 bit resolution, but a high
level of expertise in engineering art is required to implement them
properly. Interpretation of the displayed waveform is subject to operator
error and the test fixture is limited to settling time measurement alone.
Evaluation of other parameters still requires a various assortment of
fixtures and equipment hookup configurations within the laboratory.
Sampling oscilloscopes have a very high bandwidth and avoid the overload
problem of conventional types, but the accuracy of the internal diode
sampling bridge is limited to one or two millivolts. Also, there are
numerous practical problems in attempting to drive the low input
impedance.
An interesting method of testing settling time on a production basis exists
in the prior art, and this system uses a window comparator with adjustable
threshholds. Once the DC final value of the waveform is determined, a
system of DACs sets the reference levels at the positive and negative
limits of the error band. The test stimulus is then applied to the device
under test (DUT), and the window comparator output is enabled after the
allowable settling time has elapsed. If the DUT output then exceeds the
error band, the comparator triggers a flip-flop to indicate a settling
time failure.
The window comparator method is suitable for pass/fail production testing
of moderately high speed waveforms. However, it does not lend itself to
laboratory development or characterization work, because it gives no
information above the actual shape of the waveform itself.
To meet the needs of both the development laboratory and the production
floor, a system which permanently records the detailed waveshape is
required. In other words, the ideal system is an accurate, high speed
waveform digitizer.
Recognizing this, test equipment manufacturers have developed digitizers in
various forms. Waveform recorders, transient recorders, and digital
oscilloscopes are all designed to capture and store a set of
time-amplitude points in digital form. Once the signal has been digitized,
it is equally useful for production pass/fail decisions as for detailed
engineering analysis.
While the digitizer concept is attractive, commercially available units do
not yet offer the combination of bandwidth and resolution necessary for
the type of high accuracy measurements under consideration herein, such as
for the dynamic testing of high speed data conversion components and the
like.
A sampling waveform digitizer is needed which is both highly accurate and
generally useful for dynamic testing and characterization of various
waveforms. It must be relatively inexpensive ad well-suited for both
production and design engineering environments.
The present invention eliminates most of the deficiencies of the prior art
and provides a sampling waveform digitizer for performing dynamic testing
on high speed data conversion components including completely automated
dynamic performance characterizations of sample and hold amplifiers and
relatively fast digital-to-analog converters including accurate
measurements of settling time. These have been implemented in the present
invention and various system parameters can be measured including
acquisition time, sample-to-hold settling time, aperture delay, glitch
amplitude, sample-to-hold offset, feedthrough rejection, risetime, slew
rate, and the like.
SUMMARY OF THE INVENTION
The present invention teaches a sampling waveform digitizer for the dynamic
testing of high speed data conversion devices and includes a source of
waveform signals to be tested. A comparator means having at least first,
second, and third inputs and at least one comparator output is provided,
along with means for operatively coupling the waveform signal to be tested
to the signal input of the comparator means. Means for integrating the
output signal from the output of the comparator means is provided along
with a feedback path for supplying the integrated output signal back to
the reference input of the comparator to form a comparator-integrator
feedback loop means.
A control means is provided for programmably selecting a sample point in
the waveform signal to be tested and control means is provided for
generating a sequence of narrow strobe pulses with programmable phase
relative to the test waveform. The digitizer also includes means for
operatively coupling the strobe pulses to the latch enable input of the
comparator for repeatedly strobing the comparator at a selected sample
point in time until the feedback of the integrated output signal forces
the signal present at the reference input of the comparator to be equal to
the sampled value of the input waveform signal being tested, at which time
the feedback signal oscillates about the sample value and the loop
settles. An analog-to-digital conversion device reads the final value once
the loop is settled, and converts it into a digital equivalent value of
the time and digital equivalent value of the amplitude of the sampled
value and other parameters for storage and software processing and
analysis in the digital computer.
Preferably, the entire process is under the program control of a digital
computer which serves as the control means, and the computer selects and
controls the programmable delay line for selecting the test point in the
waveform signal.
The source of waveform signals can be a device under test for outputting
the waveform signal or an external device responsive to a test stimulus or
the like. The source can be an external real time waveform signal and
means are provided for triggering on the signal for clocking the program
delay means. Similarly, a phase locked loop (PLL) can be used for locking
onto the signal and generating the programmed delay means.
Alternatively, a sampling waveform digitizer for accurately measuring
various parameters on a test device such as settling time of a high speed
digital-to-analog converter, can be provided which includes a digital
computer, means for generating a test stimulus, a polarity select means, a
programmable delay line, a comparator integrator loop for integrating the
input waveform, and analog-to-digital converter means for converting the
output to a digital representation and supplying it to the digital
computer.
The invention further contemplates an improved comparator-integrator loop
circuit including a T-filter means operatively disposed in a path between
the latching comparator output and the operational amplifier inputs for
smoothing out the signal spikes and controlling the integrator current and
thus the slope of the integrator for improved accuracy. Further, a similar
T-filter can be provided in the return loop for buffering the integrator
output from the disturbances which can result from clocking the latch
enable input of the latching comparator or from disturbances caused by the
switching action of the latching comparator input, for preventing ringing,
and for rounding out signal spikes in the feedback loop.
Still another embodiment provides a sampling waveform testing system for
dynamically testing a high speed sample and hold amplifier to measure such
parameters as acquisition time, aperture delay, sample-to-hold settling
time, glitch amplitude, slew rate, sample-to-hold offset, hold mode
feedthrough rejection, risetime, and the like. The testing system includes
a digital computer, means for generating clock signals, an 8 bit binary
counter for counting the clock signals and storing the count, and a
magnitude or amplitude comparator means for comparing the stored count
with the upper 8 bits of a 16 bit delay select control word output from
the digital computer. When a positive comparison indicates that the
signals are equal, an output is sent to the programmable delay line, which
stores the lower 8 bits of the 16 bit delay select control word for "fine"
tuning the delay signal, which is then differentiated and level-shifted to
provide the comparator strobe signal.
A shift register is provided for delaying the clock signals to generate a
first square wave test stimulus having a predetermined period and a second
shift register signal which is delayed a predetermined time period. An
additional means for delaying the first square wave test stimulus is used
to generate a polarity select signal and a fast settling square wave
generating means supplies a +5 volt square wave signal for dynamically
driving the sample and hold amplitude circuit under test. The hold/sample
select circuit responds to program control for generating a hold polarity
select signal which is supplied to the hold input of the sample and hold
device under test. Both the square wave test stimulus and the sample/hold
sample select signal can be programmably controlled via the polarity
select circuitry to have the square wave generator or sample and hold
circuit utilize the input, invert the input, or ignore the input signal.
An output circuit, including a plurality of comparator-integrator loops,
is used for sampling and integrating various signals from the S/H under
test and generating final values as previously indicated. The loop means
includes latching comparators and analog output integrators, together with
the modified T-filter means for improving the performance of the
comparator-integrator loop. An analog multiplexer determines which of the
outputs of the particular loop means or individual comparators is to be
read at a particular moment in time and the reading is supplied to an
analog-to-digital converter for supplying the digital equivalent thereof
to the digital computer for storage, and further processing and analysis.
The present invention provides a highly accurate and flexible measurement
technique and apparatus which achieves previously unattainable results in
the measurement of settling time and also meets all the essential
requirements of a production tester. The present system can easily be
adapted to measure the dynamic characteristics of operational amplifiers,
digital-to-analog converters, sample and hold amplifiers, and other analog
system components, regardless of their high speed operation. Additionally,
the flexibility of the present system makes it suitable for testing the
dynamic switching characteristics of digital logic circuits as well.
Other advantages and meritorious features of the present invention will be
more fully understood from the following detailed description of the
drawings and the preferred embodiment, the appended claims, and the
drawings which are described briefly hereinbelow.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the sampling waveform digitizer of the present
invention;
FIG. 2 is a block diagram of the functional equivalent of a conventional
comparator whose output is latched with a "D"-type flip-flop;
FIG. 3 is a block diagram of a true latching comparator as used in the
present invention;
FIG. 4, including 4(a), 4(b), 4(c), and 4(d), is a waveform diagram
illustrating the sampling digitization process of the present invention;
FIG. 5 is a block diagram of a conventional comparator-integrator loop;
FIG. 6, including 6(a), 6(b), 6(c), and 6(d), are waveform diagrams
illustrating the integrator error calculation for the system of the
present invention;
FIG. 7 is a waveform of an oscillatory settling response which exceeds the
limits of a predefined error band between samples;
FIG. 8 is a block diagram of an automated tester used for measuring the
settling time of a 12 bit DAC whose current mode output reaches 1/2 LSB
accuracy in under 40 nanoseconds;
FIG. 9 is a partial block diagram, partial electrical schematic diagram of
the 8 bit delay line, strobe generator, comparator-integrater loop,
programmable voltmeter, and bus of the block diagram of FIG. 8.
FIG. 10 is a partial block diagram, partial electrical schematic diagram of
the clock, the delay, the level translation and polarity selection
circuitry of the block diagram of FIG. 8;
FIG. 11 is a block diagram of the dynamic tester for sample and hold
amplifiers which measures acquisition time, sample-to-hold settling time,
aperture delay, glitch amplitude, and slew rate, and the like of the
present invention;
FIG. 12 is a partial block diagram, partial schematic diagram of the
magnitude comparators, 8 bit counters, 8 bit delay line, flip-flop, shift
register, and delay circuitry of the block diagram of FIG. 11;
FIG. 13 is a partial block diagram, partial schematic diagram of the square
wave generator, polarity select circuitry, hold polarity select circuitry,
strobe generator circuitry, level translation circuitry, clock circuitry,
sample and hold under test device, switching circuitry, analog multiplexer
circuitry, start test circuitry, and indicator circuitry of the block
diagram of FIG. 11;
FIG. 14 is a partial block diagram, partial schematic diagram of the hold
comparator circuitry, output comparator-integrator loop circuitry, error
signal loop circuitry, and input loop circuitry of the block diagram of
FIG. 11;
FIG. 15 is a schematic diagram of the square wave generator circuitry of
the block diagram of FIG. 11;
FIG. 16 represents a computer printout plot of the measured acquisition
time characteristic in which t=0 corresponds to the hold-to-sample
transition;
FIG. 17 shows the computer printout plot of the detailed settling
characteristic as measured at the false summing node of the sample and
hold amplifier under test;
FIG. 18 is a Schottky diode network for generating a calibration standard
to validate the testing results;
FIG. 19 is a computer plot of the waveform resulting from the Schottky
diode turn-off waveform as measured on the digitizer system of the present
invention;
FIG. 20 is a broad generalized block diagram of an alternate embodiment of
the sampling waveform digitizer contemplated by the present invention; and
FIG. 21 is a schematic diagram of an improved comparator-integrator loop
usable in the present system.
FIG. 22 is a block diagram of an alternate embodiment for implementing the
comparator-integrator loop by replacing the integrator with a suitable
logic network and a DAC to form an Analog-to-Digital conversion loop.
DETAILED DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the sampling waveform digitizer of the present
invention. The output of a test signal generator 22 is supplied as a test
stimulus to a device under test 23. The output of the device under test is
supplied to the inverting or signal input of a latching comparator 27 of a
comparator-integrator loop 26. An output of the test signal generator 22
is also supplied as an input to a digitally programmable delay 24 which is
controlled by control signals or commands from a digital control computer
25. The output of the digitally programmable delay 24 produces strobe
pulses which are supplied to the latch enable input of the latching
comparator 27 for strobing the input to sample the waveform signal present
at the inverting input. The output of the latching comparator 27 is
connected to one terminal of a resistor 32 whose opposite terminal is
connected to the inverting input of an operational amplifier 28. The
operational amplifier 28 includes an integrating capacitor 29 operatively
coupled between the inverting input and the analog amplifier output node
33 for forming an integrator 31. The integrator output node 33 is
connected via feedback loop 34 to the non-inverting reference input of the
latching comparator 27 to complete the formation of the
comparator-integrator loop 26. The integrator output 33 is also connected
to an input of an analog-to-digital converter 35 which is controlled under
command of the computer 25 to output the digital equivalent of the
integrated sampled value present at the integrater output 33 and for
transferring the digital equivalent thereof to the computer for storage
and for future processing and/or analysis.
The operation of the block diagram of FIG. 1 will now be briefly described
with reference thereto. The waveform under test is supplied from the
output of the device under test 23 and fed to the inverting or signal
input of the latching comparator 27. The comparator's digital output is
integrated by the operational amplifier 28 and integrating capacitor 29
combination 31, and the integrator output 33 is fed back via feedback lead
34 to the non-inverting or reference input to the latching comparator 27.
The test signal generator 22 supplies a signal to the input of the
digitally programmable delay 24 which selects, under computer command, a
predetermined delay which is used to generate the strobe signals for
sampling the latching comparator 27. As the latching comparator 27 is
repeatedly strobed by the pulses at the latch enable input, the waveform
signal at the inverting input is repeatedly sampled and integrated by the
integrator 31. The signal at the integrator output 33 ultimately forces
the signal present at the non-inverting input of the latching comparator
27, via feedback lead 34, to equal the sampled value and produce an
equilibrium condition when the integrator output oscillates about the
sampled value. Once the loop settles, this final value is read by the
analog-to-digital converter 35 and sent to the computer 25 for storage and
further processing.
The latching comparator 36 of FIG. 2 is functionally equivalent to a
conventional comparator 37 whose output is latched with a "D"-type
flip-flop 38. The comparator's strobe input would then correspond to the
clock input of the flip-flop 38.
However, in a true latching comparator, such as shown in FIG. 3, the
latching action occurs in the analog input stage 40 of the latching
comparator 39. The latching comparator 39 also has output stages 41, an
inverting or signal input lead 43, a non-inverting or reference input lead
44, and a strobe input lead 42 operatively coupled to a latch enable input
in the first analog input stage 40 of the comparator 39. The output stages
41 supply the output or differential output signals via lead 45, as
conventionally known in the art.
Since the latching action occurs in the analog input stage 40 and since the
analog input stage 40 has only moderate gain but very high bandwidth, the
propagation delay and bandwidth limitation in the high gain output stages
do not affect the accuracy of the measurement of the sample taken by the
latching flip-flop 39. Because the latching event is edge-triggered, the
effective aperture time is well under 500 picoseconds.
The repetitive sampling technique, often referred to as "equivalent time
sampling", has several important advantages over transient recorders or
window comparator methods. First of all, random noise in the system is
averaged out by the operational amplifier integrator 31. The effectiveness
of this noise averaging is determined by the integration constant and the
number of samples taken at each time point. This is in contrast to the
single shot "transient recorder" type of digitizer in which the sample and
hold amplifier acts as a peak detector for the system noise.
Secondly, the operational amplifier integrator 31 operates at very low
frequencies, essentially DC, relative to the waveform under test. Only the
comparator input circuitry is required to track the input waveform and so
there is no need for a precision high speed amplifier, which is a
significant limitation in conventional sampling systems.
A third important advantage of the repetitive sampling technique used in
the present invention is that the measurement resolution is not limited by
the comparator's tendency to oscillate for very small differential input
voltages. In other systems, this "oscillation band" which is typically 1
to 5 millivolts for high speed comparators, is a significant resolution
limit. The oscillation can be prevented by adding positive feedback, but
the resultant hysteresis around the comparator trip point is also
detrimental to the system accuracy.
In the sampling waveform digitizer of the present invention, this
oscillation is prevented by strobing the latching comparator with a
relatively narrow pulse (5 to 10 nanoseconds wide). This enables the
feedback loop to track the sampled value with far greater precision than
the "oscillation limit" would suggest. In the present system, the
resolution limit is approximately 50 microvolts or roughly 50 times more
precise than the accuracy of the comparator alone.
The selection of the integration constant is important in order to maintain
this resolution. The intergrator output slope must be small enough so that
the
##EQU1##
integrator output changes by a negligible amount between samples. One
sample is taken per cycle of the input waveform so that the time between
samples is equal to the period T.sub.o :
t.sub.between samples =T.sub.o =1/f.sub.o
If the difference .DELTA. V.sub.max represents the largest allowable
integrator error, the maximum slope is calculated by the equation:
##EQU2##
where I.sub.IN is determined by the value of the integrator input resistor
R.sub.IN and the magnitude of the comparator's output voltage.
FIG. 4 shows the waveform digitization technique of the present invention,
while FIG. 5 may be used to understand the equations presented herein.
FIG. 6 shows the waveforms used to calculate integrator error as follows.
The correct sampled value will not necessarily equal the average value of
the integrator output, but may lie anywhere between the positive and
negative limits as seen in FIG. 6. Thus, it is important to select a small
enough value for .DELTA.V.sub.max. For example, if the waveform under test
has a frequency of 1 MHz and the maximum allowable error is set to be 50
microvolts, the integration constant will be:
##EQU3##
In the case of a lower frequency waveform which must be measured to a very
high degree of accuracy, the I.sub.IN/CF ratio will be much smaller. As
the output slope decreases, it may begin to take an intolerably long time
for the comparator-integrator loop to acquire a full scale step change. In
that case, the integrator can be designed with a variable I.sub.IN/CF
which can be large enough to allow for fast acquisition of large changes
in the sample value and small enough to allow for precision tracking.
The selection of the sampling increment is also important because the
digitizer operates in a synchronous sampling mode rather than in real time
so that the time base resolution may be arbitrarily small. The
programmable delay line used in the present system is variable in 1
nanosecond increments, yielding a maximum effective "sampling rate" of 1
GHz. This allows for accurate delay and risetime measurements, but it does
not imply that the system can digitize a 1 GHz waveform. The bandwidth of
the comparator input stage is limited to about 100 MHz which is adequate
for the devices under consideration. If it becomes desirable to accurately
digitize higher frequency components, a latching comparator with a higher
frequency input stage, and a shorter aperture time would be required.
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