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Claims  |
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What is claimed is:
1. A computer system, comprising:
a central computer which performs concurrently executing selected ones of
plural programs;
a plurality of operator terminal means connected to said computer for
exchanging commands and data required to request said computer to execute
a selected one of said plural programs between said computer and each
terminal means so as to receive and output data corresponding to results
of execution of the selected one of said plural programs;
monitor means connected to said plurality of terminal means for detecting a
first condition that at least one of the plurality of terminal means is in
an operational status, and a second condition that all of the terminal
means are in a non-operational status; and
control means connected to said monitor means and said computer and
responsive to detection of said first condition for starting supply of
power to said computer to turn on said computer and for thereafter
instructing said computer to execute initialization processing for an
operating system program included in said computer, and responsive to the
detection of said second condition for instructing said computer to
execute termination processing for the operating system program and for
thereafter terminating the supply of power to said computer so as to turn
off the computer.
2. A computer system according to claim 1, where in said control means
includes means connected to said monitor means and responsive to detection
of the second condition after starting of power supply to said computer
and before completion of execution of the initialization processing by
said computer for instructing said computer to execute to execute the
termination processing, after completion of the execution of the
initialization processing by said computer.
3. A computer system according to claim 1, wherein said control means
includes means connected to said monitor means and responsive to another
detection of the first condition after detection of the second condition
and before completing execution of the termination processing by said
computer for instructing said computer to execute the initialization
processing after completion of the termination processing
4. A computer system according to claim 1, wherein said control means
includes means connected to said monitor means and responsive to detection
of the second condition after starting of power supply to said computer
and before completion of execution of the initialization processing by
said computer for instructing said computer to execute the termination
processing, after completion of the execution of the initialization
processing by said computer and responsive to another detection of the
first condition after detection of the second condition and before
completing execution of the termination processing by said computer for
instructing said computer to execute the initialization processing after
completion of the termination processing.
5. A computer system according to claim 1, wherein said monitor means
includes:
a plurality of detect means, each corresponding to one of the plurality of
terminal means, respectively, for detecting an operation status thereof
and means connected to said plurality of detect means for detecting the
first and second conditions in response to outputs of said plurality of
detect means.
6. A computer system according to claim 5, wherein each detect means
includes means connected to switch means provided in said corresponding
terminal means for detecting the operation status thereof based on whether
the switch means turns on or off, wherein said switch means is an operator
power switch means for controlling power supply to said corresponding
terminal means.
7. A computer system according to claim 6, wherein each terminal means
comprises video data terminal means including keyboard means connected to
a video display means.
8. A computer system according to claim 4, wherein said monitor means
includes:
a plurality of detect means, each for a corresponding one of the plurality
of terminal means, for detecting an operational status of the correspond
terminal means and means connected to said plurality of detect means for
detecting the first and second conditions in response to outputs of said
plurality of detect means.
9. A computer system according to claim 8, wherein each detect means
includes means connected to switch means provided in said corresponding
terminal means for detecting the operation status thereof based upon
whether the switch means turns on or off, wherein said switch means is an
operator power switch means for controlling power supply to said
corresponding terminal means.
10. A computer system according to claim 9, wherein each terminal means
comprises video data terminal means including keyboard means connected to
a video display means.
11. A computer system, comprising:
a central computer which performs concurrently executing selected ones of
plural programs;
power supply means connected to said central computer for supplying power
thereto;
a plurality of operator terminal means connected to said central computer
for exchanging commands and data between said central computer and each
terminal means so as to request said central computer to execute selected
ones of said plural programs and so as to receive and output data
corresponding to results of execution of the selected ones of said plural
programs;
monitor means connected to said plurality of terminal means for monitoring
an on or off operational status of said plurality of terminal means; and
control means connected to said monitor means and said power supply means
for instructing said power supply means to start a supply of power to said
central computer to turn on said central computer when said monitor means
detects that any one of said plurality of terminal means is put into said
on operational status and for instructing said power supply means to
terminate the supply of power to said central computer when the monitor
means detects that none of said terminal means is in said on operational
status; wherein said power supply means includes means connected to said
control means and responsive to one command provided from said control
means to effect starting of the supply of power for instructing said
central computer to execute initialization processing for an operating
system program include in said central computer after start of the supply
of power, and responsive to another command provided from said control
means to effect terminating of the supply of power instructing said
central computer to execute termination processing for the operating
system program before termination of the supply of power thereto.
12. A computer system according to claim 11, wherein each of said terminal
means includes switch means to control said operational status, and said
monitor means includes means for detecting whether or not said switch
means provided in each of said plurality of terminal means is turned on in
order to monitor the operational status of each terminal means.
13. A computer system according to claim 12, wherein said switch means
comprises power switch means for controlling the supply of power to each
terminal means from said power supply means.
14. A computer system according to claim 11, wherein said power supply
means includes means connected to said control means and responsive to
receipt of said another command to effect terminating of the supply of
power after receipt of an instruction to effect starting of the supply of
power and before completion of execution of the initialization processing
by said central computer required by receipt of said one command to effect
starting of the supply of power for providing said central computer with
an instruction to effect execution of the termination processing, after
completion of the execution of the initialization processing by said
central computer.
15. A computer system according to claim 11, wherein said power supply
means includes means connected to said control means and responsive to
receipt of said one command from said control means to effect starting of
the supply of power, after receipt of said another command to effect
termination of the supply of power and before completion of executing the
termination processing by said central computer required by receipt of
said another command to effect termination of the supply of power, for
providing said central computer with the command to effect execution of
the initialization processing for the operating system program after
completion of the termination processing by said central computer.
16. A computer system according to claim 1, wherein said control means
includes a power supply means for supplying said power to said computer.
17. A method of automatically controlling on/off status of a main power
supply to a central computer system including a plurality of terminal
devices which can request processing, comprising the steps, performed
entirely by a monitor circuit in computer system in an automatic manner
of:
monitoring said plurality of term request processing;
detecting a power-on status of at least one of said plurality of terminal
devices;
starting the power supply to said computer system in response to the
detection of a power-on status of at least one of said plurality of
terminal devices;
detecting a power-off status of all of said plurality of terminal devices;
terminating the power supply to all of said plurality of terminal devices
in response to the detection of a power-off status of all of said
plurality of terminal devices.
18. A method of automatically controlling on/off status of a main power
supply to a central computer system including a plurality of terminal
devices which can request processing, comprising the steps, performed
entirely by a monitor circuit in said computer system in an automatic
manner, of:
monitoring each of said plurality of terminal means
detecting a first condition that at least one of the plurality of terminal
means is in an operational status;
starting a power supply to said computer in response to detection of said
first condition;
instructing said computer to execute an initialization processing for an
operating system program in said computer;
detecting a second condition that all of said plurality of terminal means
are in a non-operational status;
instructing said computer to execute a termination processing for said
operating system program in response to detection of said second
condition;
terminating the power supply to said computer so as to turn off said
computer after execution of said termination processing. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer system which automatically
controls the on/off status of the power thereof and the start/stop of its
operating system, by constantly monitoring the operational status of
terminals.
2. Description of the Prior Art
In recent years, together with the development of the use of computer
systems, the mode of using such computer systems has shifted from that
concentrating on batch job processing to that concentrating on interactive
processing using terminals, as exemplified by the TSS (Time-Sharing
System). Especially in application fields in which computers are used for
experimenting with and controlling instruments or the like (laboratory
automation field), an experimenter will often conduct experiments and
operate controls while conversing with a computer using terminals
connected to the computer. In the field of laboratory automation
(abbreviated hereinafter to "LA"), moreover, it is desirable that the
researcher or experimenter be able to use the computer system as soon as
an idea for an experiment occurs.
In order to satisfy that desire, it is necessary that the computer be
capable of operating for 24 hour without interruption.
Usually, in LA using a computer system, a large computer and a minicomputer
are hierachically connected so that large-scale data analysis is assigned
to the larger computer, whereas the operation control and data gathering
of experiment equipment are assigned to the smaller computer. Together
with the improvement in processing capacity of minicomputers moreover, a
method has been adopted in which a single minicomputer is shared by
several experiment rooms and users, and is installed in a place remote
from the experiment rooms. Of course all the operations in LA from the
control of the experiment equipment to the data analysis may be performed
by a large computer alone, without using a minicomputer.
As has been described above, it is desirable that an experimenter can
promptly use a computer, even if it is midnight or a holiday, if he wants
to. For this purpose, continuous 24-hour service is an essential condition
for a computer system. When batch job processing and interactive
processing such as TSS are combined, as in a large computer system, the
continuous 24-hour service increases the utilization of the computer to a
significant degree. However, if a computer assigned to experimental
control alone is subjected to continuous 24-hour service, it is in
operation even when it is not being used for experimental control. This
reduces the utilization of the computer, and also wastes power.
If the computer operates only when it is required for controlling
experiment equipment, on the other hand, the following problems arise: (i)
an operator must be assigned to administer the operation of the system for
each of several minicomputers and (ii) the experimenter must go to the
remote place, in the absence of the operator, to start the supply of power
to the computer system and initialize the system, or turn off the power
supply and the system.
As a result of the increase in the necessity for continuous 24-hour service
of computer systems, an automatic power on/off system has been proposed as
one of the supports of an unsupervised computer system, in which the
operation of the computer system is started or terminated at a
predetermined time. However, this system is time-dependent, not
user-dependent, so that the problem remains that the user is still
inconvenienced.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a
user-dependent computer system which starts the power supply to the system
when at least one of a group of terminal devices which can ask the
computer processor for processing is activated, and terminates the power
supply when all the terminal devices are inactivated.
In order to achieve this object, the computer system according to the
present invention is characterized in that it monitors all the terminal
devices which can request processing, and starts the power supply means
when it detects the power-on status of at least one of these terminal
devices, and terminates the power supply means when it detects the
power-off status of all the terminal devices.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features and advantages of the present invention will become
apparent from the following description taken in conjunction with the
accompanying drawings, in which:
FIG. 1 is a block diagram of a terminal-oriented computer system according
to one embodiment of the present invention;
FIG. 2 is a block diagram of the interior of the terminal control equipment
of FIG. 1;
FIG. 3 is a block diagram of a send/receive control unit (COMC) controlling
communications with the terminals of FIG. 2;
FIG. 4 is a block diagram of the monitoring control unit (WATCH) of FIG. 2;
FIG. 5 is a block diagram of one of the terminals of FIG. 1;
FIG. 6 is a table of the assignments of individual bits of the last byte on
the address bus of FIG. 2;
FIG. 7 is an operation flow chart of a terminal status-monitoring program;
FIG. 8 is a table of the control blocks used by the terminal
status-monitoring program; and
FIG. 9 is a block diagram of the power control unit of FIG. 1.
DESCRIPTION OF PREFERRED EMBODIMENT
FIG. 1 is a block diagram of a terminal-oriented computer system according
to one embodiment of the present invention. Reference numeral 1 denotes a
central processing unit (CPU), numeral 2 a main storage device (MS),
numeral 3 a channel (CH), numeral 4 a power control unit (PWR), numeral 5
a panel (PNL), numeral 6 a disk storage unit (DISK), numeral 7 denotes a
magnetic tape unit (MT), numeral 8 a unit record device including a card
reader (CR) and a line printer (LP), numeral 9 an input/output control
unit (CU), numeral 10 terminal control equipment (TCE), and numeral 11 a
video data terminal (VDT).
The present invention is characterized in that the TCE 10 and the PWR 4 are
provided with special control circuits.
Although only one TCE 10 is provided in FIG. 1, a plurality of TCEs may be
connected to the CH 3.
The TCE 10 controls the several VDTs 11, and is provided with a special
control circuit which is operated by a power supply separate from that of
the main TCE 10, such as a battery, so that it monitors the usage status
of the VDTs 11 at all times, using that special control circuit. If any
one of the VDTs 11 is activated, e.g., if the power to a VDT 11 is turned
on by the user, a corresponding signal is sent to the PWR 4 of the
computer. PWR 4 turns on the power when it receives the status signal, to
generate a trigger signal for starting the initialization of the operating
system (OS), so that the computer system is started. As a result, the
computer system can be used. After the computer system has operated, the
special control circuit in the TCE 10 sends, when the power to all the
VDTs 11 is turned off, a status signal to the PWR 4. As a result, the PWR
4 interrupts to the OS as an external interruption in the CPU 1 of the
computer. The OS sends a power-off instruction to the PWR 4 when it
detects the interruption, after it has conducted system termination
processing, to cut the power-supply to the computer system. In short, the
computer system is operated by the terminal orientation.
The special control circuits (the circuits monitoring the power on/off
status of all the VDTs 11 connected to the TCE 10), which are built into
the TCE 10 operate using a common internal data bus for the usual data
send/receive operations within the TCE 10, and are driven by a power
supply which is different from that of the circuits for the usual data
send/receive operations.
Even if the power to all the VDTs 11 is turned off before or during
initialization after the supply of power to the computer system has
started, so that a status is produced in which the power supply to the
computer system is to be cut, this termination is controlled so that it
does not occur until after the completion of the initialization of the OS.
On the other hand, if it is detected that the power to all the VDTs 11 is
off, so that the termination processing of the OS is conducted to cut the
power supply to the termination computer system, the report that the power
is on is ignored until the processing of the OS and the processing
interrupting the power supply to the computer system ends, even if it is
detected that the power to one or more VDTs 11 is on so that power is
supplied to the computer system.
The transmission and reception of signals between the individual components
and the PWR 4 will be described in more detail in the following.
The TCE 10 always monitors the status of the group of VDTs 11, and the
monitored result is reported over a signal line L1 to the PWR 4. If the
power to one of the VDTs 11 being monitored by the TCE 10, e.g., the
lefthand VDT 11, is turned on, the signal on the signal line L1 becomes
"1", which is reported to the PWR 4. When there are a plurality of TCEs
10, incidentally, a logical or of the signals on the signal line L1, sent
from the individual TCEs 10, is taken and the resultant output is reported
to the PWR 4. A signal giving the current monitor mode is input to the PWR
4 over a signal line L2 from the PNL 5. The monitor mode is either a mode
in which the computer operates while monitoring the terminal status (the
signal on the signal line L2 is "1") , or a mode in which the computer
operates while ignoring the terminal status (the signal on the signal line
L2 is "0") . The designation of these modes is done by a node switch on
the PNL 5, and is reflected by the signal on the signal line L2. A trigger
signal for turning on and off the power to the PNL 5 is input over a group
of signal lines L3 from the PNL 5 to the PWR 4. Power is supplied from the
PWR 4 to the individual components over a line L4. A power supply
termination, i.e., a request signal for turning off the power, is input
from the CPU 1 to the PWR 4 over a signal line L5.
A signal line L6 transmits an initialization request signal from the PWR 4
to the CPU 1, and a signal line L7 transmits the information that the
computer is in operation from the CPU 1 to the PWR 4.
When the mode of the computer is system such that it does not monitor the
status of the VDTs 11, i.e., if the signal on the signal line L2 from the
PNL 5 is at "0", the power supply to the computer system and the
termination method by the PWR 4 is the same as that known in the prior
art.
A method of controlling the power supply and the termination of the
computer system when the mode is monitoring the status of the VDTs 11,
i.e., when the signal on the signal line L2 from the PNL 5 is at "1", and
a method of controlling the operation start and termination processing of
the computer system are proposed by the present invention.
The special control circuits for monitoring the VDTs 11 are built into the
TCE 10 and are operated by a stand-alone power supply such as a battery
which is independent of the power supply of the TCE 10. If any one of the
VDTs 11 is activated, the signal on the signal line L1 becomes "1", and
this is reported to the PWR 4. The PWR 4 starts to supply power over the
power supply line L4 to the individual components of the computer system
when the mode signal supplied from the PNL 5 over the signal line L2 is at
"1".
After the lapse of a predetermined period (usually after about one minute),
a request for the loading of a microprogram and initialization by loading
the OS into the MS 2 from the DISK 6 is made to the CPU 1 over the signal
line group L6. The microprogram is loaded into the CPU 1 when the CPU 1
receives the request signal L6 from the PWR 4, and then the basic portion
of the OS is loaded into the MS 2 from the DISK 6 and initialization is
done with the program in the basic portion of the OS. The initialization
of the OS means that the basic portion of the OS, when loaded into the MS
2, consecutively loads the program groups necessary for the OS operation
into the MS 2, and then either sets a constant value or starts a TSS job
and an on-line program and activates a job queue file. When the
initialization of the OS is completed, the researcher or experimenter can
freely use the computer system from any of the group of terminals VDT 11.
Interruptions to the computer system and the power supply are conducted in
the following manner.
A monitor circuit built into the TCE 10 reduces the signal on the signal
line L1 to "0" when it detects that all the VDTs 11 are not in use, i.e.,
that the power supply to all the terminals is off. The PWR 4 reports an
external interruption signal indicating "system termination" to the CPU 1
by using one of the group of signal lines L6, after it has confirmed that
the terminal monitor mode sent from the PNL 5 over the signal line L2 is
"1".
When an external interruption signal is generated for the CPU 1, an
external interruption program of the OS operates to identify that the
reason for the external interruption is "system termination". Reason codes
for external interruptions are stored in a predetermined storage area of
the MS 2 by an external interruption circuit (not shown) of the CPU 1.
A system termination program of the OS thin operates to issue a "power-off
request" command to the PWR 4 after the termination processing of the OS.
The termination processing of the OS is a reverse process to the
initialization, and consists of the following specific processes: the
termination of the TSS job, the termination of any on-line programs, the
process of inactivating the job queue file, the termination of the
accounting file gathered in the OS; the termination of any job being
executed; and data storage for restart. The job queue file provides
openings for receiving batch jobs, and for storing job numbers in the
order they were received.
The execution of a "power-off request" command reports a signal indicating
this request to the PWR 4 from the CPU 1 over the signal line L5. The PWR
4 starts a relay circuit of the power supply circuit to interrupt the
power supply when it receives the power-off request.
The status of terminals remote from the computer system, as stated above,
makes it possible to turn on or off the power supply to the computer
system, and start or interrupt the OS operated by the computer system.
The operations of each of the terminal status monitor circuit in the TCE 10
and the control circuit in the PWR 4 will be described in the following.
FIG. 2 is a block diagram of the TCE 10. Reference numeral 12 denotes a
micro central processing unit (.mu.CPU) which is mounted in the TCE 10 to
control the transmission and reception of data between the CH 3 and the
VDTs 11 of FIG. 1. Numeral 13 denotes a channel input register (CINREG)
which holds data sent out from the CH 3, numeral 14 denotes a channel
output register (COUTREG) which holds data to be sent to the CH 3, numeral
15 denotes a memory (which is composed of a RAM), numeral 16 denotes a
send/receive control unit (COMC) which sends and receives data to and from
the VDTs 11, numeral 17 denotes a monitoring control unit (WATCH) which is
added according to the present invention to monitor the status of the VDTs
11, numeral 18 is a battery (BATTERY) driving the COMC 16 and the WATCH
17, numeral 19 denotes an interruption control unit, and numeral 20
denotes a decoder which addresses each of the parts in the TCE 10, and
which receives address data from an address bus L11 as an input. Data on
the address bus L11 is also sent to the COMC 16. A data bus L10 is used in
common for the usual operations of sending and receiving data, and also
for the monitoring operation of the WATCH 17.
FIG. 3 is a block diagram of the internal structure of the COMC 16 of FIG.
2, FIG. 4 is a block diagram of the internal structure of the WATCH 17 of
FIG. 2, and FIG. 5 is a block diagram of the structure of one of the VDTs
11 connected to the TCE 10.
With reference to FIGS. 2 to 5, the usual data transmission and reception
operations, and the operations of monitoring the power-on or power-off
status of the VDTs 11 will be described in the following.
As shown in FIG. 2, when data is sent from the CH 3 to the VDTs 11 of the
computer system, the data is received in the CINREG 13 over a data line
L14. The data in the CINREG 13 is one byte long (or eight bits long) and
is sequentially transferred to the memory 15 by the .mu.CPU 12.
When the data transmission from the CH 3 ends, the .mu.CPU sends a data
train which has been temporarily stored in the memory 15 over the data bus
L10 to the COMC 16. When data is being transmitted, a number is sent on
the address bus L11 indicating which of the terminals VDT connected to the
TCE 10 is the addressee.
The address bus is constructed so that it is two bytes long, for example,
so that only the latter byte is sent to the COMC 16. The meanings of the
individual bits of data within that one byte are tabulated in FIG. 6. More
specifically bit position 0 corresponds to a flag showing that the .mu.CPU
12 is using the COMC 16, and indicates whether or not the data bus L10,
the address bus L11 and the COMC 16 are being used for transmitting and
receiving data between the .mu.CPU 12 and a VDT 11. Therefore, "1" means
"in use" and "0" means "not used". As a result, this is at "1" when data
is sent or received through the .mu.CPU 12. Bit position 1 indicates the
start of timing of the data transmission and reception signals, and bit
positions 3 to 7 give the terminal number.
The COMC 16 sends a signal over a signal line L12 to the interruption
control unit 19 to report that every byte length of data from the .mu.CPU
12 is sent out sequentially bit-by-bit to the VDT 11. In response to this
interruption, the .mu.CPU 12 identifies that the one-byte data
transmission has terminated, extracts the next data from the memory 15,
and repeats these data-transmission operations.
In the COMC 16 of FIG. 3, reference numeral 21 denotes an address register
(AREG), numeral 22 a data register (DREG), numeral 23 a decoder, numeral
24 a timing control circuit used when parallel data and serial data are
converted, and numeral 25 denotes a send/receive control unit. The
send/receive control unit 25 is composed of serial/parallel converter 26
(SERPARA) which converts serial data to parallel data and vice versa, and
a send/receive circuit 27 which transmits and receives the data for each
bit, and controls the data transmission and reception operations with the
VDTs 11. A maximum of thirty-two send/receive control units 25 can be
provided, one for each of the VDTs 11.
Each terminal number is determined, as shown in FIG. 6, by the values of
bit positions 3 to 7 within the byte, which are held in the AREG 21 of the
COMC 16.
In FIG. 3 reference numeral 28 denotes a status register, numeral 29 an OR
circuit, numerals 30 and 32 AND circuits, and numeral 33 a gate circuit.
In the TCE 10, the one-byte long data sent from the .mu.CPU 12 is stored in
the DREG 22 of the COMC 16 through the data bus L10. The operational
status (i.e., bits 0 to 2) sent over the address bus L11 and the terminal
number (bits 3 to 7) are held in the AREG 21. A maximum of 32 terminal
numbers, e.g., 0 to 31, can be assigned with this system, but this can
easily be increased by changing the number of bits. In response to an
instruction from the .mu.CPU 12, an action-start signal is sent over a
signal line L15 to the OR circuit 29 to open the gate 33. Thus, one of the
send/receive control units 25 is selected in accordance with the result
obtained by the decoder 23. The data in the DREG 22 is transferred to the
SERPARA 26 and is simultaneously set in the status register 28.
Bit position 0 in the status register 28 during normal data transmission
and reception operations is "1", and bit position 1 is "1", as shown in
FIG. 6. Next, the value of bit position 1 of the status register 28 is
reported over a signal line L18 to the timing control circuit 24, which
sends out timing signals at the same rate as the transmission speed of the
transmission or reception of data to the SERPARA 26. The SERPARA 26 is
composed of a shift register and data is sent therefrom bit-by-bit in
response to the timing signals through the send/receive circuit 27 to the
corresponding VDT 11. When the transmission terminates, a termination
report is sent through the AND circuit 30 to the interruption control unit
19 of FIG. 2 over the signal line L12, until it reaches the .mu.CPU 12. By
repeating the operations described above, data is sent from the computer
system through the TCE 10 to the VDT 11.
The normal data-reception operation will be described in the following. The
description of how data (e.g., the terminal number) is sent over the
address bus L11 by the .mu.CPU 12 will not be repeated, because it is
received by the same method as that of the data-transmission operation.
The data in one-bit units received from the VDTs 11 is stored in the
serial/parallel converter (SERPARA) 26 via the send/receive circuit 27.
The data in thin SERPARA 26 is the transferred to the DREG 22, and a
signal is then sent to the .mu.CPU 12 over the signal line L12. The
.mu.CPU 12 takes in the data on the data bus L10 in response to the signal
on the signal line L12, and sequentially stores it in the memory 15 of
FIG. 2. When the data reception from the VDT 11 terminates, the .mu.CPU 12
then transmits the received data in the memory 15 to the computer system
of FIG. 1 over the CH 3. More specifically, the .mu.CPU 12 sequentially
takes the data byte-by-byte from the memory 15 and sends it to the COUTREG
14 over the data bus L10. The addressing of the COUTREG 14 is done by the
decoder 20. The CH 3 takes in the data received from the VDT 11 by
removing the data held in the COUTREG 14, and sequentially stores the data
in the MS 2 of the computer system.
The description thus far made is directed to the normal data transmission
and reception operations of the TCE 10. WATCH 17 in the TCE 10 operates
independently to monitor whether the power to the VDTs 11 is on or off.
The monitoring of the VDTs 11 and the power supply, and the termination of
the computer system by the WATCH 17 and the COMC 16 will now be described,
including the processing done by the OS. The WATCH 17 and the COMC 16 are
driven by a power supply system which is different from the
circuit-driving power supply for the normal data transmission and
reception operations of the TCE 10, which is the BATTERY 18. However, the
COMC 16 can be driven by the power supplies of both systems.
The signal lines and circuits needed for monitoring the WATCH 17 are shown
in FIGS. 2 and 4. A signal line L13 transmits a signal requesting a
terminal status test from WATCH 17 to COMC 16, and a signal line L16
transmits a signal output from the status register 28 in the COMC 16 to
the WATCH 17. When the signal on the signal line L6 is "1", it means that
the .mu.CPU 12 is using the data bus line L10. When the operation
requesting WATCH 17 terminates, the signal on the signal line L7 becomes
"1". The signal line L1 transmits to the PWR 4 of FIG. 1 whether the power
of the group of VDTs 11 connected to the TCE 10 is on or off. When the
signal on the signal line L1 is "1", it means that the power of at least
one of the VDTs 11 is on. When that signal is "0", it means that the power
to all the VDTs 11 is off. The address bus L11 is used in common with the
.mu.CPU 12.
In the WATCH 17, as shown in FIG. 4, a separate micro central processing
unit (.mu.CPUA) 38 provides control, independently of the .mu.CPU 12 in
the TCE 10. The WATCH 17 is driven by the battery supply (BATTERY) 18 of
FIG. 2. Reference numeral 39 in FIG. 4 denotes a memory which holds the
programs executed by the .mu.CPUA 38, and a control block for monitoring
the terminals which is addressed through a signal line L28. Numeral 40
denotes an input register (INREG) which is addressed by the .mu.CPUA 38
and which is uniquely identified by an output signal line L24 from a
decoder 42. Numeral 41 denotes an output register (OUTERG) which is
identified by an output signal line L25. Numeral 43 denotes an
interruption control unit of the .mu.CPUA 38 which is addressed over a
signal line L26, numeral 46 denotes a terminal status register which is
addressed over a signal line L27, and numeral 44 denotes a timer control
unit which generates an interruption in the .mu.CPUA 38 in a predetermined
cycle. The interruption-generating cycle can be freely set within a range
of between 30 seconds to 20 minutes, for example. Reference characters L20
and L21 denote an internal data bus and an internal address bus. The
internal address bus L21 is two bytes long for example, the last byte
(bits 8 to 15) of which is held in a bus register 45, as in the normal
data transmission and receptio | | |
