An address control system for a RAM, comprising a synchronous counter for receiving input data according to a clock signal and providing n-bit row column address, and an n-bit column address a first buffer for receiving the n-bit row address from the synchronous counter and generating the n-bit row address, a first tri-state inverter for outputting data stored in a ROM according to a write enable signal a second tri-state inverter for outputting reference data according to the write enable signal, an adder for adding the n-bit column address from the synchronous counter and output address signals from the first inverter, and a second buffer for receiving output signals from the adder generating a column address delayed from the n-bit column address.

A control system including a motherboard having at least two auxiliary card connectors and a control bus on which control addresses and control data are transferred. Auxiliary cards are connected to the auxiliary card connectors of the motherboard. The auxiliary cards are effectively identical but have different control addresses for selective controlling through the control bus. The control addresses of the auxiliary cards are card location-specific and provided on the motherboard by wiring or switches or in some other corresponding manner. When an auxiliary card is inserted in an auxiliary card connector of the motherboard, the auxiliary card always obtains the correct address from the motherboard through the connector.

Playback of pre-recorded messages to respond to caller inquiries has been subject to delays inherent in speech retrieval. Latent periods, both initial and intra-message, are reduced by breaking speech elements (words, phrases, sentences, etc.) into opening fragments and remaining portions. For each pre-recorded speech element for a particular application, an opening fragment (e.g., 4K bytes of speech data) is stored in active computer memory. The remaining portion of each speech element, regardless of length, is stored in a large capacity speech storage facility. For an incoming call, an appropriate responsive message is determined. The opening fragment of a pre-recorded speech element for that message is retrieved from active memory and used to initiate message transmission to the caller. Contemporaneously, a remaining portion of the speech element is retrieved from the storage facility and moved to active memory. By concatenation techniques, the remaining portion is transmitted to provide continuous speech to the caller.

A multi-channel digital random access recorder-player receives an analog audio signal, converts the audio signal into a digital signal, and stores the digital signal in a memory for random access. The memory includes sixteen channels, each channel having sixteen memory boards, each channel and each memory board being assigned a unique four bit binary address by an address counter. An external control is provided by which the user selects an address for recording or playback and a comparator compares the selected address with the addresses of the memory. When the memory address corresponding to the selected address is detected, that memory board is enabled so that data can be recorded on the memory board or retrieved from the memory board for playback through an audio output device such as a loudspeaker. The recorder-player thereby provides random access to a memory. Also provided is a system in which several modules, each with a logic board and a memory, are combined into a single system.

A dual-access protected electronic mass memory unit, the various elements of which comprise a plurality of logic boards connected to at least one peripheral controller (CNT.sub.1, CNT.sub.2) of the information processing system (H) to which the unit belongs. The electronic memory unit includes at least one electronic disk unit (DEI.sub.1, DEI.sub.2) including a motherboard (11, 21) containing the corresponding controller (CNT.sub.1, CNT.sub.2), and a plurality of daughter boards (12-13, 22-23) comprising an equal number of memory planes connected among one another two-by-two, the first of them being connected to the motherboard. The central processor and the electronic disk unit are connected by the motherboard to a first and second parallel bus (B.sub.1, B.sub.2).