A broadband space switch matrix constructed from a plurality of NAND gates arranged into a set of cascaded stages to form a tree-switch multiplexing configuration. A plurality of input digital signals are applied to input ports coupled to the NAND gates in the first stage. A selected one of the input signals emerges as an output signal from an output port coupled to a single NAND gate in the last stage. Each NAND gate has a select line for receiving control signals. The switching path for the selected input signal is established by placing the sequence of NAND gates defined by the selected switching path in a state of conduction whereby only the selected input signal propagates through the switch. This is effected by forcing to a HIGH state the particular NAND gates in each stage whose outputs are coupled to the same NAND gate in the following stage along with the output of the NAND gate in the current stage which is in the chosen path. The forced HIGH state is achieved by applying a LOW state signal to the respective select lines of the particular NAND gates. In an alternate arrangement, the NAND gates in the first stage are replaced by 2:1 pass-transistor-selectors which offer a reduction in the number of transistors.

A broadband space switch matrix includes a parallel combination of individual switch modules each comprising a cascade of pass-transistor selectors, NAND gates, and inverters arranged into a multi-stage tree multiplexing configuration. The switching speed is increased by isolating each switching crosspoint from the stray capacitive loading in the matrix.

In a small-size device, one input terminals of a plurality of AND circuits are connected in series. The other terminals of the plurality of AND circuits receive failure information held by a register circuit. Among the AND circuits, by changing values at the AND circuits which are connected in an output direction (i.e., most significant bit side) of an AND circuit receiving a failure bit and values at the AND circuits which are connected in an input direction (i.e., least significant bit side) of the AND circuit receiving the failure bit, a signal line associated with the failure bit is disconnected and signal lines are re-connected to adjacent signal lines including an extra line by selectors. Hence, a failure bit is compensated in a very simple structure.

An integrated circuit (IC) tester includes several processing nodes, each accessing a separate terminal of an IC to be tested. The tester receives as input a description of an integrated circuit test to be conducted. The description indicates actions to be taken at each processing node and a time relative to the start of the test that each action is to be taken. The actions may include transmitting a test signal to the IC or sampling an output signal produced by the IC. Before starting the test, the tester converts the description into a set of algorithms for generating test vectors and stores each algorithm in a separate processing node. The test is organized into a succession of test cycles and during the test, each node executes its stored algorithm, generating a separate test vector at the beginning of each test cycle. The test vector indicates an action to be taken by that node during the following test cycle along with a time during the test cycle that the action is to be taken. Each node includes circuits for executing the action at the time indicated.

In a small-size device, one input terminals of a plurality of AND circuits are connected in series. The other terminals of the plurality of AND circuits receive failure information held by a register circuit. Among the AND circuits, by changing values at the AND circuits which are connected in an output direction (i.e., most significant bit side) of an AND circuit receiving a failure bit and values at the AND circuits which are connected in an input direction (i.e., least significant bit side) of the AND circuit receiving the failure bit, a signal line associated with the failure bit is disconnected and signal lines are re-connected to adjacent signal lines including an extra line by selectors. Hence, a failure bit is compensated in a very simple structure.