 |
Claims  |
|
|
I claim:
1. A bit interleaved time division multiplexer for multinode systems having
a plurality of aggregate lines, comprising:
(a) a high speed bus;
(b) at least two aggregate common means connected to said bus, each
aggregate common means including,
(1) aggregate common address recognition means for recognizing when a
particular aggregate common means is being addressed,
(2) recoding means for obtaining first bits of information from a
particular aggregate line in accord with a first frame format, supplying a
first intramultiplexer system address for at least one bit of said
obtained first bits of information, and sending at least one of said
obtained first bits of information accompanied by said first
intramultiplexer system address onto said high speed bus,
(3) aggregate common decoding means for receiving second bits of
information from said high speed bus and for sending at least one of said
second bits to one of a set of buffers in said particular aggregate common
means when said aggregate common address recognition means indicates that
said particular aggregate common means is being addressed, and
(4) aggregate transmit multiplexing means for multiplexing said said bits
of information in said set of buffers of said particular aggregate common
means according to a second frame format and for sending said multiplexed
bits of information over said particular aggregate line; and
(c) system control means connected to said high speed bus, said system
control means including means for generating select signals for each of
said at least two data aggregate common means, wherein when said
particular aggregate common means is selected it sends at least a bit of
said first bits of information accompanied by said first intramultiplexer
system address on said high speed bus.
2. A multiplexer according to claim 1, wherein:
said further includes a microprocessor;
said recording means and said aggregate transmit multiplexing means are at
least partially controlled by said microprocessor; and
said system control means further includes common control means for
instructing said aggregate common means microprocessor regarding system
configurations such that said microprocessor may properly control said
recoding means and said aggregate transmit multiplexing means.
3. A multiplexer according to claim 2, wherein:
in order to provide a nodal bypass, said first intramultiplexer system
address supplied by said recoding means of one of said first and second
aggregate common means for said first bits of information is an address of
the other of said first and second aggregate common means.
4. A multiplexer according to claim 3, wherein:
said high speed bus is an asynchronous high speed bus.
5. A multiplexer according to claim 4, wherein:
said recoding means of said first and second aggregate common means are
arranged to supply said first bits of information at different rates for
sending over said high speed bus.
6. A multiplexer according to claim 5, wherein:
said aggregate transmit multiplexing means of said first and second
aggregate common means are arranged to send said second bits of
information over said first and second aggregate lines at different rates.
7. A multiplexer according to claim 1, wherein:
each said first bit of information received by said recoding means of said
aggregate common means is recoded with at least a flag bit to indicate
whether said first bit of information is control information, and said
intramultiplexer address supplied by said recoding means is sent in
parallel with said first bit of information and at least said flag bit
over said high speed bus.
8. A multiplexer according to claim 7, wherein:
when said first bit of information is a control bit, said flag bit is
arranged to indicate the transmission of control bits, and said control
bit and three additional control bits and said flag bit are sent together
with said intramultiplexer address in parallel over said high speed bus.
9. A multiplexer according to claim 1, further comprising:
(b) at least one channel common means connected to said high speed bus,
each of said channel common means including,
(1) channel common address recognition means for recognizing when a
particular channel common means is being addressed,
(2) channel common decoder means for receiving third bits of information
from said high speed bus and for sending said third bits to their proper
channels when said channel common address recognition means indicates that
said particular channel common means is being addressed, and
(3) channel common multiplexing means for multiplexing fourth bits of
information from a plurality of channels according to a third frame
format, for supplying a second intramultiplexer system address to
accompany at least one of said fourth bits of information over said high
speed bus, and for sending at least one said fourth bit of information
accompanied by said second intramultiplexer system address onto said high
speed bus, wherein
said system control means further includes means for generating select
signals for said at least one channel common means, and said channel
common means sends at least said fourth bit of information accompanied by
said second intramultiplexer system address on said high speed bus when
selected.
10. A multiplexer according to claim 9, wherein:
said aggregate common means further includes a first microprocessor;
said recording means and said aggregate transmit multiplexing means are at
least partially controlled by said first microprocessor;
said channel common multiplexing further includes a second microprocessor;
said channel common multiplexing means is at least partially controlled by
said second microprocessor; and
said system control means further includes common control means for
instructing said first and second microprocessors regarding system
configurations such that said microprocessors may properly control said
recoding means, said aggregate transmit multiplexing means, and said
channel common multiplexing means.
11. A multiplexer according to claim 10, wherein:
in order to provide a nodal bypass, said first intramultiplexer system
address supplied by said recoding means of one of said first and second
aggregate common means for said first bits of information is an address of
the other of said first and second aggregate common means.
12. A multiplexer according to claim 11, wherein:
said high speed bus is an asynchronous high speed bus.
13. A multiplexer according to claim 12, wherein:
at least one of said recoding means of said at least two aggregate common
means and said channel common multiplexer of said at least one channel
common means is arranged to supply one of said first and said fourth bits
of information at a different rate than another of said recoding means of
said at least two aggregate common means and said channel common
multiplexer of said at least one channel common means, for sending over
said high speed bus.
14. A multiplexer according to claim 13, wherein:
said aggregate transmit multiplexing means of said first and second
aggregate common means are arranged to send said second bits of
information over said first and second aggregate lines at different rates.
15. A multiplexer according to claim 9, wherein:
each said first bit of information received by said recoding means of said
aggregate common means and each said fourth bit of information received by
said channel common multiplexing means from said plurality of channels is
recoded with at least a flat bit to indicate whether said first or fourth
bit of information is control information, and said first intramultiplexer
address supplied by said recoding means and said second intramultiplexer
address supplied by said channel common multiplexing means is sent in
parallel with said first or fourth bit of information respectively and at
least said flag bit over said high speed bus.
16. A multiplexer according to claim 15, wherein:
when said first or fourth bit of information is a control bit, said flag
bit is arranged to indicate the transmission of control bits, and said
control bit and three additional control bits and said flag bit are sent
together with said first or second intramultiplexer address in parallel
over said high speed bus.
17. A bit interleaved time division multiplexer, comprising:
(a) a high speed bus;
(b) at least one aggregate common means, each aggregate common means
including,
(1) aggregate common address recognition means for recognizing when a
particular aggregate common means is being addressed,
(2) recoding means for obtaining first bits of information according to a
first frame format over an aggregate line, supplying a first
intramultiplexer system address for at least one bit of said first bits of
information, and sending said at least one said first bit of information
accompanied by said first intramultiplexer system address onto said high
speed bus,
(3) aggregate common decoding means for receiving second bits of
information from said high speed bus and for sending said second bits to
one of a set of buffers in said particular aggregate common means when
said aggregate common address recognition means indicates that said
particular aggregate common means is being addressed, and
(4) aggregate transmit multiplexing means for multiplexing said second bits
of information in said set of buffers of said particular aggregate common
means according to a second frame format and for sending said second bits
of information over said aggregate line ;
(c) at least one channel common means, each channel common means including,
(1) channel common address recognition means for recognizing when a
particular channel common means is being addressed,
(2) channel common decoder means for receiving third bits of information
from said high speed bus and for sending the received third bits to their
proper channels when said channel common address recognition means
indicates that said particular channel common means is being addressed,
and
(3) channel common multiplexing means for multiplexing fourth bits of
information from said channels according to a third frame format, for
supplying a second intramultiplexer system address to accompany at least
one bit of said fourth bits over said high speed bus, and for sending said
at least one bit of said fourth bits accompanied by said second
intramultiplexer system address onto said high speed bus; and
(d) system control means connected to said high speed bus, said system
control means including means for generating select signals for each of
said aggregate common and channel common means, wherein when said channel
common means and aggregate common means are respectively selected they
each send at least a first or fourth bit of information accompanied by
said first or second intramultiplexer system address on said high speed
bus.
18. A multiplexer according to claim 17, wherein:
said aggregate common means further includes a first microprocessor;
said recording means and said aggregate transmit multiplexing means are at
least partially controlled by said first microprocessor;
said channel common multiplexing further includes a second microprocessor;
said channel common multiplexing means is at least partially controlled by
said second microprocessor; and
said system control means further includes common control means for
instructing said first and second microprocessors regarding system
configurations such that said microprocessors may properly control said
recording means, said aggregate transmit multiplexing means, and said
channel common multiplexing means.
19. A multiplexer according to claim 18, wherein:
said high speed bus is an asynchronous high speed bus.
20. A multiplexer according to claim 19, wherein:
at least one of said recording means of said at least one aggregate common
means and said channel common multiplexer of said at least one channel
common means is arranged to supply one of said first and said fourth bits
of information at a different rate than another of said recoding means of
said at least one aggregate common means and said channel common
multiplexer of said at least one channel common means for sending over
said high speed bus.
21. A multiplexer according to claim 17, wherein:
each said first bit of information received by said recoding means of said
aggregate common means and each said fourth bit of information received by
said channel common multiplexing means from said plurality of channels is
recoded with at least a flag hit to indicate whether said first or fourth
bit of information is control information, and said first intramultiplexer
address supplied by said recoding means and said second intramultiplexer
address supplied by said channel common multiplexing means is sent in
parallel with said first or fourth bit of information respectively and at
least said flag bit over said high speed bus.
22. A multiplexer according to claim 21, wherein:
when said first or fourth bit of information is a control bit, said flag
bit is arranged to indicate the transmission of control bits, and said
control bit and three additional control bits and said flag bit are sent
together with said first or second intramultiplexer address in parallel
over said high speed bus.
23. A bit interleaved time division multiplexer, comprising:
(a) a high speed bus;
(b) at least two channel common means connected to said bus, each channel
common means including,
(1) channel common address recognition means for recognizing when a
particular channel common means is being addressed,
(2) channel common decoder means for receiving first bits of information
from said high speed bus and for sending said received bits to their
proper channels when the channel common address recognition means
indicates that said particular channel common means is being addressed,
and
(3) channel common multiplexing means for multiplexing second bits of
information from a plurality of said channels according to a first frame
format, for supplying an intramultiplexer system address to accompany at
least one of said second hits over said high speed bus, and for sending
said at least one second bit accompanied by said intramultiplexer system
address onto said high speed bus; and
(c) system control means connected to said high speed bus, said system
control means including means for generating select signals for each of
said at least two channel common means, wherein when one of said channel
common means is selected it sends at least said second bit of information
accompanied by said intramultiplexer system address on said high speed
bus.
24. A multiplexer according to claim 23, wherein:
said at least two channel common means each further include a
microprocessor;
said channel common multiplexing means of said at least two channel common
means are each at least partially controlled by said microprocessor; and
said system control means further includes common control means for
instructing each of said channel common means microprocessors regarding
system configurations such that said microprocessor may properly control
said channel common multiplexing means.
25. A multiplexer according to claim 24, wherein:
said high speed bus is an asynchronous high speed bus.
26. A multiplexer according to claim 25, wherein:
said channel common multiplexing means of said first and second channel
common means are arranged to supply said first bits of information at
different rates for sending over said high speed bus.
27. A multiplexer according to claim 23, wherein:
said channel common multiplexing means of each of said at least two channel
common means further includes recoders for attaching additional third bits
of information to each second bit of information received from said
plurality of channels and multiplexed by said channel common multiplexing
means, said additional third bits of information including at least a flag
bit to indicate whether said second bit of information received from said
plurality of channels is control information, and wherein said
intramultiplexer address supplied by said channel common multiplexing
means is sent in parallel with said second bit of information received
from said plurality of channels and at least said flag bit over said high
speed bus.
28. A multiplexer according to claim 27, wherein:
when said second bit of information received from said plurality of
channels is a control bit, said flag bit is arranged to indicate the
transmission of control bits, and said control bit and three additional
control bits received from said channels and said flag bit are sent
together with said intramultiplexer address in parallel over said high
speed bus. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
This invention relates to time division multiplexers, and more particularly
to architectures for a high speed bit interleaved time division
multiplexer for multinode communication systems.
Apparatus for time division multiplexing have been known in the arts for
some time. Typically, multiplexers are comprised of interfaces to a
plurality of channels and to an aggregate, buffers for incoming and
outgoing information, and a frame which includes a memory means and a
recirculating counter which addresses the memory means. The frame is used
to select information from a plurality of channels for sending over an
aggregate line according to a framing algorithm. The frame typically
frames both data from the plurality of channels, control information from
the channels, and multiplexer overhead information such as
intermultiplexer communication and synchronization bits. Demultiplexers,
which decode the information being received over the aggregate, typically
include a frame which is programmed in a manner similar to the frame of
the multiplexer such that the received bits of information can be properly
sent to the channels for which they were meant. Such a
multiplexer-demultiplexer system is presently known as a "point to point"
system.
More recently, multinode networks have become known in the art. Each node
of such a network is given the capability of communicating over a
plurality of aggregates. In such a manner, if any aggregate line
connecting two nodes is down, the information may be sent via other nodes
to the desired locations. The standard multinode networks of the art,
while providing improved service over the point to point systems, require
sophisticated arbitration systems with buffers and other circuitry to
arbitrate the simultaneous requests of various channels to the single
transmit bus or single receive bus. Thus, if a single channel is provided
access to a plurality of multiplexers via a single bus, the channel must
request access to the bus from the arbitrator in proportion to its channel
speed and then receive an enable from the arbitrator prior to sending any
information. If separate transmit and receive busses are used for the
node, means must be provided to connect the busses together when it is
desired to bypass an aggregate. Indeed, in the standard multinode networks
of the art, physical bypasses must be installed on a node when a line is
disconnected and information is sent to one node via the bypassed node.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a high speed bit
interleaved multiplexer for a multinode system which obviates the need for
arbitration systems.
It is a further object of the invention to provide a nonarbitrated
multiplexer for multinode systems which requires no additional circuitry
or hardware to perform a bypass function.
In accord with the objects of the invention, a high speed bit interleaved
multiplexer for a multinode system is provided and generally comprises:
(a) a high speed bus;
(b) at least two aggregate common means, each aggregate common means
including,
(1) aggregate common address recognition means for recognizing when the
particular aggregate common means is being addressed,
(2) recoding means for obtaining information according to a first frame
over an aggregate, supplying an intramultiplexer system address for at
least one bit of said obtained information, and sending said at least one
bit of information accompanied by said intramultiplexer system address
onto said high speed bus,
(3) aggregate common decoding means for receiving bits of information from
said high speed bus and for sending the received bits to a set of buffers
in said particular aggregate common means when the aggregate common
address recognition means indicates that said particular aggregate common
means is being addressed, and
(4) aggregate transmit multiplexing means for multiplexing said information
in said set of buffers of said particular aggregate common means according
to a second frame and for sending said information over an aggregate;
(c) at least one channel common means, each channel common means including,
(1) channel common address recognition means for recognizing when the
particular channel common means is being addressed,
(2) channel common decoder means for receiving bits of information from
said high speed bus and for sending the received bits to their proper
channels when the channel common address recognition means indicates that
said particular channel common means is being addressed, and
(3) channel common multiplexing means for multiplexing information from a
plurality of channels into a bit stream according to a third frame, for
supplying an intramultiplexer system address for at least one bit of said
bit stream, and for sending at least one bit of information of said bit
stream accompanied by said intramultiplexer system address over said high
speed bus, and
(d) system control means connected to said high speed bus, said system
control means including means for generating select signals for each of
said aggregate common and channel common means, wherein when said channel
common means and aggregate common means are respectively selected they
each send at least a bit of information accompanied by an intramultiplexer
system address on said high speed bus.
For purposes herein, the term "select" should be taken to mean a time
period during which information can be put on the bus.
The multiplexer of the invention has a three-tiered design. In sending bits
of information from a channel over an aggregate, it will be seen that in
the first tier, the information bits from channels are multiplexed by the
channel common means according to the frame of the channel common means.
The channel common means provides an intramultiplexer system address for
each multiplexed bit of information. In the second tier, the system
control means sequentially polls the channel common means which places the
information bits and intramultiplexer system address on a high speed bus,
thereby multiplexing the already multiplexed information. The destination
of each multiplexed bit is the intramultiplexer system address provided by
the channel common means and may be any of the channel common means or any
of a plurality of aggregate common means. In the third tier, bits of
information which have been received over the high speed bus by the
aggregate common means and stored in its channel buffers is multiplexed
for sending over an aggregate according to the frame of the aggregate
common means.
It will be appreciated that each contributor to the high speed data bus
preferably has its own microprocessor and memory means for building a
frame and for controlling the various functions of the contributor
including a recognition of when it is being addressed. Likewise, the
system control means preferably includes a microprocessor and memory means
for communicating with the contributors as well as for controlling and
storing nodal configurations such as data routing and channel selection.
Thus, the system control can easily conduct a nodal bypass if an aggregate
line is down by informing the contributors to the affected aggregate
common and having the contributors reroute their information. The system
control would also inform the system control of a remote multiplexer to
the necessity of performing a nodal bypass. The remote multiplexer could
then send all information received over a first aggregate contributor out
over a second aggregate contributor.
Further objects and advantages of the invention will be more easily
understood upon reference to the detailed description of the invention
taken in conjunction with the figures.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified block diagram of the design of the multiplexer
invention;
FIG. 2 is a simplified block diagram illustrating the bus of the
multiplexer invention and its relationship to the other blocks of the
invention;
FIG. 3 is a block diagram illustrating the flow of information through the
channel common means of the invention;
FIG. 4 is a block diagram illustrating the flow of information through the
aggregate common means of the invention;
FIG. 5 is a block diagram of the system control of the invention;
FIG. 6 is a block diagram of the channel common means of the invention; and
FIGS. 7a, 7b, and 7c are block diagrams of the CPU section, the receive
logic section, and the transmit logic section, respectively of the
aggregate common means of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
A basic understanding of architecture of the multiplexer 10 of the
invention may be had by reference to FIG. 1. The multiplexer 10 of the
invention is seen to be comprised of a single high speed bus 15, a
plurality of contibutors 20 and 25 to the bus, and a system control 30.
The contributors which multiplex bits of information from a plurality of
channels 32 located on channel shelves 34 before contributing to the high
speed bus 15 are conveniently called "channel common means", and are
denoted as 20. The contributors which receive bits of information from an
aggregate before contributing to the high speed bus, are called "aggregate
common means" and are denoted as 25. The aggregate common means receive
bits of information from the channel common means or other aggregate
common means for sending out over the aggregate links 38.
The basic working of the multiplexer 10 is seen in FIG. 2. The system
control 30 includes a high speed clock 40 and a ring counter 42 which are
used to serially address the contributors 20 and 25 to the system. Upon
being addressed, a specific contributor 20 or 25 is permitted (in the
preferred embodiment) to place five bits of information ("data word" or
"control word") onto the high speed bus 15 along with eleven system
address bits. Of the five bits of information, a first "flag" bit is used
to indicate whether the information to be transferred is data or control
information. If the flag bit is indicative of a data word, the second bit
is the data bit which is being sent. The third bit is then used to
indicate a null transaction with the fourth bit being used in the
aggregate common means only to indicate the presence or lack of
synchronization with a remote multiplexer. The fifth bit is presently left
undefined. If the flag bit is indicative of a control bit, the second
through fifth bits are used as controls bits. Of course, the use of five
information bits having particular meanings is only indicative of the
preferred embodiment of the invention. Those skilled in the art could
provide different schemes which utilize different numbers of information
bits and/or different meanings to the bits while still practicing the
invention.
Of the eleven address bits (intramultiplexer system address) sent with the
five information bits, four address bits are used to identify a
contributor 20 or 25, and seven bits are used to identify the channel in
the contributor. Thus, in the preferred multiplexer of the invention, up
to sixteen contributors may be accommodated on the system with up to one
hundred twenty-eight channels addressable in each contributor. Again, if
desired, the number of address bits may be changed by those skilled in the
art to accommodate additional contributors and/or channels per
contributor. Regardless, the information bits are sent into the common bus
15 along with the address bits and the information is received by the
addressed contributor, as each contributor has resident intelligence and
can recognize its address and accept information via a latch.
As indicated by FIGS. 1 and 2, the multiplexer 10 of the invention has a
three-tiered design. In sending information from a channel 32 over an
aggregate 38, it will be seen that in the first tier, information bits
from channels are multiplexed by the channel common means 20 according to
the frame of the channel common means as will be more fully described
herinafter. The channel common means 20 also provides an intramultiplexer
system address for each multiplexed bit of information. In the second
tier, the system control means 30 sequentially polls the channel common
means and in response thereto, each channel common means places the
information and the intramultiplexer system address on the high speed bus
15. In this manner, already multiplexed information from a plurality of
contributors 20 and 25 is again multiplexed although the destinations of
the information placed on bus 15 may be different. Thus, when sending
information from a channel 32 to an aggregate 38, the destination of the
information which is on bus 15 is the system address provided by the
channel common means 20 and may be any of a plurality of aggregate common
means 25. In the third tier, information which has been received over the
high speed bus 15 by the aggregate common means 25 and stored in the
aggregate common means channel buffers is multiplexed for sending over an
aggregate 38 according to the frame of the aggregate common means.
Turning to FIGS. 3 and 4, it is seen that the multiplexer 10 accommodates
full duplex communication, and also permits channel to channel and
aggregate to aggregate internal communication. Thus, in FIG. 3, a
simplified channel common means 20 is provided to show the flow of
information through the means 20. The channel common means 20 includes a
microprocessor 50, a RAM control 54, a channel RAM 58, and an address
converter 62, and a transmit/receive section including latches 64 and 66,
a decoder 67, and decode driver 68. The microprocessor 50 is responsible
for frame calculation and channel control, and it communicates with the
system controller 30 via microprocessor bus 69, and to individual channels
via a response bus 74. The frame for multiplexing up to one hundred
twenty-eight channels of information is loaded by RAM control 54 into the
channel RAM 58 where it is stored. The frame is preferably built by the
microprocessor according to the teachings of U.S. Pat. Nos. 4,122,309 and
4,460,993, which are assigned to the assignee herein. When a signal from
RAM control 54 increments an address in channel RAM 58, RAM 58 indicates
whether the next select is of data or control information. If the select
is for data from a channel, a transmit select 70a issues from the channel
common means to the channel identified by the RAM 58. In response, the
channel transmits data at 70b, and the data is stored in parallel with
four other bits (i.e. a flag bit, null bit, a preset sync bit (sync=1),
and extra bit) sequentially in a FIFO buffer-latch 64. Along with the data
sent over the transmit data line 70b, an eleven bit intramultiplexer
system address is generated by address converter 62 under the direction of
RAM control 54. The eleven bit system address is stored in parallel with
the five information bits in latch 64. If, on the other hand, the select
indicated by RAM 58 is for control information, the channel RAM 58
addresses a control select generator 71 and control information therein
issues therefrom. The control information i obtained by control select
generator 71 via line 72b according to selects generated over line 72a and
in accord with the teachings of commonly owned U.S. Pat. No. 4,437,182.
Thus, when RAM 58 selects a channel control, four bits of control
information are sent by control select generator 71 to the address
converter, where an eleven bit intramultiplexer system address is
generated. As with the information bits, the control bits and system
address accompanying the control bits are stored in latch 64.
When the channel common means 20 is selected by the system control 30, one
set of information bits and system address bits contained in the buffer of
latch 64 is placed onto the high speed bus 15. While all contributors to
the bus have access to the information and the system address, only that
contributor having the address of the first four address bits accepts the
five information and remaining seven address bits. Thus, in the receive
section of the channel common means 20, the latch 66 stores the sixteen
bits on the bus, and the four contributor address bits are compared in the
decoder 67 with the contributor address. If a match is made, and the five
information bits do not indicate a null data word, the decode driver 68 is
loaded with the seven bit channel address and the five information bits.
The decode driver 68 then sends the five information bits, or some
stripped version thereof to the indicated channel. Those skilled in the
art will recognize that the arrangement of the multiplexer where all
contributors have access to a single high speed bus permits the
performance of a loop-back by allowing a contributor to address itself.
In FIG. 4, the data flow through an aggregate common means is shown with a
simplified block diagram of the aggregate common means 25. It will readily
be appreciated that many aspects of the aggregate common means 25 are
similar, if not identical, to the channel common means 25. Thus, the
aggregate common means includes a microprocessing section, a transmit
section, and a receive section. The microprocessing section has a
microprocessor 75 which performs frame calculation, and which uses RAM
control 76 to load the frames into a receive frame RAM 78, and a transmit
frame RAM 80. The microprocessor 75 also loads the address converter 81
with routing information which it has received from the system control 30
via the microprocessor bus 69.
The transmit section of the aggregate common means has a transmit frame 80,
a latch 82, a decoder 83, channel and control buffers 84 and 85 and a sync
generator 86, and in some manners functions similarly to the receive
section of the channel common means 20. Thus, the latch 82 stores the
sixteen bits (five information bits, and eleven system address bits) on
the bus, and the four contributor address bits are compared in the decoder
83 with the contributor address. If a match is made, and the flag bit
indicates the transmission of a data bit, and a null data word is not
indicated, a buffer 84 corresponding to the seven bit channel address is
loaded with the data bit which is to be transmitted over the aggregate. If
the flag bit indicates the transmission of control bits, the control
buffer 85 of the addressed channel is loaded with the control bits. The
bits of information in buffers 84 and 85 are then sent over the aggregate
via the synchronization generator 86 and aggregate interface 88 according
to the transmit frame in RAM 80.
The receive section of the aggregate common means 25 has a receive frame
RAM 78, an address converter 81, a sync detector 90, a receive control
section 94, and a latch 92 and in some manners functions in a similar
manner to the transmit section of the channel common means 20. The
aggregate common means receive section receives information via the
aggregate interface 88 and locates the frame bits of the received
aggregate bit stream in the sync detector 90. Using the frame bits as a
reference, the receive frame RAM 78 disassembles the bit stream into
channel data, channel controls and multiplexer overhead. The channel data
bits are processed such that the data is stored in parallel with four
other bits (i.e. a flag bit, null bit, sync bit, and extra bit) and the
five information bits are tagged with an eleven bit system destination
address by the address converter 81 under the direction of RAM control 76
and the microprocessor 75. The eleven bit intramultiplexer system address
is stored in parallel with the five information bits in latch 92. If the
information received by the aggregate common receive section is control
information, the information is processed by the receive control section
94 which sends a five bit control word (a flag bit and four bits of
control information) with a seven bit address to the address converter 81,
where an eleven bit system address is generated. As with the information
bits, the control bits and system address accompanying the control bits
are stored in latch 92.
With the agggregate common means 25 so arranged, those skilled in the art
will appreciate that a nodal bypass is easily accomplished without the use
of additional hardware. To accomplish the same, information which is
destined for a remote multiplexer but which is routed through an aggregate
common means 25 of the instant multiplexer 10 will have an
intramultiplexer system address of another aggregate common means of
multiplexer 10 tagged to it. The address converter 81 of the receiving
aggregate common means will be informed by the system controller 30 via
the aggregate common means microprocessor 75 of the aggregate (and
channel) to which the information is to be sent.
Having described the design of the multiplexer of the invention and the
data flow therethrough in basic terms, the details of the preferred
embodiment of the components of multiplexer 10 are seen in FIGS. 5, 6, and
7a-7c.
As previously indicated, the system control means 30 of the invention
provides clock generation and ring counter circuitry used to generate
selects of the information contributing means 20 and 25. The system
control means 30 also provides intramultiplexer system coordination, and
performs, controls and stores all nodal configuration information such as
information routing and channel selection and all diagnostic management.
The system control means is driven by a microprocessor and uses a
microprocessor bus to communicate with each contributing means and to
perform and control system configuration.
Turning to FIG. 5, the circuitry for performing the various functions of
the system control means 30 is seen in block diagram format. The "brains"
of the system is located in the microprocessor 102 which is preferably a
68B09 manufactured by Motorola. The microprocessor controls most of the
functions of the system controller via internal system controller address
bus 103 and data bus 104. The memory and input-output address decoder 105
of the microprocessor indicates that various addresses of the memory of
microprocessor 102 interface with the system controller memories 110,
including a EEPROM, and EPROM, a RAM, and the interface section 120. The
EEPROM of memory 110 is used to store application routines, operating
program software, nodal configurations, information path maps through the
multiplexer, other common routines, etc., in a relatively permanent
environment. The EEPROM may be preprogrammed, or it may be programmed,
modified, or maintained by the user via a network controller such as is
disclosed in Publication No. 058R671, May 1986, published by General
DataComm, Inc., the assignee herein. The EPROM of memory 110 is used to
store the most permanent elements of the software including self test
routines, bootstrap program loads, the operating system, and common
routines and vector tables used during interrupt servicing. The RAM of
memory is used to store information of a purely temporary nature such as
stack pointers and tables, a well as for scratchpad calculations for
configuration determinations etc.
If desired, various additional elements may be provided to enhance the
functioning of the microprocessor 102. Thus, in order to help the
microprocessor 102 interface with memory 110, a direct memory access 115
may be provided. Likewise, if additional memory is desired or required, a
bank control 116 may be provided so that more memory may be accessed with
the same number of address bits. Further, dip switches 117 and switch
interfaces 118 may be provided for providing additional functions.
The microprocessor 102 itself is subject to a modicum of control by various
elements of the system controller 30. The interrupt controller 124
controls and prioritises interrupts received by the microprocessor from
other elements of the controller 30 such as e.g. interface circuitry, or
memory elements. When an interrupt is processed, the controller 124
generates a vector which is used by the software to enter the appropriate
interrupt service routine. The power on reset 126 generates reset pulses
during the power up phase to ensure that the hardware starts in an orderly
fashion, and during power disturbances to prevent writing into the EEPROM
of memory 110 when the voltage supply is low. The watchdog timer 128
guards agains the software of the microprocessor entering into a fatal
loop. The watchdog 128 is software driven in that the software
periodically sets the timer. If a period of real time transpires without
the watchdog timer 128 being reset, the timer will expire and cause the
highest priority interrupt to occur in the microprocessor 102 so that
appropriate action may be taken.
The system controller 30 interfaces with the contributing means of the
multiplexer 20 and 25 and with data communication means outside the
multiplexer via the interface section 120. Thus, in the preferred
embodiment, four serial communications data links can be connected to the
system controller. An operator controlled video display unit link 140 or a
network controller link 141 may be connected via an RS423 and/or RS232C
port 144 and a universal synchronous/asynchronous receiver transmitter
(USART) 146. In this manner, an operator can control information routing,
nodal configurations, etc. in a remote or local manner by communicating
via a higher level controller such as an IBM PC with the system control
means 30. A third serial communication link of interface section 120 is a
modem link 148. The system supports the ability to provide system
instructions by an operator over a telephone line via an auto answer
interface 150, a modem 152, and a universal asynchronous receiver
transmitter (UART) 154. Finally, a serial data link 156 links a back-up
system controller (not shown) and the system controller 30 via the UART
154. This serial port permits the backup system controller to be loaded
with the same information as the system controller 30 which is in service.
With all four serial data communication links 140, 141, 148 and 156, an
address/data multiplexer 158 is used to take the information received by
the UART 154 or USART 146 and direct it onto the proper bus (e.g. the
address or data busses 103 or 104).
Another aspect of the interface section 120 of the system controller 30 is
the interface 160 with the redundancy control means (not shown), of which
the back-up supervisor is an element, and the interface 170 with the
information contributing means 20 and 25. The redundancy control means
(not shown) provides control of redundant circuitry for all of the other
elements of the multiplexer. As a result, proper functioning of the
multiplexer is permitted even when certain elements are being serviced or
are not functioning properly. The contributing means interface 170 is an
interface with the dual port RAMs of all the contributing means | | |
