Mode optimized D.C. power supply - Patent Review 4816740

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BACKGROUND OF THE INVENTION

Direct current power supplies are generally designed for optimum performance in a constant voltage mode (CV) or in a constant current mode (CC). In either case there is a "limit" mode of operation at which the supply automatically switches from one mode to the other. Specifically when a constant voltage supply, CV, reaches a current output such that CV/CC.gtoreq.RL, wherein CV is the constant voltage setting , CC is the constant current setting and RL=the load resistance, it switches into a constant current mode and when a constant current supply reaches a current such that CV/CC.gtoreq.RL, it switches to a constant voltage mode.

A power supply optimized for CV operation should approach zero output impedance at all frequencies, and a power supply optimized for CC operation should approach an infinite output impedance at all frequencies.

A power supply optimized for CV operation generally has a large output capacitor connected between its output terminals that minimizes the output impedance for the CV mode but impairs its transient response for varying loads when operating in a CC mode.

A power supply optimized for CC operation usually does not have an output capacitor connected between its output terminals, but the lack thereof causes a poorer load effect transient response when operating in CV mode.

BRIEF SUMMARY OF THE INVENTION

In accordance with a first aspect of this invention, an output capacitor is connected between the output terminals of a power supply when it is operating in a CV mode and is disconnected therefrom when the power supply is operating in a CC mode.

In accordance with a second aspect of this invention, means are provided for charging and discharging the output capacitor to the voltage between the output terminals when it is disconnected therefrom during CC operation, thereby preventing output transients from being produced when CV operation is resumed.

In accordance with a third aspect of the invention, a P channel FET (or PNP bipolar Transistor) having its source and drain electrodes (emitter and collector electrode) respectively closer to input and output terminals of the supply is used as a series pass resistance having the high output impedance desired for CC operation.

In accordance with a fourth aspect of this invention, an N channel FET (or NPN Bipolar Transistor) having its drain and source electrodes (collector and emitter) respectively closer to the input and output terminals of the supply is used as a series pass resistance having a low output impedance desired for CV operation.

In a preferred embodiment of the invention P channel and N channel FET's are connected in series and controlled in such manner that the P channel FET is saturated when the output voltage is being controlled by the N channel FET during CV operation and the N channel FET is saturated when the output current is being controlled by the P channel FET during CC operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a preferred embodiment of the invention,

FIG. 1A is a schematic diagram of a level shifter for use in FIG. 1,

FIG. 2 is a schematic diagram of a portion of FIG. 1 that is altered so as to place the current sensing resistor between the FET's and the source of unregulated voltage, and

FIG. 3 is a schematic diagram of a portion of FIG. 1 that is altered so as to use only one FET for CV and CC operation.

DETAILED DESCRIPTION OF THE INVENTION

Reference is made to the schematic diagram of FIG. 1 illustrating one form of a preferred embodiment of the invention wherein an unregulated source 2 of D.C. voltage is connected between input terminals IT.sub.1 and IT.sub.2. Two series pass FET's Q.sub.1 and Q.sub.2 are connected in series with a resistor R.sub.1 between the input terminal IT.sub.1 and an output terminal OT.sub.1. The input terminal IT.sub.2 is directly connected to an output terminal OT.sub.2 and a load RL is connected between the output terminals OT.sub.1 and OT.sub.2. Q.sub.1 is a P channel FET having its source electrode S, connected to IT.sub.1, and its drain electrode D.sub.1 connected to R.sub.1. Q.sub.2 is an N channel FET having its drain electrode D.sub.2 connected to R.sub.1 and its source electrode connected to the output terminal OT.sub.1.

CC operation is controlled by an operational error amplifier A.sub.1 having its non-inverting input connected to D.sub.1, its inverting input connected to D.sub.2 via a variable D.C. voltage source Vc and its output electrode coupled via a level shifter LS to the gate electrode G.sub.1 of Q.sub.1. As the load RL changes so as to vary the current through R.sub.1, A.sub.1 varies the resistance of Q.sub.1 in such manner as to keep the current very close to the value determined by the voltage supplied by Vc. During CC operation Q.sub.2 is saturated so as to have little series resistance.

The connection of the drain electrode D.sub.1 to OT.sub.1 aids in providing a high output impedance for the power supply, but a significantly higher output impedance can be attained if an output capacitor C that is connected between OT.sub.1 and OT.sub.2 during CV operation is removed from the output circuit by placing a switch SW that is in series with C in the position shown. The switch SW may be controlled in any suitable manner as by connecting a relay winding W.sub.1 in series with a low pass filter 8 and an inverting amplifier 10 between the output electrode of A.sub.1 and a point of positive voltage and coupling W.sub.1 to a winding W.sub.2 that moves SW to the position shown when current flows in W.sub.1. Whereas SW is shown as an electromagnetic switch it could be a solid state switch.

CV operation is controlled by an operational error amplifier A.sub.2 having its non-inverting input connected to the junction of resistors 4 and 6 that are connected in series with a variable D.C. voltage source between OT.sub.1 an OT.sub.2. The inverting input of A.sub.2 is connected to OT.sub.1, and its output electrode is connected to the gate G.sub.2 of Q.sub.2. As the load R.sub.L changes so as to vary the output current, A.sub.2 varies the resistance of Q.sub.2 in such manner as to keep the output voltage very close to the value determined by the value of resistor 6 divided by the value of the resistor 4 times V.sub.v. During CV operation Q.sub.1 is saturated so as to have little resistance.

During CV operation the connection of the source electrode S.sub.2 of Q.sub.2 to OT.sub.1 aids in providing a low output impedance for the supply. Further decrease in impedance as well as good transient response is attained by the fact that no current flows in W.sub.1 so as to permit SW to connect the output capacitor C between OT.sub.1 and OT.sub.2.

Whereas the removal of the output capacitor C from the output circuit during CC operation increases the output impedance of the power supply as desired, an arc may be drawn by the switch SW and/or an output transient could be produced when CV operation is resumed and SW returns to the position that connects C between OT.sub.1 and OT.sub.2. This is prevented in accordance with another aspect of the invention by provision of means for charging or discharging C during CC operation so that the voltage across it follows the output voltage between OT.sub.1 and OT.sub.2.

Control of the charge and discharge of the output capacitor C is effected by an operational amplifier A.sub.3 having its noninverting input connected to OT.sub.1 and its inverting input connected via a resistor R.sub.2 to the drain electrodes D.sub.3 and D.sub.4 of FET's Q.sub.3 and Q.sub.4 that are connected in series with a D.C. saturation compensation voltage source V.sub.B between S.sub.4 and IT.sub.2. The output electrode of A.sub.3 is connected via a resistor 12 to the gate electrodes G.sub.3 and G.sub.4 of Q.sub.3 and Q.sub.4 respectively. The saturation compensation voltage source V.sub.B permits Q.sub.4 to operate down to zero volts. A guard connection is made to the inverting input of A.sub.3.

As the voltage at OT.sub.1 increases, the output of A.sub.3 becomes more positive and current flows through Q.sub.3, the resistor R.sub.2 and the switch SW so as to increase the voltage on the output capacitor C. If the voltage at OT.sub.1 decreases, so as to be less than the voltage across C, the output of A.sub.3 becomes negative so as to turn on Q.sub.4 and permit current to flow from C via the switch SW to IT.sub.2 via V.sub.B.

When the power supply is operating in the CC mode, step changes in output voltage can occur that are not large enough to cause the power supply to change to CV operation and yet large enough to damage Q.sub.3 or Q.sub.4. A protection circuit is therefore provided that is comprised of operational amplifiers A.sub.4 and A.sub.5 having their non-inverting inputs respectively connected via reference voltages B.sub.4 and B.sub.5 to the side of the resistor R.sub.2 that is connected to the switch SW. Their inverting inputs are connected to the opposite side of R.sub.2. The output of A.sub.4 is connected via a diode d.sub.4 to the gates G.sub.3 and G.sub.4, and the output of A.sub.5 is connected via a diode d.sub.5 to the gates G.sub.3 and G.sub.4. The diodes d.sub.4 and d.sub.5 are oppositely poled. When sufficient current is flowing toward the output capacitor C through Q.sub.3 to make the inverting inputs of the amplifier A.sub.4 have a greater voltage than is applied to its non inverting input by the source B.sub.4, the output of A.sub.4 becomes negative so that control current from A.sub.3 flows through the resistor 12, d.sub.4 and A.sub.4 to the common for the operational amplifier A.sub.3, A.sub.4 and A.sub.5, not shown, that would be connected to guard. The circuit for A.sub.5 operates in a similar manner (so as to protect Q.sub.4) when the voltage across the load steps in the other direction.

Reference is now made to FIG. 1A for a description of a circuit that can be used as the level shifter LS. Components corresponding to those of FIG. 1 are designated in the same manner and need not be further described. The output of A.sub.1 is coupled via a resistor 14 to a gate G.sub.5 of an N channel FETQ.sub.5 having its source electrode S.sub.5 connected to the drain electrode D.sub.1 of Q.sub.1 and its drain electrode D.sub.5 connected to the gate G.sub.1 and Q.sub.1 and to the source electrode S.sub.1 of G.sub.1 and IT.sub.1 via a resistor 16. As the control voltage for CC operation provided by A.sub.1 increases, the resulting current drawn through the resistor 16 makes the gate G.sub.1 more negative than it otherwise would be thereby increasing the impedance of Q.sub.1 as required.

Reference is now made to FIG. 2 illustrating a circuit that does not require a level shifter. Components corresponding in function to FIG. 1 are designated in the same manner primed. The principle difference is that the current sensing resistor R.sub.1 ' is connected between the source electrode S.sub.1 of Q.sub.1 and the input terminal IT.sub.1.

Although not shown the resistor R.sub.1 can be inserted between the source electrode S.sub.2 of Q.sub.2 and the output terminal OT.sub.1 in which case a level shifter would be required.

FIG. 3 illustrates a portion of the circuit of FIG. 1 that would be involved if only one FET Q.sub.6 is used for control in both the CC and CV modes of operation. Components corresponding in function to those of FIG. 1 are designated in the same manner with a double prime. Q.sub.6 can be an N channel FET as shown if CV operation is favored or a P channel FET if CC operation is favored. In the latter case, a level shifter would be required and drain and source connections would have to be interchanged. In either case the removal of the output capacitor from the output circuit during the CC mode of operation and the desired maintainance of the voltage across it at the voltage between the output terminals would be performed in the same way as in FIG. 1. The x near the inverting input of A.sub.2 " is the point x in FIG. 1. Diodes d.sub.7 and d.sub.8 are respectively connected between the outputs of A.sub.1 " and A.sub.2 " and the gate G.sub.6 with the polarity shown so as to decouple A.sub.1 " from A.sub.2 ". A resistor 14 is connected between G.sub.6 and S.sub.6 so as to prevent charge build-up from inadvertently saturating Q.sub.6.

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