Signal scrambling transmission system

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BACKGROUND OF THE INVENTION

This invention relates generally to transmission of digital data, and more particularly concerns the transmission of digital data in scrambled fashion to facilitate clock recovery, recovery of the carrier through statistical techniques, and equalization of the number of "0"s and "1"s, thus eliminating the need for frequency response down to DC.

A common form of scrambler/descrambler data transmission system is based on a pseudo random sequence generator called a maximal length shift register. The maximal length shift register includes a shift register with exclusive OR feedback. The inputs to the exclusive OR gate feedback are connected to separate taps on the shift register. The maximal length shift register will clock through a pseudo random sequence, available at the output of the OR gate (input to shift register). The pseudo random sequence will repeat every 2.sup.N -1 clock cycles, where N is the number of stages in the shift register. The particular taps used for the inputs to the exclusive OR feedback gate must be carefully chosen to insure that the sequence is random and is of maximal length.

The maximal length shift register can be used to scramble data transmissions in two basic ways. The first, and most common, system is the self-synchronizing system in which a second OR gate is interposed in the feedback loop just before the input to the shift register. The second OR gate exclusively ORs the data with the feedback signal and produces the transmitter output at the input to the shift register. If the user data is held at a binary zero. the pseudo random generator performs exactly as if no data was present and that pseudo random sequence is connected to the transmission line. If, on the other hand, the user data is held at a binary one, a different pseudo random sequence is generated at the output of the OR gate (input to the shift register), and that sequence is connected to the transmission line. In general, the effect will be to randomize the data stream. Recovery of the original data is simplified by the fact that what is transmitted is the actual input to the shift register. By feeding the scrambled data received into a similar shift register with exclusive OR connections from the same shift register taps, the shift register generates the original transmit side pseudo random sequence on the receive side. This signal is then exclusively ORed with the scrambled data to restore the original data.

The second scrambling system is a synchronization system in which two free-running pseudo random sequence generators, each consisting of a maximal length shift register, are provided both at the transmit and receive end. The pseudo random sequence at the input of the shift register is then exclusively ORed with the data at the transmit end and connected to the transmission line. In addition, a synchronization signal is generated by the maximal length shift register which is also transmitted to the receive side. At the receive side, the synchronization signal is used to synchronize the freerunning maximal length shift register so that its output can then be exclusively ORed with the transmitted or scrambled data, thereby recovering the original data.

The second scrambling system has substantial advantages over the first system. Errors occurring in the transmission path of the first self synchronizing system show up immediately as the data is applied to the recovery exclusive OR gate. The transmission error propagates down the shift register past the exclusive OR taps. Consequently, one error in the transmission channel becomes N+1 separate errors in the maximal length shift register (where N equals the number of taps from the shift register). In the second system, errors in the transmission channel are only exclusively ORed with the pseudo random sequence which is unchanged, and therefore each transmission error only results in a single error in the data output.

Another difficulty in the transmission of binary data is the problem associated with demodulating binary phase shift keying data (BPSK). When BPSK data is received at a receiver and the receiver locks on to the carrier frequency and begins developing a carrier signal, there is 180.degree. uncertainty as to the absolute phase of the carrier. The result is that the demodulated data may either be inverted or not inverted. For quadrature phase shift keying (QPSK), there is a four-way ambiguity involving inversions of pairs of bits. Other modulation schemes such as M-ary PSK and M-ary QAM also produce phase ambiguities which must be resolved at the receiver. Commonly, such ambiguity is overcome by a system called differential encoding. Before transmission, binary "1"s are encoded as a change in state, and binary "0"s are encoded as no change in state. After demodulation, transitions are decoded to binary "1"s, and bits not causing a transition are decoded to binary "0"s. This process maintains correct polarity whether or not the transmission channel is inverted because it depends only on the change of state. Differential encoding, however, possesses its own problems in that it leads to a multiplication of errors, and each error propagates into two errors since each decoded bit depends on the current bit and the past bit to establish the change of state.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a signal scrambling transmission system based on logically combining a pseudo random sequence with the data prior to transmission and recovering the data with the same pseudo random sequence at the receive side by synchronizing the pseudo random sequence at the receive side with the pseudo random sequence at the transmit side of the transmission system.

It is also an object of the present invention to provide a signal scrambling transmission system in which the length of the pseudo random sequence is long enough to keep the data pattern from being periodic and producing insignificant descrete power spectral line components in the modulated RF spectrum.

It is further an object of the present invention to provide a signal scrambling transmission system in which data used for synchronizing the pseudo random sequences (overhead) is less than 2% of the transmitted data.

It is further an object of the present invention to provide a signal scrambling transmission system in which the probability of the receiver missing the first occurrence of a synchronization word in the data stream is equal in magnitude to the probability of the receiver synchronizing on the wrong, randomly occurring synchronization word in the transmitted data.

It is likewise an object of the present invention to provide a signal scrambling transmission system wherein the pseudo random sequence in the receiver will synchronize with the pseudo random sequence from the transmitter within a short, predetermined time after receipt of the scrambled data by the receiver.

It is further an object of the present invention to provide a signal scrambling transmission system which has a fast clock in the transmission link that runs slightly faster than the normal system clock. The ratio of the normal system clock and the fast clock is such that the ratio is reduced to a low integer value to simplify the clock multiplier circuitry.

It is further an object of the present invention to provide a signal scrambling transmission system wherein the scrambled data is transmitted in BPSK mode and is connected to the receiver by means of a controllable phase inverter. The phase inverter is controlled by recognition of the synchronization word or its complement in the scrambled data, thereby allowing for phase correction at the receive end of the transmission system.

It is further an object of the present invention to provide a signal scrambling transmission system wherein the receiver includes a false synchronization detector which, for each occurrence of the synchronization word, determines whether the pseudo random sequence of the receiver is still in synchronization with the transmitter's pseudo random sequence. Upon the occurrence of a predetermined number of occurrences of false synchronization, the receiver resets the pseudo random sequence to an initial position and begins looking for the next occurrence of the synchronization word in the transmitted scrambled data.

It is further an object of the present invention to provide a signal scrambling transmission system wherein the pseudo random sequence is contained in a read only memory (ROM) consisting of 32 frames. Each frame is 4,096 bits long and includes 27 bits of synchronization word, 5 bits of index word to identify the frame number, and 4,064 bits of pseudo random sequence.

The foregoing objectives of the present invention are accomplished by a signal scrambling transmission system in which the transmitter comprises an exclusive OR gate having one input connected to the data to be transmitted and having its other input connected to a pseudo random sequence generator. The pseudo random sequence generator is a ROM divided into 32 frames, each of which is 4,096 bits long, for a total of 131,072 bits. Each 4,096-bit frame is divided into a 27-bit synchronization word, a 5-bit index word for identifying the frame number, and 4,064 bits of pseudo random sequence.

The receiver for the signal scrambling transmission system includes an exclusive OR gate with one input for receiving the scrambled data and the other input connected to a pseudo random sequence generator which has the same pseudo random sequence as the pseudo random sequence generator at the transmit end. The receiver searches for the 27-bit synchronization word and 5-bit index word to identify the beginning of a frame and the particular frame in the ROM. Once the fixed synchronization word is found, the associated 5-bit index word is loaded into the upper five bits of a 17-bit address counter which addresses the first bit in the identified frame of the ROM and starts the ROM sequentially counting out its pseudo random sequence for exclusively ORing with the scrambled data.

The organization of the ROM with its 32 frames, each with a 27-bit synchronization word, a 5-bit index word, and 4,064 bits of pseudo random sequence, is selected to provide certain desirable operating characteristics for the scrambling transmission system. The 32 bits (27-bit synchronization word and 5-bit index word) represent overhead in the system, and therefore should be kept at a minimum. In the present invention, the overhead is maintained below 2%, and preferably is 0.8% which is the ratio of the overhead (32 bits of synchronization and index words) to the total frame length of 4,096 bits. The synchronization word length of 27 bits is chosen so that the chance of the detection system missing the first occurrence of the synchronization word based on an established transmission error rate is approximately equal in magnitude to the chance of the detection system locking on the random coincidental occurrence of the 27-bit synchronization word in the scrambled data.

The ROM is divided into 32 frames so that the synchronization word appears 32 times during the complete cycle through the ROM. Thus, at low data rates of 56 kilobits per second, for example, the time between synchronization words is less than 100 milliseconds, and is preferably about 73 milliseconds, which is equal to the number of bits in a frame (4,096 bits) divided by the data rate.

Because it is necessary to insert the synchronization word and index word at the beginning of each frame of data, the data has to be transmitted slightly faster than the data is processed at the transmit end. The ratio between the normal system clock and the fast clock is set at the ratio of the length of the pseudo random sequence as compared to the entire length of the frame for a ratio of 4,064 to 4,096, which reduces to 127/128. By having the ratio of pseudo random sequence to frame length reduced to a fraction having integer values of less than 200, the clock multiplier circuit which uses a phase lock loop will only have to work down to frequencies which are 128 times less than the normal clock frequency, or about 400 hertz for a low bit rate of 56 kilobits per second. The lower limit on the frequency in the phase lock loop makes the design less difficult.

Because the 27-bit synchronization word is fixed and therefore known, detection of the synchronization word for synchronizing the pseudo random sequence with the incoming scrambled data can also provide a basis for determining the existance and nature of any phase ambiguity that may have resulted during transmission. For example, the receiver of the present invention can determine whether data transmitted in BPSK mode is inverted or not inverted and can invert the phase as required if the complement of the synchronization word is detected in the scrambled data.

Other objects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing the transmitter of the signal scrambling transmission system of the present invention;

FIG. 2 is a schematic diagram of the receiver of the signal scrambling transmission system of the present invention; and

FIG. 3 is a diagram showing the organization in the ROM of the pseudo random sequence, the fixed synchronization word, and the frame index word.

DETAILED DESCRIPTION

While the invention will be described in connection with a preferred embodiment, it will be understood that we do not intend to limit the invention to that embodiment. On the contrary, we intend to cover all alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

Turning to FIG. 1, there is shown a transmitter 10 of the signal scrambling transmission system of the present invention. The transmitter 10 comprises data holding means 12, clock multiplier 14, address counter 16, a pseudo random sequence generator in the form of a ROM 18, an exclusive OR gate 20, and a multiplexer 22.

Data is fed to the transmitter 10 on data input line 26, and a normal system clock signal is provided on input 28 of the transmitter. After scrambling, the digital data is connected to a transmission line (not shown) via output line 30, and a fast clock signal is connected to the transmission line via output 32.

The system clock signal on line 28 is multiplied by clock multiplier circuit 14 to produce the fast clock signal which has a frequency of 128/127 times the frequency of the normal clock signal. The frequency of the fast clock is established at 128/127 times the slow clock to accommodate the transmission of synchronizing data to the receiver. The clock multiplier circuit 14 is essentially conventional and uses a phase lock loop and a voltage controlled oscillator 50 to produce the fast clock on line 32. Particularly, the frequency of the normal system clock signal on line 28 is divided by an integer value of 127 by divide circuit 42. The output on line 44 is connected to the phase comparator circuit 46 which has an output 48 connected to the voltage controlled oscillator 50. The output of the voltage controlled oscillator 50 is fed back via feedback line 52 to a second divide circuit 54 which divides the frequency of the feedback signal on line 52 by an integer value of 128 and produces an output on line 56. The phase comparator compares the frequency of the signal on line 56 to the frequency of the signal on line 44 and produces a control voltage on line 48 which controls the frequency of the oscillator 50 thereby assuring that the fast clock on line 32 runs at a frequency of 128/127 of the normal system clock on line 28.

The fast clock signal on line 32 is connected via input 60 to the 17-bit address counter 16 which serves to generate an address count Q0 through Q16 on output lines 62, 64, and 66. Address output line 62 is in fact five separate lines identifying address bits Q0 through Q4. Likewise, line 64 is in fact seven separate lines representing address bits Q5 through Q11, and output line 66 is in fact five separate lines representing address bits Q12 through Q16. The 17 address lines (Q0 through Q16) are collectively identified as line 68 which is in fact 17 separate lines connected to 17 address inputs of ROM 18. The address on lines 68 discretely identifies each of 131,072 bits of data contained in the ROM 18.

Turning to FIG. 3, there is shown schematically the organization of the memory of the ROM 18, which includes 32 frames 70 numbered 0 through 31. Each frame is 4,096 bits long. The 4,096 bits include a 27-bit fixed synchronization word 72, a 5-bit index word 74 for identifying the frame count, and 4,064 bits of pseudo random sequence 76. When the address count on lines 68 (FIG. 1) is at "0", the ROM 18 reads out the first bit of 78 of the first frame onto its output 38. As the address count is incremented by the fast clock on input line 60 of the address counter 16, the ROM 18 sequentially reads out each of the 131,072 bits shown in FIG. 3, proceeding left to right and top to bottom until the last bit 80 has been read out onto output line 38.

In operation, data to be processed is clocked into data holding means 12, which is a first-in, first-out (FIFO) memory by means of the normal clock signal on line 28. The data is clocked out of the FIFO memory 12 onto line 34 by means of an intermittent fast clock signal on line 36. The intermittent fast clock signal on line 36 runs at the rate of the fast clock on line 90 (and 32) until the beginning of each frame (detector output 84 is a logic "1") at which time it is disabled and no data is clocked onto line 34. The beginning of each frame is identified the seven address bits Q5 through Q11 on line 64. When bits Q5 through Q11 of the address count are all "0"s that indicates the end of one frame of pseudo random sequence and beginning of the synchronization word of the next frame. Consequently, at the beginning of each frame (Q5 through Q11 are "0"s), the detect circuit 82 produces an output on line 84 which is connected to multiplexer 22 to select input 42 so that the synchronization word and index word at the beginning of the frame are connected to output 96, through register 24, and onto output line 30 for transmission. At the same time, the detect circuit output on line 84 is connected via inverting input 88 of AND gate 86 to disable the AND gate 86 so that the fast clock signal on input 90 is not connected through the AND gate 86 to the output 36, and data is ot clocked out of the FIFO 12 by the intermittant fast clock.

The clock signal on line 32 is also connected to input 60 of the master counter 16, which begins counting the address onto combined output lines 68. As long as the count on lines 64 (Q5 through Q11) does not equal "0" (the beginning of a frame), each fast clock pulse clocks data out of FIFO memory 12 onto line 34. The data on line 34 is connected to one input of exclusive OR gate 20, and the other input 38 of exclusive OR gate 20 is the output of the ROM 18. The exclusive OR gate 20 exclusively ORs the data on line 34 and the pseudo random sequence on line 38 as both are delivered to the exclusive OR gate inputs in timed relationship. The output of exclusive OR gate 20 on line 40 is the scrambled data. Because the detector signal on line 84 is a logic "0", input 40 of the multiplexer 22 is selected, and the scrambled data is connected through the multiplexer 22 to output 96 and to register 24. The scrambled data in register 24 is clocked onto output line 30 by the fast clock on line 32. The scramble data is then modulated in any of a number of known manners for transmission.

Once the address count reaches all "0"s on lines 64 (bits Q5 through Q11), the detect circuit 82 provides an output on line 84 which disables the fast clock count on line 90 to the FIFO memory 12 via line 36. At the same time, the detector signal on line 84 selects the input 42 of multiplexer 22 instead of the input 40. Consequently, for the next 32 counts on the counter 16, the ROM 18 reads out the 27-bit synchronization word followed by the 5-bit index word. The synchronization word and the index word appear at output 96 of multiplexer 22 and are then gated onto the transmission output 30 by means of the output register 24 under the control of the fas