In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.
An improved small computer systems interface multiplexer (SCSI Mux II) provides for coupling of a computer on a local bus with shared peripheral devices on a global bus. The SCSI Mux II is accessed by a pseudo-operation code that includes two local bus identifiers as the identifier for the SCSI Mux II. Once the SCSI Mux II is identified, the computer accesses the SCSI Mux II as a local bus peripheral device and the SCSI Mux II couples the local bus to the global bus by translating the target peripheral device identification into a global identifier to complete the transfer between the computer and the designated shared peripheral device.
The technical field of the invention generally concerns digital computers and, in particular, repeaters or switches (40) for distributed arbitration digital data buses (52, 54, 56, and 58) to which devices (62, 64, 66, 68, 72 and 74) connect in parallel. The bus repeater/switch (40) includes a plurality of bus interface cards (48) that are connected to the distributed arbitration buses (52, 54, 56 and 58) for receiving signals from and transmitting signals to devices (62, 64, 66, 68, 72 and 74) connected thereto. The bus interface cards (48) connect to a control card (44) which allows signals from one of the sharing buses (52, 54 or 56) to be exchanged with the shared bus (58). The bus switch (40) also includes selector switch (84 or 88) for choosing which particular one of the sharing buses (52, 54 or 56) exchanges digital data signals with the shared bus (58). The bus switch (40) responds to signals on the distributed arbitration buses (52, 54, 56 and 58) and to phases of the protocol for those signals so that its presence between pairs of buses (52-58, 54-58 or 56-58) is imperceptible to devices (62, 64, 66, 68, 72 and 74) connected thereto.
A system and method for flexibly and efficiently allowing multiple categories of data to be managed using a circular stack containing pointers pointing to memory resources within a memory resource area. The pointers to these memory resources can be obtained sequentially only from a first part of the circular stack, but can be placed into the circular stack at different locations depending upon the characterization of the memory resources that the pointers are associated with. The system and method is used, for example, within a private branch exchange (PBX).
A method and apparatus for enabling AIX device driver (DD) created for a uniprocessor (UP) system to run unchanged on a symmetrical multiprocessor system (SMP). Device drivers are processed by a funnelling mechanism so that UP device drivers always runs on a "Master" processor in a multi-processor system. New device drivers written for the SMP system are permitted to bypass the funneling mechanism and proceed directly to execution on any available processor in the SMP system. Device registration services are provided which examine DD flags looking for a new unique flag indicating that the device driver is SMP enabled. If the flag is not present, then emulating a uniprocessor environment for execution of that device driver.
A data bus control circuit is formed on a single semiconductor integrated circuit that includes input/output terminals for external data exchange and a plurality of functional blocks including a CPU. A bi-directional bus buffer buffers data sent over a data bus between the CPU and the input/output terminals. The signal propagation direction of the bus buffer is determined according to a logic level of a read control signal supplied from the CPU.
