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Claims  |
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I claim:
1. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving a code-modulated signal,
providing a digitized signal from said code-modulated signal, generating
model delays, generating a model code sequence that is time offset by the
model delays so that the resulting model code values are closely aligned
in time with the received code sequence, and generating model carrier
phases that are closely matched to received carrier phase, for accurately
measuring the code group delay and carrier phase of the code-modulated
signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phase of the digitized signal with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signal with the model code values
and accumulating the multiplication produces over respective selected time
intervals;
means for processing the accumulated products to obtain model phase and
model delay; and
means for modifying model carrier phase to obtain fast feedback models for
code group delays.
2. The digital signal processor recited in claim 1 further comprising:
means for applying slow feedback corrections to the fast feedback models,
for code group delay, by using accumulated products at selected intervals.
3. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving at least two code-modulated
signals, providing digitized signals from said code-modulated signals,
generating model delays, generating model code sequences that are time
offset by the model delays so that the resulting model code values are
closely aligned in time with the received code sequences, and generating
model carrier phases that are closely matched to received carrier phases,
for accurately measuring the code group delay and carrier phase of each
code-modulated signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phases of the digitized signals with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signals with the model code
values and accumulating the multiplication products over respective
selected time intervals;
means for processing the accumulated products to obtain model phases and
model delays; and
means for modifying model carrier phase to obtain fast feedback models for
code group delays.
4. The digital signal processor recited in claim 3 further comprising:
means for applying slow feedback corrections to the fast feedback models,
for code group delays, by using accumulated products at selected
intervals.
5. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving at least two code-modulated
signals, providing digitized signals from said code-modulated signals,
generating model delays, generating model code sequences that are time
offset by the model delays so that the resulting model code values are
closely aligned in time with the received code sequences, and generating
model carrier phases that are closely matched to received carrier phases,
for accurately measuring the code group delay and carrier phase of each
code-modulated signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phases of the digitized signals with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signals with the model code
values and accumulating the multiplication products over respective
selected time intervals;
means for processing the accumulated products to obtain model phases and
model delays; and
means for modifying the model carrier phase of one of said code-modulated
signals to obtain a fast feedback model for the carrier phase of another
such code-modulated signal.
6. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving a code-modulated signal,
providing a digitized signal from said code-modulated signal, generating
model delays, generating a model code sequence that is time offset by the
model delays so that the resulting model code values are closely aligned
in time with the received code sequence, and generating model carrier
phases that are closely matched to received carrier phase, for accurately
measuring the code group delay and carrier phase of the code-modulated
signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phase of the digitized signal with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signal with the model code values
and accumulating the multiplication products over respective selected time
intervals;
means for processing the accumulated products to obtain model phase and
model delay; and
means for averaging measured code group delays over a selected short
averaging interval by using concurrently measured values for carrier phase
to remove the averaged effects of time variations of the code group delays
over said interval.
7. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving at least two code-modulated
signals, providing digitized signals from said code-modulated signals,
generating model delays, generating model code sequences that are time
offset by the model delays so that the resulting model code values are
closely aligned in time with the received code sequences, and generating
model carrier phases that are closely matched to received carrier phases,
for accurately measuring the code group delay and carrier phase of each
code-modulated signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phases of the digitized signals with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signals with the model code
values and accumulating the multiplication products over respective
selected time intervals;
means for processing the accumulated products to obtain model phases and
model delays; and
means for averaging measured code group delays over a selected short
averaging interval and using concurrently measured values for carrier
phase to remove the averaged effects of time variations of the code group
delays over said interval.
8. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving a code-modulated signal,
providing a digitized signal from said code-modulated signal, generating
model delays, generating a model code sequence that is time offset by the
model delays so that the resulting model code values are closely aligned
in time with the received code sequence, and generating model carrier
phase that are closely matched to received carrier phase, for accurately
measuring the code group delay and carrier phase of the code-modulated
signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phase of the digitized signal with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signal with the model code values
and accumulating the multiplication products over respective selected time
intervals;
means for processing the accumulated products to obtain model phase and
model delay; and
means for extracting measured carrier phase for a code-modulated signal by
extracting residual phase from the accumulated products and then adding
said residual phase to the model phase for the interval.
9. A digital signal processor for use in a Global Positioning system (GPS)
receiver, the receiver of the type receiving a code-modulated signal,
providing a digitized signal from said code-modulated signal, generating
model delays, generating a model code sequence that is time offset by the
model delays so that the resulting model code values are closely aligned
in time with the received code sequence, and generating model carrier
phases that are closely matched to received carrier phase, for accurately
measuring the code group delay and carrier phase of the code-modulated
signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phase of the digitized signal with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signal with the model code values
and accumulating the multiplication products over respective selected time
intervals;
means for processing the accumulated products to obtain model phase and
model delay; and
means for extracting measured code group delay for a code-modulated signal
by extracting residual delay from the accumulated products and then adding
said residual delay to the model delay for the interval.
10. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving at least two code-modulated
signals, providing digitized signals from said code-modulated signals,
generating model delays, generating model code sequences that are time
offset by the model delays so that the resulting mode code values are
closely aligned in time with the received code sequence, and generating
model carrier phases that are closely matched to received carrier phase,
for accurately measuring the code group delay and carrier phase of each
code-modulated signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phase of the digitized signals with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signals with the model code
values and accumulating the multiplication products over respective
selected time intervals;
means for processing the accumulated products to obtain model phases and
model delays;
said receiver also receiving a data signal superimposed upon said
code-modulated signals, said processor further comprising means for
testing the logic sign of the accumulated products for extracting a data
bit sign therefrom for a data-bit interval; and
means for removing the data-bit signal from one code-modulated signal based
upon the data-bit sign extracted from another code-modulated signal.
11. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving a code-modulated signal,
providing a digitized signal from said code-modulated signal, generating
model delays, generating a model code sequence that is time offset by the
model delays so that the resulting model code values are closely aligned
in time with the received code sequence, and generating model carrier
phases that are closely matched to received carrier phase, for accurately
measuring the code group delay and carrier phase of each code-modulated
signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phase of the digitized signal with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signal with the model code values
and accumulating the multiplication products over respective selected time
intervals;
means for processing the accumulated products to obtain model phase and
model delay;
said receiver also receiving a data signal having defined data-bit
intervals and being superimposed upon said code-modulated signal; and
said digital processor further comprising means for synchronizing the
product accumulation intervals with the data-bit intervals by offsetting
accumulation interval start time with a previously measured code group
delay.
12. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving a code-modulated signal,
providing a digitized signal from said code-modulated signal, generating
model delays, generating a model code sequence that is time offset by the
model delays so that the resulting model code values are closely aligned
in time with the received code sequence, and generating model carrier
phase that are closely matched to received carrier phase for accurately
measuring the code group delay and carrier phase of each code-modulated
signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phase of the digitized signal with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signal with the model code values
and accumulating the multiplication products over respective selected time
intervals;
means for processing the accumulated products to obtain model phase and
model delay; and
means for estimating model carrier phase over a future time interval by
two-point linear extrapolation of measured phase from prior time
intervals.
13. A digital signal processor for use in a Global Positioning System (GPS)
receiver, the receiver of the type receiving at least two code-modulated
signals, providing digitized signals from said code-modulated signals,
generating model delays, generating model code sequences that are time
offset by t he model delays so that the resulting mode code values are
closely aligned in time with the received code sequences, and generating
model carrier phases that are closely matched to received carrier phases,
for accurately measuring the code group delay and carrier phase of each
code-modulated signal; the processor comprising:
means for generating counter-rotation sinusoids from model phases;
means for counter-rotating the carrier phases of the digitized signals with
said counter-rotation sinusoids;
means for multiplying the counter-rotated signals with the model code
values and accumulating the multiplication products over respective
selected time intervals;
means for processing the accumulated products to obtain model phases and
model delays; and
means for averaging measured carrier phase values of one code-modulated
signal over a selected short averaging interval by using concurrently
measured values of carrier phase of another code-modulated signal to
remove the averaged effects of time variation in said one carrier phase
over said interval.
14. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving a code-modulated
signal, providing a digitized signal from said code-modulated signal,
generating model delays, generating a model code sequence that is time
offset by the model delays so that the resulting model code values are
closely aligned n time with the received code sequence, and generating
model carrier phases that are closely matched to received carrier phase,
for accurately measuring the code group delay and carrier phase of the
code-modulated signal; the method comprising the steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phase of the digitized signals with said
counter-rotation sinusoids;
multiplying the counter-rotated signals with the model code values and
accumulating the multiplication products over respective selected time
intervals;
processing the accumulated products to obtain model phase and model delay;
and
modifying model carrier phase to obtain fast feedback models for code
groups delays.
15. The method of digitally processing signals recited in claim 14 further
comprising the step of applying slow feedback corrections to the fast
feedback models, for code group delay, by using accumulated products at
selected intervals.
16. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving at least two
code-modulated signals, providing digitized signals from said
code-modulated signals, generating model delays, generating model code
sequences that are time offset by the model delays so that the resulting
model code values are closely aligned in time with the received code
sequences, and generating model carrier phases that are closely matched to
received carrier phases, for accurately measuring the code group delay and
carrier phase of each code-modulated signal; the method comprising the
steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phases of the digitized signals with said
counter rotation sinusoids;
multiplying the counter rotated signals with the model code values and
accumulating the multiplication products over respective time intervals;
processing the accumulated products to obtain model phases and model
delays; and
modifying model carrier phase to obtain fast feedback models for code group
delays.
17. The method of digitally processing signals recited in claim 16 further
comprising the step of applying slow feedback corrections to the fast
feedback models, for code group delay, by using accumulated products at
selected intervals.
18. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving at least two
code-modulated signals, providing digitized signals from said
code-modulated signals, generating model delays, generating model code
sequences that are time offset by the model delays so that the resulting
mode code values are closely aligned in time with the received code
sequences, and generating model carrier phases that are closely matched to
received carrier phases, for accurately measuring the code group delay and
carrier phase of each code-modulated signal; the method comprising the
steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phases of the digitized signals with said
counter-rotation sinusoids;
multiplying the counter-rotated signals with the model code values and
accumulating the multiplication products over respective time intervals;
processing the accumulated products to obtain model phases and model
delays; and
modifying the model carrier phase of one of said code-modulated signals to
obtain a fast feedback model for the carrier phase of another such
code-modulated signal.
19. A method of digitally processing signals in a Global Positioning system
(GPS) receiver, the receiver of the type receiving a code-modulated
signal, providing a digitized signal from said code-modulated signal,
generating model delays, generating a model code sequence that is time
offset by the model delays so that the resulting model code values are
closely aligned in time with the received code sequence, and generating
model carrier phases that are closely matched to received carrier phase,
for accurately measuring the code group delay and carrier phase of the
code-modulated signal; the method comprising the steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phase of the digitized signals with said
counter-rotation sinusoids;
multiplying the counter-rotated signals with the model code values and
accumulating the multiplication products over respective selected time
intervals;
processing the accumulated products to obtain model phase and model delay;
and
averaging measured code group delays over a selected short averaging
interval by using concurrently measured values for carrier phase to remove
the averaged effects of time variations of the code group delays over said
interval.
20. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving at least two
code-modulated signals, providing digitized signals from said
code-modulated signals, generated model delays, generating model code
sequences that are time offset by the model delays so that the resulting
model code values are closely aligned in time with the received code
sequences, and generating model carrier phases that are closely matched to
received carrier phases, for accurately measuring the code group delay and
carrier phase of each code-modulated signal; the method comprising the
steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phases of the digitized signals with said
counter rotation sinusoids;
multiplying the counter rotated signals with the model code values and
accumulating the multiplication products over respective time intervals;
processing the accumulated products to obtain model phases and model
delays; and
averaging measured code group delays over a selected short averaging
interval and using concurrently measured values for carrier phase to
remove the averaged effects of time variations of the code group delays
over said interval.
21. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving a code-modulated
signal, providing a digitized signal from said code-modulated signal,
generating model delays, generating a model code sequence that is time
offset by the model delays so that the resulting model code values are
closely aligned in time with the received code sequence, and generating
model carrier phases that are closely matched to received carrier phase,
for accurately measuring the code group delay and carrier phase of the
code-modulated signal; the method comprising the steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phase of the digitized signals with said
counter-rotation sinusoids;
multiplying the counter-rotated signals with the model code values and
accumulating the multiplication products over respective selected time
intervals;
processing the accumulated products to obtain model phase and model delay;
and
extracting measured carrier phase for a code-modulated signal by extracting
residual phase from the accumulated products and then adding said residual
phase to the model phase for the interval.
22. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving a code-modulated
signal, providing a digitized signal from said code-modulated signal,
generating model delays, generating a model code sequence that is time
offset by the model delays so that the resulting model code values are
closely aligned in time with the received code sequence, and generating
model carrier phases that are closely matched to received carrier phase,
for accurately measuring the code group delay and carrier phase of the
code-modulated signal; the method comprising the steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phase of the digitized signals with said
counter-rotation sinusoids;
multiplying the counter-rotated signals with the model code values and
accumulating the multiplication products over respective selected time
intervals;
processing the accumulated products to obtain model phase and model delay;
and
extracting measured code group delay for a code-modulated signal by
extracting residual delay from the accumulated products and then adding
said residual delay to the model delay for the interval.
23. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving at least two
code-modulated signals, providing digitized signals from said
code-modulated signals, generating model delays, generating model code
sequences that are time offset by the model delays so that the resulting
model code values are closely aligned in time with the received code
sequences, and generating model carrier phases that are closely matched to
received carrier phases, for accurately measuring the code group delay and
carrier phase of each code-modulated signal; the method comprising the
steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phases of the digitized signals with said
counter rotation sinusoids;
multiplying the counter rotated signals with the model code values and
accumulating the multiplication products over respective time intervals;
processing the accumulated products to obtain model phases and model
delays;
receiving a data signal superimposed upon said code-modulated signals,
testing the logic sign of the accumulated products for extracting a data
bit sign therefrom for a data bit interval; and
removing the data bit sign from one code-modulated signal based upon the
data bit sign extracted from another code-modulated signal.
24. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving a code-modulated
signal, providing a digitized signal from said code-modulated signal,
generating model delays, generating a model code sequence that is time
offset by the model delays so that the resulting model code values are
closely aligned in time with the received code sequence, and generating
model carrier phases that are closely matched to received carrier phase,
for accurately measuring the code group delay and carrier phase of the
code-modulated signal; the method comprising the steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phase of the digitized signals with said
counter-rotation sinusoids;
multiplying the counter-rotated signals with the model code values and
accumulating the multiplication products over respective selected time
intervals;
processing the accumulated products to obtain model phase and model delay;
receiving a data signal having defined data-bit intervals and being
superimposed upon said code-modulated signal; and
synchronizing the product accumulation intervals with the data-bit
intervals by offsetting accumulation interval start time with a previously
measured code group delay.
25. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving a code-modulated
signal, providing a digitized signal from said code-modulated signal,
generating model delays, generating a model code sequence that is time
offset by the model delays so that the resulting model code values are
closely aligned in time with the received code sequence, and generating
model carrier phases that are closely matched to received carrier phase,
for accurately measuring the code group delay and carrier phase of the
code-modulated signal; the method comprising the steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phase of the digitized signals with said
counter-rotation sinusoids;
multiplying the counter-rotated signals with the model code values and
accumulating the multiplication products over respective selected time
intervals;
processing the accumulated products to obtain model phase and model delay;
and
estimating model carrier phase over a future time interval by two-point
linear extrapolation of measured phase from prior time intervals.
26. A method of digitally processing signals in a Global Positioning System
(GPS) receiver, the receiver of the type receiving at least two
code-modulated signals, providing digitized signals from said
code-modulated signals, generating model delays, generating model code
sequences that are time offset by the model delays so that the resulting
model code values are closely aligned in time with the received code
sequences, and generating model carrier phases that are closely matched to
received carrier phases, for accurately measuring the code group delay and
carrier phase of each code-modulated signal; the method comprising the
steps of:
generating counter-rotation sinusoids from model phases;
counter-rotating the carrier phases of the digitized signals with said
counter rotation sinusoids;
multiplying the counter rotated signals with the model code values and
accumulating the multiplication products over respective time intervals;
processing the accumulated products to obtain model phases and model
delays; and
averaging measured carrier phase values of one codemodulated signal over a
selected short averaging interval by using concurrently measured values of
carrier phase of another code-modulated signal to remove the averaged
effects of time variation in said one carrier phase over said interval. |
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Claims |
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Description |
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2. Field of the Invention
The present invention relates generally to receivers for the Global
Positioning System and more specifically, to an all-digital GPS signal
processor having a unique digital tracking processor as well as to a
digital processing method carried out therein.
PRIOR ART
The NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) will provide extremely accurate
three-dimensional position and velocity information to users anywhere in
the world. The position determinations are based on the measurement of the
transit time of RF signals from a number of satellites selected from a
total constellation of 18. The signals are modulated with two codes: P,
which provides for precision measurement of transit time; and C/A which
provides for crude measurement of same and for easy lock-on to the desired
signal. The satellites employ a shaped-beam antenna that radiates to a
0-dBic ground antenna near-uniform power of at least -163 dBW for the
L.sub.1 P code and -160 dBW for the L.sub.1 C/A code. The corresponding
L.sub.2 power level carrying only the P code is at least -166 dBW.
At least four satellites are required for navigation purposes. The visible
satellites offering the best geometry can be selected either manually or
automatically by receivers using ephemeris information transmitted by the
satellites. Ranges to the observed satellites are determined by scaling
the signal transit time by the speed of light. The transmitted message
contains ephemeris parameters that enable the user to calculate the
position of each satellite at the time of transmission of the signal.
The measurement of range to the satellites made by the user with an
imprecise clock, is sometimes called "Pseudo-range" because it contains a
bias of fixed magnitude in each range estimate due to the clock error. In
this description, pseudorange will also be referred to as group delay.
The GPS user measures the apparent (pseudo-range) transit time by measuring
the delay or time shift between the pseudorange noise (PRN) code generated
in the space vehicle and the identical code sequence generated by the user
receiver, with each synchronized with its own clock. The receiver code is
shifted until maximum correlation is achieved between the two codes; the
time magnitude of the shaft is the receiver's measure of delay
(pseudo-range).
The navigation signal transmitted from the space vehicles consists of two
RF frequencies, L.sub.1 at 1575.42 MHz and L.sub.2 at 1227.6 MHz. The
L.sub.1 signal is modulated with both the P and the C/A pseudo-random
noise codes in phase quadrature. The L.sub.2 signal is modulated with the
P code. Both the L.sub.1 and L.sub.2 signals are also continuously
modulated with the navigation data-bit stream at 50 bps. The functions of
the codes are twofold: (a) identification of space vehicles, as the code
patterns are unique to each space vehicle and are matched with like codes
generated in the user receiver; and (2) the measurement of the navigation
signal transit time by measuring the phase shift required to match the
codes. The P code is a long precision code operating at 10.23 Mbps and is
difficult to acquire. The C/A (clear access) code is a short code, readily
acquired, but operating at 1.023 Mbps, which provides a more coarse
measurement of delay. The C/A code is a normally acquired first and a
transfer is made to the P code. It is possible, however, for users with
precision clocks precisely synchronized with GPS time and the approximate
knowledge of their position (10,000 ft-20,000 ft) to bypass the C/A code
and acquire the P code directly.
The P code generated in each space vehicle is a pseudo-random noise chip
sequence of seven days in length.
In order for the ground receiver to lock onto the P code, it must know
approximately what time-slice in the seven-day code to search. At typical
receiver search rates, on the order of 50 bits per second, the time
required to search as much as one second of the seven-day P code would
require many hours. It is therefore necessary to resort to the C/A code
for initial code match and lock-on when good a priori information on
receiver position, clock offsets and satellite position is not available.
The C/A code is a pseudo-random noise chip stream unique in pattern to each
space vehicle that repeats every millisecond. It is relatively easy for a
receiver to match and lock onto the C/A code because the search is limited
to the time interval of one millisecond and the chip rate is only
one-tenth that of the P code. The P code frequency affords the degree of
accuracy required for the measurement of signal transit time that the C/A
code frequency could not.
The navigation message contains the data that the user's receiver requires
to perform the operations and computations for successful navigation with
the GPS. The data include information on the status of the space vehicle;
the time synchronization information for the transfer from the C/A to the
P code; and the parameters for computing the clock correction, the
ephemeris of the space vehicle and the corrections for delays in the
propagation of the signal through the atmosphere. In addition, it contains
almanac information that defines the approximate ephemerides and status of
all the other space vehicles, which is required for use in signal
acquisitions. The data format also includes provisions for special
messages.
SUMMARY OF THE INVENTION
There components have been combined in the present invention to produce an
all-digital GPS signal processor with outstanding accuracy, high dynamic
tracking, versatile integration times, lower loss-of-lock signal strengths
and infrequent cycle slips. The three components are: Digital chip
advancer; carrier down-converter and code correlator; and digital tracking
processor.
A highly accurate, all digital correlator and down converter for GPS
receivers permits roundoff and commensurability errors to be reduced to
extremely small values. The use of digital chip and phase advancers
provides outstanding control and accuracy in phase and feedback.
Flexibility is provided by the feature of arbitrary start time and
integration length. A minimum bit design requires a minimum number of
logical elements, thereby reducing size, power and cost.
The invention combines the features of all-digital implementation with C/A
phase-driven fast feedback loops for all phases and delays, thereby
providing high accuracy, high dynamics, loss of lock at lower signal
strengths and infrequent carrier cycle slips. Simple techniques for cycle
counting, data-bit extraction and data-bit synchronization eliminate the
need for involved circuitry and/or software found in existing receivers.
Flexibility is provided in selecting feedback interval and output
averaging interval.
A pseudorandom code sequence is generated by simple digital logic that
incorporates the effects of time, delay and delay rate. For each
integration interval, both chip and chip rate are initialized to a small
fraction of a chip, for example, to the order of 10.sup.-7, thereby making
feedback control and delay extraction highly accurate and flexible.
Appropriate selection of sample rate relative to chip rate, reduces
commensurability errors to extremely small levels.
The digital code generator is initialized each correlation interval on the
basis of the initial integer chip supplied on the basis of feedback by
other hardware or software. The fractional chip register is initialized
with the associated fractional chip supplied by the feedback. The
fractional chip register is then digitally incremented for every
subsequent sample point by the chip change due to both time and delay
rate. Whenever the fractional chip register overflows as the result of an
increment, another chip has been reached and a pulse is sent to the code
generator which responds with the next code sign.
OBJECTS OF THE INVENTION
It is an object of the present invention to provide a compact, highly
accurate, yet simple and versatile carrier down-converter and code
correlator for a GPS receiver, with highly flexible control of phase and
delay.
It is another object of the present invention to provide a reliable,
compact, highly accurate, high dynamic GPS tracking processor with the
simplest possible circuitry and logic, with loss of lock at lowest
possible signal strengths and with extremely infrequent cycle slips.
It is still another object of the present invention to accurately and
simply generate a delayed pseudorandom code sequence with a high degree of
control in a purely digital fashion primarily for use in GPS signal
processing.
It is still another object of the present invention to provide a
high-accuracy, high dynamic GPS baseband processor with variable
integration times, low loss-of-lock signal strengths and extremely
infrequent carrier cycle slips.
It is still another object of the present invention to provide a GPS
digital signal processor in which all fast feedback loops for phase and
delay are driven by C/A L.sub.1 phase, with an additional slow feedback
correction for P-L.sub.1 phase, for P-L.sub.2 phase and for all delays.
It is still another object of the present invention to provide a method of
processing GPS signals in a purely digital manner.
BRIEF DESCRIPTION OF THE DRAWINGS
The aforementioned objects and advantages of the present invention as well
as additional objects and advantages thereof will be more fully understood
hereinafter as a result of a detailed description of a preferred
embodiment when taken in conjunction with the following drawings in which:
FIG. 1 is a simplified block diagram of a GPS receiver employing the
digital processor of the present invention;
FIG. 2 is a functional block diagram of the signal processing in the
tracking processor of the present invention;
FIG. 3 is a functional block diagram of the signal processing in the high
speed digital processor of the present invention;
FIG. 4 is a simplified representation of the digital baseband processor of
the invention;
FIG. 5 is a graphical representation of the quadrature three-level sinsoids
used in the down-converter phase logic of the invention;
FIG. 6 is a schematic illustration of digital operations that produce
three-level down-conversion phasers;
FIGS. 7a and 7b are flow charts of C/A channel signal processing in the
tracking processor of the invention;
FIGS. 8s and 8b, are flow charts of the feedback loop for the C/A channel
in the tracking processor of the invention;
FIGS. 9a and 9b, are flow charts of the P channel signal processing in the
tracking processor of the invention; and
FIG. 10 is a block diagram of a chip advancer used in the present invention
for generating a pseudorandom code sequence.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
To illustrate the use of the digital signal processor in the context of a
complete receiver, reference is first made to FIG. 1 which represents a
top level block diagram of a GPS receiver of the present invention. It is
assumed that antenna, front end, and frequency subsystems are all designed
and implemented in a manner that provides the necessary baseband signals
to the baseband processor. Using fixed-frequency L.O.'s, the frontend
hardware down-converts the GPS signals from RF to baseband, where the
signals are low pass filtered and digitally sampled. Three digitally
sampled signals are supplied: The P.sub.1 and P.sub.2 signals (e.g. each
at 15.374 Ms/sec) and the C/A signal (e.g. at 1.5374 Ms/sec). The three
signal processing paths followed by these three signals will be referred
to as channels herein. Two important aspects of the frequency subsystem
are sampling frequency and L.O. offset frequencies. The sampling frequency
must be highly incommensurate with the fundamental chip rate (e.g. 15.374
MHz vs. 10.23 MHz) so that discrete sampling errors will be negligible. | | |
