Programmable low impedance anti-fuse element

What is claimed is:

1. An electrically programmable semiconductor device comprising a plurality of elements each of which comprises a first electrode, a second electrode, a multilayer dielectric comprising at least two dielectric layers of different dielectric constant disposed between the first electrode and the second electrode, and wherein at least one element has a conductive filament passing through the multilayer dielectric ohmically connecting the first electrode to the second electrode.

2. A plurality of electrically-programmable lowimpedance anti-fuse elements, each of said elements including:

a semiconductor substrate,

a first electrode comprising a heavily-doped region disposed within a selected portion of said substrate,

an insulator covering said heavily-doped region, said insulator having a first layer of silicon dioxide, and a second layer of silicon nitride over said first layer, and

a second electrode comprising a heavily-doped polysilicon layer over said insulating layer,

at least one of said elements further including a conductive filament in said insulator electrically connecting said first electrode and said second electrode.

3. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 2, each of said elements further including a third layer of silicon dioxide over said second layer in said insulator.

4. The plurality of electrically-programmable, low-impedance anti-fuse elements of claim 2, wherein said substrate is P-type and said heavily-doped region and said heavily-doped polysilicon layer are N-type and are doped with arsenic.

5. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 4, wherein said heavily-doped region is doped to a concentration of from 1.times.10.sup.19 to 1.times.10.sup.21 atoms/cm.sup.3 and said heavily-doped polysilicon region has a sheet resistance of from approximately 10-100 ohms/square.

6. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 3, wherein said first layer has a thickness in the range of from 20 to 50 .ANG., said second layer has a thickness in the range from 40 to 100 .ANG., and said third layer has a thickness in the range from 0 to 50 .ANG..

7. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 6, wherein said substrate is P type and said heavily-doped region and said heavily-doped polysilicon region are doped with arsenic.

8. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 7, wherein said heavily-doped region is doped to a concentration of from 1.times.10.sup.19 to 1.times.10.sup.21 atoms/cm.sup.3 and said heavily-doped polysilicon region has a sheet resistance of from approximately 10 to 100 ohms/square.

9. A plurality of electrically-programmable low-impedance anti-fuse elements disposed on a first insulator over a semiconductor substrate, each of said elements including:

a first electrode, including a heavily-doped polysilicon layer over said first insulator, and a metal silicide layer over said polysilicon layer,

a second insulator over said metal silicide layer, said second insulator having a first layer of silicon dioxide and a second layer of silicon nitride over said first layer,

a barrier metal layer over said second insulator, and

a second electrode comprised of a metal over said barrier metal layer,

at least one of said elements further including a conductive filament in said second insulator electrically connecting said first electrode in second electrode.

10. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 9, wherein said polysilicon layer has a sheet resistance of from approximately 10 to 100 ohms/square.

11. The plurality of electrically-programmable low impedance anti-fuse elements of claim 9, each of said elements further including a third layer of silicon dioxide over said second layer in said second insulator.

12. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 11, wherein said polysilicon layer is doped with arsenic.

13. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 12, wherein said first layer of silicon dioxide has a thickness of from 10 to 50 .ANG. said second layer of silicon nitride has a thickness of from 40 to 100 .ANG., and said third layer of silicon dioxide has a thickness of from 0 to 50 .ANG..

14. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 13, wherein said polysilicon layer has a thickness of between 500 to 10,000 .ANG., and said silicide layer has a thickness of from 100 to 5,000 .ANG., and wherein said barrier metal has a thickness of from 50 to 5,000 .ANG..

15. A plurality of electrically programmable low-impedance anti-fuse elements disposed on a first insulator over a semiconductor substrate, each of said elements including:

a first electrode comprised of a metal layer over said first insulator and a layer of barrier metal over said metal layer,

a metal silicide layer over said first electrode,

a second insulator over said metal silicide layer, said second insulator having a first layer of silicon dioxide and a second layer of silicon nitride over said first layer,

a barrier metal layer over second insulator, and

a second electrode comprised of a metal over said barrier metal layer,

at least one of said elements further including a conductive filament in said insulator electrically connecting said first electrode and second electrode.

16. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 15, wherein said first electrode has a metal layer having a thickness of from 5,000 to 15,000 .ANG.and a barrier metal layer having a thickness of from 50 to 5,000 5 .ANG., and a silicide layer over said first electrode having a thickness of from 100 to 5000 .ANG..

17. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 15, each of said elements further including a third layer of silicon dioxide over said second layer in said second insulator.

18. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 17, wherein said first layer of silicon dioxide has a thickness of from 20 to 50 .ANG., said second layer of silicon nitride has a thickness of from 40 to 100 .ANG.and said third layer of silicon dioxide has a thickness of from 0 to 50 .ANG..

19. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 18, wherein said second electrode has a barrier metal layer having a thickness of between 50 to 5,000 .ANG., and a metal layer having a thickness of from 5,000 to 15,000 .ANG..

20. A plurality of electrically-programmable, low-impedance anti-fuse elements, each of said elements including:

a semiconductor substrate,

a first electrode comprising a heavily-doped region disposed within a selected portion of said substrate,

an insulator covering said heavily-doped region, said insulator having a first layer of silicon dioxide, having a thickness in the range of approximately 20-45.ANG., a second layer of silicon nitride over said first layer having a thickness in the range of approximately 45-80.uparw., and a third layer of silicon dioxide having a thickness in the range of approximately 1-20.ANG., and,

a second electrode comprising a heavily-doped polysilicon layer over said insulating layer,

at least one of said elements further including a conductive filament in said insulator electrically connecting said first electrode and said second electrode.

21. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 20, wherein said substrate is P-type and said heavily-doped region and said heavily-doped polysilicon layer are N-type and are doped with arsenic.

22. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 21, wherein said heavily-doped region is doped to a concentration of from 1.times.10.sup.19 to 1.times.10.sup.21 atoms/cm.sup.3 and said heavily-doped polysilicon region has a sheet resistance of from approximately 10-100 ohms/square.

23. A plurality of electrically-programmable low-impedance anti-fuse elements disposed on a first insulator over a semiconductor substrate, each of said elements including:

a first electrode, including a heavily-doped polysilicon layer over said first insulator, and a metal silicide layer over said polysilicon layer,

a second insulator over said metal silicide layer, said insulator having a first layer of silicon dioxide, having a thickness in the range of approximately 20-45.ANG., a second layer of silicon nitride over said first layer having a thickness in the range of approximately 45-80.ANG., and a third layer of silicon dioxide having a thickness in the range of approximately 1-20.ANG.,

a barrier metal layer over said second insulator, and

a second electrode comprised of a metal over said barrier metal layer,

at least of one said elements further including a conductive filament in said second insulator electrically connecting said first electrode in second electrode.

24. The plurality of electrically-programmable low-impedance anti-fuse elements of claim 23, wherein said polysilicon layer has a sheet resistance of from approximately 10 to 100 ohms/square.

25. The plurality of electrically-programmable low impedance anti-fuse elements of claim 23, wherein said polysilicon layer is doped with arsenic.

26. The plurality of electrically-programmable low impedance anti-fuse elements of claim 25, wherein said polysilicon layer has a thickness in the range of approximately 500 to 10,000.ANG., and said silicide layer has a thickness in the range of approximately from 100 to 5,000.ANG., and wherein said barrier metal has a thickness in the range of approximately 50 to 5,000.ANG..

27. A plurality of electrically-programmable low impedance anti-fuse elements disposed on a first insulator over a semiconductor substrate, each of said elements including:

a first electrode comprised of a metal layer over said first insulator and a layer of barrier metal over said metal layer,

a metal silicide layer over said first electrode,

a second insulator over said metal silicide layer, said insulator having a first layer of silicon dioxide, having a thickness in the range of approximately 20-45.ANG., a second layer of silicon nitride over said first layer having a thickness in the range of approximately 45-80.ANG., and a third layer of silicon dioxide having a thickness in the range of approximately 1-20.ANG.,

a barrier metal layer over second insulator, and

a second electrode comprised of a metal over said barrier metal layer,

at least one of said elements further including a conductive filament in said insulator electrically connecting said first electrode and second electrode.

28. The plurality of electrically-programmable low impedance anti-fuse elements of claim 27, wherein said first electrode has a metal layer having a thickness in the range of from approximately 5,000 to 15,000.ANG. and a barrier metal layer having a thickness in the range of from approximately 50 to 5,000.ANG., and a silicide layer over said first electrode having a thickness in the range of from approximately 100 to 5000.ANG..

29. The plurality of electrically programmable low-impedance anti-fuse elements of claim 27, wherein said second electrode has a barrier metal layer having a thickness in the range of from approximately 50 to 5,000.ANG., and a metal layer having a thickness in the range of from approximately 5,000 to 15,000.ANG..

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BACKGROUND

1. Field of the Invention

The present invention relates to the field of integrated electronic circuit technology. More particularly, the invention relates to a reliable and manufacturable capacitorlike, electrically-programmable interconnect device to be used in integrated circuits.

2. The Prior Art

Integrated electronic circuits are usually made with all internal connections set during the manufacturing process. However, because of high development costs, long lead times, and high manufacturing tooling costs of such circuits, users often desire circuits which can be configured or programmed in the field. Such circuits are called programmable circuits and they usually contain programmable links. Programmable links are electrical interconnects which are either broken or created at selected electronic nodes by the user after the integrated device has been fabricated and packaged in order to activate or deactivate respectfully the selected electronic nodes.

Programmable links have been used extensively in programmable read only memory devices (PROMs). Probably the most common form of programmable link is a fusible link. When a user receives a PROM device from a manufacturer, it usually consists of an X-Y matrix or lattice of conductors or semiconductors. At each cross-over point of the lattice a conducting link, called a fusible link, connects a transistor or other electronic node to this lattice network. The PROM is programmed by blowing the fusible links to selected nodes and creating an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data which the user wishes to store in the PROM.

Such fusible link PROM systems present certain disadvantages. For instance, because of the nature of the conducting material in the link, relatively high voltage and high current levels are needed during programming to guarantee the complete blowing of the fusible links. Since the link is usually conductive, it needs large amounts of power dissipation to blow it. Also, the shape and size of the fusible link must be precise so that the link will function effectively as a conductor if it is not blown and will be a completely open circuit if it is blown. Therefore, very critical photolithographic steps and controlled etch techniques are required during the manufacturing process of fusible link PROMS. Finally, a large gap must be blown in the link in order to prevent it from later becoming closed through the accumulation of the conducting material near the blown gap. Fusible link memory cells are relatively large in order to accommodate the link and its associated selection transistor and, therefore, fusbile link PROM systems have high manufacturing and material costs and take up large amounts of chip real estate space.

In recent years, a second type of programmable links, called anti-fuse links, have been developed for use in integrated circuit applications. Instead of the programming mechanism causing an open circuit as is the case with fusible links, the programming mechanism in anti-fuse circuits creates a short circuit or relatively low resistance link. Anti-fuse links consist of two conductor and/or semiconductor materials having some kind of a dielectric or insulating material between them. During programming, the dielectric at selected points in between the conductive materials is broken down by predetermined applied voltages, thereby electrically connecting the conducting or semiconducting materials together.

Various materials have been suggested for the dielectric or insulating layer. Some of these suggested dielectric materials require a relatively high current and voltage during programming, require complex manufacturing techniques and have low reliability during programming because it is difficult to control the reproducibility of the conductive state due to the nature of the crystalline structures of the materials involved. In addition, the programming process results in a link having a finite resistance in the order of several hundred to several thousand ohms. This characteristic of the known anti-fuse elements renders them relatively unsuitable for use in high speed circuits.

Some of the proposed dielectric insulators are doped amorphous silicon alloys, polycrystalline resistors, oxides, titanate of a transition metal, silicon oxide, aluminum oxide and cadmium sulfide. The problems with these approaches, have been related to the need of a high current and voltage to program and the difficulty to manufacture and control their reliability in both the on and off states. Materials such as cadmium sulfide, aluminum oxide and titanate, present complicated technological problems because they are difficult to integrate into standard semiconductor processing. Capacitors with silicon oxides used as a dielectric do not produce a low enough impedance after programming.

Examples of known anti-fuse elements are found in the prior art using various insulating materials. Reference is made to: U.S. Pat. No. 3,423,646 which uses aluminum oxide, cadmium sulfide; U.S. Pat. No. 3,634,929 which uses single film of AL.sub.2 O.sub.3, SiO.sub.2, and Si.sub.3 N.sub.4 ; U.S. Pat. No. 4,322,822 which uses SiO.sub.2 ; U.S. Pat. No. 4,488,262 which uses oxide or titanate of a transition metal; U.S. Pat. No. 4,499,557 which uses doped amorphous silicon alloy; U.S. Pat. No. 4,502,208 which uses SiO.sub.2 ; U.S. Pat. No. 4,507,757 which uses SiO.sub.2 ; U.S. Pat. No. 4,543,594 which uses SiO.sub.2.

Most of the above patents either describe complicated technologies or need high breakdown voltages and currents, and or are difficult to manufacture or do not meet the reliability requirements of state-of-the-art integrated circuits in both the on and off states. These patents do not disclose the creation of controllable conductive filaments with low resistance after programming.

Other problems associated with existing dielectric materials in anti-fuse links include large memory cells, and complex manufacturing processes for the unblown anti-fuse elements.

OBJECTS AND ADVANTAGES

An object of the present invention is to provide an electrically programmable low-impedance interconnect element.

Another object of the present invention is to provide an electrically programmable interconnect element which may be programmed with sufficiently low voltages and currents compatible with state-of-the-art MOS technology, resulting in a low impedance in the on-state.

Another object of the present invention is to provide an electrically-programmable interconnect element which is manufacturable using standard semiconductor processing and has high reliability in both the on and off states.

Advantages associated with the present invention in some or all of its embodiments include an interconnect which can be made with standard semiconductor manufacturing techniques, having a small size, a high reading current after programming, may be fabricated using manufacturing process with a minimal number of steps, and having a controlled radius interconnect filament through the dielectric after programming resulting in a repeatably manufacturable controlled low resistance link after programming. Furthermore, the present invention is characterized by high reliability in both the programmed and unprogrammed state. Other and further advantages of the present invention will appear hereinafter.

SUMMARY OF THE INVENTION

An electrically programmable anti-fuse, having a low impedance after programming, is disclosed. It consists of a capacitor-like structure with very low leakage current before programming and a low-resistance after programming.

This low impedance anti-fuse element is formed by having a dielectric between two conductive electrodes. In a preferred embodiment, one or both of the two conductive electrodes may be made of a high electromigration immunity material and may be formed from either heavily doped polysilicon, heavily doped single crystal silicon, or refractory metal such as tungsten, molybdenum, platinum, titanium, tantalum, or their silicides or a sandwich of polysilicon and metal. Those of ordinary skill in the art will recognize that the metal may be any substance used to provide interconnect in integrated circuits or which is used as a diffusion barrier. In addition, it is believed that combinations of the above materials will function in the present invention. In other embodiments, lower electromigration immunity materials may be used as long as the current passed through the low impedance anti-fuse after programming is appropriately limited to assure proper lifetime.

The dielectric layer, single or composite, between the two electrodes is such that when it is disrupted by a high electric field it will facilitate the flow of one of the two electrodes to produce a controlled radius conductive filament during its breakdown. It requires a low amount of charge fluence to breakdown at the higher programming voltage with practically-used voltages and currents in integrated circuits. It also has a large enough charge fluence to breakdown at normal operating voltages to be a reliable circuit element during operation in its off state.

During programming, as the applied voltage reaches the dielectric breakdown, a localized weak spot in the dielectric starts to carry most of the leaking current and heats up, which, in turn, increases the leakage current. A thermal runaway condition develops which results in localized heating and melting of the dielectric and adjacent electrode material. The conductive material flows from one of the two electrodes and forms a conductive filament shorting both electrodes. The thickness of the electrodes should be sufficient not to cause any discontinuity or pits during the filament formation. The final radius of the filament depends on the composition and thickness of the dielectric, the electrode conductive material melting temperature, and the energy dissipated during programming. Lower final resistance of this element after its programming can be obtained with a larger radius and a lower resistivity of the formed filament and a lower spreading resistance of both electrodes. A larger filament radius and higher electromigration immunity of the conductive electrode material that flows to form the filament result in higher current carrying capacity of the programmed element without blowing open due to electromigration.

In a preferred embodiment, one of the conductors, the top electrode, is formed of heavily doped polysilicon of either n+(or p+) or is a sandwich of said polysilicon and a metal above it and the other conductor, the lower electrode, is formed of heavily doped equal polarity n+(or p+) diffusion region in a substrate or a well of opposite polarity p (or n). The dielectric in this embodiment is a three-layer sandwich formed of a bottom oxide layer of 20A-50A, a central silicon nitride layer of 40A-100A, and a top oxide layer of 0A to 50A.

The low impedance anti-fuse element in the first preferred embodiment is programmed by applying a current-controlled voltage source across the two conductors (electrodes). The composition of the composite dielectric is such that the structure provides an on-resistance of less than 300 ohms after programming and an off-resistance of more than 100 Mohns before programming. The structure requires a programming pulse of magnitude less than 30 volts, a time duration of less that 100 mSec while supplying a current of less than 10 mA. The size of the conductive filament is a function of the programming pulse and the composition of the composite dielectric structure and its radius is in the range of 0.02 um to 0.2 um.

In a second and third embodiment of the low impedance anti-fuse element, the low impedance anti-fuse element or capacitor anti-fuse is between two conductors (metal lines or polysilicon lines). This facilitates the interconnect between two conductors without using the silicon substrate as a path. Hence, the substrate can be used for active devices.

Those of ordinary skill in the art will recognize that the technology of this invention is compatible with and may be applied to any semiconductor structure or process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-section of a preferred embodiment of a low impedance anti-fuse element fabricated on a semiconductor substrate material in accordance with the present invention.

FIG. 2a is a cross-section of an alternative embodiment of a low impedance anti-fuse element according to the present invention having one metal electrode and one polysilicon electrode.

FIG. 2b is a cross-section of an alternative embodiment of a low impedance anti-fuse element according to the present invention having two metal electrodes.

FIG. 3 is a simplified cross-section of a element after programming.

FIG. 4 is a cross section of a element like the embodiment disclosed with respect to FIG. 1 fabricated on a semi-conductor substrate material wherein semiconductor material is employed as the electrically conducting material.

FIGS. 5a and 5b are schematic diagrams of the equivalent circuit of the low