High-frequency transistors are formed on a semiconductor substrate. Each transistor includes an emitter having a fish-bone structure, a base formed to surround the emitter, and a base lead region connected to the base. A resistor layer having the same conductivity type as that of the base lead region, and an impurity concentration and a junction depth equal to those of the base lead region is formed in the substrate. An emitter electrode is connected to the emitter and the resistor layer. A portion of the emitter electrode connected to the resistor layer has an interdigital structure, and is connected to the resistor layer at two or more contact surface portions or an interdigital surface portion. An electrode on the wiring layer side is connected to the resistor layer. A portion of the electrode connected to the resistor layer has an interdigital structure which matches with the interdigital structure of the emitter electrode.

A transistor structure incorporates a polysilicon layer which is doped with N-type dopants and is used as an emitter ballast resistor in an array of NPN transistors. In one embodiment, the polysilicon layer is also used as a diffusion source to form N-type emitter regions within a deep and high resistivity P-well, which acts as a relatively high value base ballast resistor for the transistor. In another embodiment, a standard base is used, contributing little base ballast resistance. A buried collector region carries collector current. Preferably, the emitter regions are formed as oblong strips. P-type base contact regions, also generally formed as oblong strips, are formed in the surface of this P-well parallel to the emitter regions. The dimensions of the base contact regions may be varied in order to achieve a constant base-emitter voltage along the entire length of each emitter strip. An emitter metal layer overlies the polysilicon layer and contacts the polysilicon layer through openings in an insulating layer. The resulting three dimensional structure in one embodiment thus incorporates a stacked collector region, base ballast resistor, base region, emitter regions, emitter ballast resistors, and emitter metal layer. In another embodiment, the same three dimensional structure results except that there is no base ballast resistor. Dimensions of the emitter metal layer and other metal layers may be adjusted so that the transistor structure has a trapezoidal shape and requires less silicon real estate.

A semiconductor device including a substrate, a semiconductor element formed on the substrate, a terminal formed on the substrate and electrically connected to the semiconductor element, and a protective resistor formed on the substrate and electrically connected between the semiconductor element and the terminal. The resistor is composed of a ferromagnetic magnetoresistive material including Ni alloy. The device may be extended to detect magnetism by adding a magnetoresistive element composed of a ferromagnetic magnetoresistive material including the same Ni alloy as for the protective resistor and deposited at the same time. The device is superior in an anti-noise characteristic and is integrated. Furthermore, the device for detecting magnetism is formed with a lower cost.

Disclosed are devices having emitters having resistive emitter diffusion sections are in a radial pattern. Such devices include vertical PNP power devices. The radial pattern of holes defines resistive emitter diffusion sections between adjacent holes. The resistive emitter diffusion sections result in a lower emitter ballast resistance due to the higher emitter sheet resistance of PNP devices. This allows all the periphery of the emitter to be active, not just two sides. The device has improved emitter ballast resistance while at the same time remaining efficient with low saturation resistance.

A layout is provided for RF power transistors that reduces common lead inductance and its associated performance penalties. An RF transistor cell is rotated 90.degree. with respect to a conventional RF transistor cell so as to located bond pads nearer the edge of a silicon die, reducing bond wire length and common lead inductance and thereby improving performance at high frequencies. The placement of bond pad and distribution of different parts of the transistor layout further reduces common lead inductance.