Static frame digital memory - Patent Review 4839796

Claims

What is claimed and desired to be secured by United States Letters Patent is:

1. In a digital computer including a high speed address generating device, an address bus, and a data bus, a digital memory system for rapidly accessing and retrieving binary information, the binary information being organized into frames and words contained in the frames, the digital memory system comprising:

digital memory storage means comprising a plurality of memory arrays, each array comprising memory locations defined by a plurality of rows and columns by which individual locations in each array are addressable, corresponding rows from each array together providing storage for at least a portion of said frames, the digital memory storage means further comprising (a) row activation means for activating in response to a first row address presented on the address bus corresponding first rows storing at least a portion of one of said frames, and (b) column selecting means for selecting in response to a sequence of column addresses presented on the address bus a sequence of memory locations on the first rows and accessing the memory locations identified by the activated first rows and selected columns;

tag means for storing a row identification portion of a first address presented on the address bus which identified and caused the activation of the first rows; and

comparator means for determining whether a second address presented on the address bus includes a row identification portion which is equivalent to the row identification portion stored in the tag means, the comparator means generating an acknowledge signal whenever the row identification portion of the second address is equivalent to the row identification portion stored in the tag means thereby allowing the binary information contained in the memory locations on the first rows and identified by a column address portion of the second address to be output by the memory storage means directly onto the data bus in response to the presentation of the second address.

2. A memory system as defined in claim 1 wherein the memory means comprises at least on memory device and wherein the corresponding first rows of the memory array are equivalent to a frame.

3. A memory system as defined in claim 1 wherein the digital memory storage means comprises a plurality of static column random access memory devices.

4. A memory system as defined in claim 1 wherein the digital memory storage means comprises a plurality of static column random access memory devices, the static column random access memory devices interconnected such that at least one frame may be activated into static column mode.

5. A memory system as defined in claim 4 wherein the digital memory storage means comprises a plurality of static column random access memory devices interconnected such that a number of bits equal to a word may be simultaneously accessed.

6. A memroy system as defined in claim 5 wherein the word length comprises 32 bits.

7. A memory system as defined in claim 1 wherein the digital memory storage means comprises a plurality of banks, each bank capable of activating at least a frame into static column mode and wherein the row identification portion comprises a frame identification portion.

8. A memory system as defined in claim 7 wherein the digital memory storage means further comprises a plurality of static column random access memory devices and each bank comprises a plurality of static column random access memory devices.

9. A memory system as defined in claim 8 further comprising:

tag means for each bank, the tag means for storing a frame identification portion of an address previously presented on the address bus;

comparator means for each bank, the comparator means for comparing the frame identification portion stored in the tag means with a frame identification portion of an address currently presented on the address bus; and

acknowledge means for indicating to the address generating device that the frame identification portion stored in the tag means and the frame identification portion of the address currently presented on the address bus are equivalent.

10. A memory system as defined in claim 1 wherein the tag means comprises means for storing a frame identification portion of the first address which was previously presented on the address bus and wherein the comparator means comprises means for comparing the frame identification portion stored in the tag means with a frame portion of a second address which is currently presented on the address bus.

11. A memory system as defined in claim 1 wherein the digital computer further includes a memory management unit adapted for translating logical addresses to physical addresses, the logical addresses including a page portion identifying a page in virtual memory, the page portion corresponding to a frame in physical memory and wherein the digital memory storage means comprises a plurality of banks, each bank including a plurality of static column random access memory devices arranged to hold at least one frame in static column mode in each bank, and

wherein the tag means comprises a plurality of tag registers, each tag register associated with one bank, the tag registers each adapted for storing a page portion of a logical address, and

wherein the comparator means comprises a plurality of comparators, each comparator associated with one tag register, a first input of each comparator in communication with the output of its associated tag register and a second input of each comparator in communication with the address bus each comparator adapted to compare the value stored in the associated tag register with the page portion of a logical address presented on the address bus, and

wherein the memory system further comprises means for acknowledging to the address generating device that a hit has occurred.

12. A memory system as defined in claim 11 further comprising a transparent latch connected to the address bus, the transparent latch adapted to latch a page portion of the logical address and wherein the second input of each comparator is in communication with the output of the transparent latch.

13. A memory system as defined in claim 11 further comprising a multiplexor having inputs connected to the address bus and having outputs connected to the plurality of static column random access memory devices, the multiplexor being adapted to selectively apply a column address field or a row address field to the address inputs of the plurality of static column random access memory devices.

14. A memory system as defined in claim 11 further comprising a bank decode circuit connected to the address bus, the bank decode circuit comprising means for activating a frame in any of the plurality of banks into static column mode.

15. A memory system for rapidly accessing locations within a digital memory frame, the memory system adapted for use with a digital computer including an address generating device, a data bus, and an address bus, the memory system comprising:

digital storage means comprising an address input in communication with the address bus, at least one data port in communication with the data bus, and a plurality of memory array locations, accessed by a first presentation of a frame address and a subsequent presentation of at least one word address, and further comprising means for allowing the presentation of a plurality of word addresses without an intervening presentation of a frame address, whereby the presentation of each word address causes a location in the memory array to be place in communication with the data bus;

addressing means for presenting a word address portion to the digital storage means;

tag means for storing a frame address portion of a previously presented address placed on the address bus, the frame address portion identifying a set of memory locations corresponding to a portion of the digital storage means addressed by a frame address;

comparator means for (a) determining if the frame address portion of a previously presented address stored in the tag means is equivalent to a frame address portion of a currently presented address placed on the address bus and for (b) generating an acknowledge signal if the frame address portion of the currently presented address is equivalent to the frame address portion of the previously presented address; and

means for communicating the acknowledge signal to the address generating device to indicate that the presentation of the currently presented address on the address bus has caused the desired location in the memory array to be placed in communication with the data bus.

16. A memory system as defined in claim 15 wherein the digital memory means comprises at least one memory device wherein each set of active locations within the memory array is equivalent to a frame.

17. A memory system as defined in claim 15 wherein the digital memory means comprises a plurality of static column random access memory devices, the static column random access memory devices interconnected such that at least one frame may be activated into static column mode.

18. A memory system as defined in claim 17 wherein the digital memory means comprises a plurality of static column random access memory device interconnected such that a number of bits equal to a word may be simultaneously accessed.

19. A memory system as defined in claim 18 wherein the word is equal to 32 bits.

20. A memory system as defined in claim 15 wherein the digital memory means comprises a plurality of banks, each bank capable of activating at least an entire frame into static column mode.

21. A memory system as defined in claim 14 wherein the digital computer implements a virtual memory scheme whereby both logical addresses and translated physical addresses are sequentially presented on the address bus and wherein the tag means comprises a tag register adapted for storing a frame address portion of a logical address.

22. A memory system as defined in claim 21 wherein the digital memory means further comprises a plurality of static column random access memory devices, each bank comprising at least one static column random access memory device.

23. A memory system as defined in claim 22 further comprising a transparent latch connected to the address bus, the transparent latch adapted to latch a frame portion of the logical address and wherein the input of each tag register is in communication with the output of the transparent latch.

24. A memory system as defined in claim 23 wherein the comparator means comprises a plurality of comparators, each comparator having a first input connected to the address bus and a second input connected to the output of the tag register.

25. A memory system as defined in claim 22 further comprising a multiplexor having inputs connected to the address bus and having outputs connected to the plurality of static column random access memory devices, the multiplexor being adapted to selectively apply a column address field or a row address field tothe address inputs of the plurality of static column random access memory devices.

26. A memory system as defined in claim 20 further comprising a bank decode circuit connected to the address bus, the bank decode circuit comprising means for activating a frame in any of the plurality of banks into static column mode.

27. A memory system for use in a digital computer including an address generating device in communication with an address bus and a data bus, the memory system comprising:

a plurality of memory banks, each memory bank comprising a plurality of digital memory devices having their address inputs in communication with the address bus, each memory device capable of operating such that the presentation of a first device address activates a frame of memory array locations into static random access mode such that a plurality of locations in the frame of memory array locations may be sequentially accessed as a static random access memory by the presentation of a plurality of second device addresses, the digital memory devices all having a data port in communication with the data bus and the presentation of a second device address causes the addressed memory array location to be placed in communication with the data bus;

a plurality of tag registers, each tage register associated with one bank, the tag registers adapted for storing at least a frame address portion of the last address presented on the address bus which caused an access to a location in the bank associated with the tag register, the frame address portion corresponding to one frame of memory array locations which may be activated into static random access mode;

a plurality of comparators, each comparator associated with a tag register, the comparators adapted for (a) comparing the value stored in the associated tag register with the value of a frame address portion of a currently presented address placed on the address bus and for (b) asserting a hit signal if the two compared values are equivalent; and

means for acknowledging to the address generating device if the comparator has asserted a hit signal and that the addressed memory location has been placed in communication with the data bus.

28. A memory system as defined in claim 27 wherein the plurality of digital memory devices comprise a plurality of static column random access memory devices.

29. A memory system as defined in claim 28 wherein the first device address comprises a row address of the plurality of static column random access memory devices and wherein the second device address comprises a column address to the plurality of static column random access memory devices.

30. A memory system as defined in claim 27 wherein the digital computer includes a memory management unit which controls the presentation of logical address and physical addresses on the address bus, and wherein the memory system further comprises a transparent latch, the transparent latch connected to the address bus and adapted for latching the value of a portion of the logical address corresponding to a frame of memory array locations, the output of the transparent latch connected to the input of the plurality of tag registers.

31. A memory system as defined in claim 27 wherein each bank comprises thirty-two static column random access memory devices having their outputs connected to form a thirty-two bit data pathway in communication with the address bus.

32. A static frame digital memory for use in a digital computer including an address generating device connected to an address bus and a data bus, the digital computer implementing a virtual memory scheme wherein virtual memory is divided into pages and the address generating device sequentially presents a logical address including a column address field and a remainder field to the static frame digital memory, the static frame digital memory comprising:

a plurality of memory banks, each memory bank comprising a plurality of static column random access memory devices, the static column random access memory devices being arranged such that at least one frame may be held in static column mode in each bank, the frame being of a size sufficient to hold one page of data;

a multiplexor circuit receiving input from the address bus and outputting a column address to all of the static column random access devices;

a plurality of tag registers, one tag register being associated with each bank, the tag registers each being adapted to store the value of the logical address remainder field of the most recent address presented on the address bus which caused an access to the bank associated with the tag register;

a latch circuit with inputs connected to the address bus and outputs connected to the inputs of all of the tag registers, the latch circuit holding the value of the remainder field of the address currently presented on the address bus;

a plurality of comparators, each comparator being associated with one bank and its associated tag register, each comparator being adapted for (a) ascertaining if a hit has occurred by determining if the value of the remainder field of the address currently presented on the address bus is equivalent to the value stored in the associated tag register and for (b) asserting a signal if the values are equivalent; and

means for acknowledging to the address generating device that a hit has occurred.

33. A method of controlling the memory functions of a digital computer, the digital computer including an address generating device, an address bus, and a data bus, the method comprising the steps of:

providing a digital memory device having address inputs in communication with the address bus and having at least one data port in communication with the data bus, the digital memory device including a memory array wherein the presentation of a first device address to the address inputs causes the activation of a set of active locations within the memory array and the presentation of a second device address to the address inputs causes a memory location in the set of active locations to be placed in communication with the data bus;

presenting a currently presented address on the address bus;

comparing the currently presented address with a previously presented address to determine if the location to be accessed by the currently presented address is contained within the set of active locations in the memory array;

presenting the second device address to the digital memory device; and

accessing the memory location in the set of active locations identified by the second device address if the location to be accessed by the currently presented address is contained within the active set of locations.

34. A method as defined in claim 33 wherein the step of providing at least one digital memory device comprises the steps of:

providing a plurality of static column random access memory devices; and

organizing the plurality of static column random access memory devices into banks such that each bank is capable of activating at least one frame into static column mode.

35. A method as defined in claim 33 wherein the digital computer implements a virtual memory scheme including the steps of presenting a logical address on the address bus for each memory access followed by the conditional presentation of a translated physical address, and wherein the step of presenting a currently presented address comprises the steps of:

presenting a logical address on the address bus, the logical address including a field identifying a specific location within a frame; and

presenting a translated physical address on the address bus, the translated physical address also including a field identifying the specific location within a frame.

36. A method as defined in claim 35 further comprising the step of storing a field in the logical address identifying a frame in physical memory.

37. A method as defined in claim 35 wherein the step of comparing the currently presented address with a previously presented address comprises the step of comparing a portion of the previously presented logical address which corresponds to a memory frame with a portion of the currently presented logical address which corresponds to a memory frame.

38. A method as defined in claim 33 wherein the step of providing a digital memory device comprises the step of providing a static column random access memory device and wherein the first device address comprises a row address and the second device address comprises a column address.

39. A method of performing memory accesses in a digital computer, the digital computer including an address generating device, an address bus, and a data bus, the method comprising the steps of:

providing at least one digital memory device having an address input in communication with the address bus and having at a data port in communication with the data bus, the digital memory device including a two dimensional memory array wherein the presentation of a first device address to the address input causes the selection of a set of active locations within the memory array and the sequential presentation of a plurality of second device addresses to the address input causes a plurality of memory locations in the set of active locations to be sequentially connected to the data port;

presenting an original address on the address bus from the address generating device;

selecting a set of active locations containing the memory array location identified by the original address;

selecting a first memory array location within the set of active locations corresponding to the original address;

accessing the first memory array location;

presenting a subsequent address on the address bus from the address generating divide;

determining if the location corresponding to the subsequent address is contained within the selected set of active locations;

selecting a second memory array location identified by the subsequent address from the set of active locations if the second single location is contained within the active set of locations; and

accessing the second memory array location.

40. A method as defined in claim 39 wherein the step of providing at least one digital memory device comprises the step of providing at least one static column random access memory device and wherein the first address comprises a row address and the second device address comprises a column address.

41. A method as defined in claim 40 wherein the step of selecting a set of active locations comprises the steps of:

presenting a row address to the static column random access memory device; and

asserting a row address selection signal.

42. A method as defined in claim 41 wherein the step of accessing the first memory array location comprises the step of presenting a column address to the static column random access memory device.

43. A method as defined in claim 42 wherein the step of accessing the first memory array location further comprises the step of asserting a chip select signal.

44. A method as defined in claim 39 wherein the step of determining if the location corresponding to the subsequent address is contained within the selected set of active locations comprises the steps of:

storing at least a portion of the original address;

comparing the stored portion of the original address with a corresponding portion of the subsequent address; and

generating an acknowledge signal if the compared portions are equivalent.

45. A method as defined in claim 39 further comprising the step of arranging a plurality of digital memory devices into banks, the digital memory devices organized such that a frame in memory is equivalent to a set of active locations.

46. A method as defined in claim 39 further comprising the steps of:

presenting a plurality of subsequent addresses on the address bus, the locations corresponding to the subsequent addresses being contained within the selected set of active locations;

sequentially selecting a plurality of memory array locations identified by the corresponding subsequent addresses; and

sequentially accessing the plurality of memory array locations.

47. A method of operating a memory system in a digital computer, the digital computer including an address generating device, an address bus, and a data bus, the method comprising the steps of:

providing a pluraity of memory devices capable of operating in a static column mode, the address inputs of the memory devices in communication with the address bus and the data ports of the memory devices in communication with the data bus;

presenting a first address on the address bus;

activating a set of locations in the memory devices into static column mode, the set of locations containing the memory location identified by the first address;

storing a portion of the first address;

presenting a second address on the address bus;

comparing the stored portion of the first address with a corresponding portion of the second address to determine if the set of locations activated into static column mode contain the memory location identified by the second address; and

accessing the memory location identified by the second address if the memory location is located in the set of locations activated into static column mode.

48. A method as defined in claim 45 wherein the step of providing a plurality of memory devices comprises providing a plurality of static column random access memory devices.

49. A method as defined in claim 47 wherein the step of providing a plurality of memory devices comprises the step of providing a pluraity of static column random access memory devices, the random access memory devices being organized into banks, each bank including at least one static column random access memory device.

50. A method as defined in claim 47 further comprising the step of organizing the banks such that each bank contains memory frame which may be activated into static column mode.

51. A method as defined in claim 47 wherein the digital computer further includes a memory management unit which translates logical addresses into physical addresses and wherein the step of presenting a first address on the address bus comprises the steps of:

presenting a first logical address on the address bus; and

presenting a first physical address on the address bus; and

wherein the step of storing a portion of the first address comprises storing a portion of the first logical address.

52. A method as defined in claim 49 wherein the step of presenting a second address comprises the step of presenting a second logical address and wherein the step of comparing the stored portion of the first address comprises the step of comparing the stored portion of the first logical address with a corresponding portion of the second logical address.

53. A method as defined in claim 52 further comprising the steps of:

generating an acknowledge signal if the compared portions of the first and second logical addresses are equivalent; and

presenting the acknowledge signal to the address generating device.

54. A method as defined in claim 49 wherein the step of storing a portion of the first address further comprises storing a portion of a plurality of first addresses, each stored first address being associated with a bank, and wherein the step of comparing the stored portion of the first address further comprises comparing a portion of the second address with all the stored first addresses and wherein the method further comprises the step of acknowledging to the address generating device if a match occurs.

55. A method as defined in claim 49 wherein the step of accessing the memory location identified by the second address comprises the step of presenting a column address to the plurality of static column random access devices.

56. A method of operating a static frame digital memory system in a digital computer, the digital computer including an address generating device, an address bus, and a data bus, the digital computer implementing a virtual memory scheme wherein logical addresses comprising a column field and a remainder field and which identify locations within a page of virtual memory are presented on the address bus and translated physical addresses and which identify frames within the static frame digital memory system are also presented on the address bus, the method comprising the steps of:

providing a plurality of static column random access memory devices organized into banks such that at least one frame may be activated into static column mode in each bank by presenting a device row address to at least one static column random access memory device in each bank;

presenting a first logical address on the address bus;

defining a column field of the first logical address and presenting the column address to all static column random access memory devices;

defining a remainder field of the first logical address;

latching the remainder field of the first logical address into a logical address latch;

presenting a first translated address on the address bus;

defining a row device address field in the translated address;

presenting a row device address to the static column random access memory devices and activating a frame into static column mode in a bank;

storing the reaminder field latched into the logical address latch in a tag register which is associated with the bank containing the activated frame;

performing a static column mode access on the location identified by the first translated address and maintaining the active frame in static column mode;

presenting a second logical address on the address bus;

defining a column field of the second logical address and presenting the column address to all static column random access memory devices;

defining a remainder field of the second logical address;

latching the remainder field of the second logical address into a logical address latch;

comparing the value of the remainder field latched into the logical address latch with the values previously stored in the plurality of tag registers;

performing a static column mode access in the active frame which has been maintained in static column mode on the location within the active frame indentified by the column field in the second logical address; and

acknowledging to the address generating device that the memory access has occurred.