In a data processing system, multiple requests for a service are stored on a deferred list formed out of already allocated memory space. Specifically, a received service request is added to the deferred list by altering the request as dictated by a stated convention. Preferably, the convention mandates that an instruction pointer of the received service request is decremented or otherwise manipulated. The altered received service request then is exchanged for a sevice request currently held at the service. The altering and exhanging are performed atomically. The service request that was previously held for the service is sent to the head of the current deferred list. It is preferred that the deferred list be formed out of activation frames.

Data packet circulates in the order of program storing portion, data pair producing portion and operation processing portion, so that operation processing based on the data flow program stored in the program storing portion progresses. Priority information is applied in advance to the data flow program stored in the program storing portion. If hash collision occurs in the data pair producing portion, the data pair producing portion determines priority for data pair production processing in accordance with the priority information, so that data pair production processing is first formed with respect to the data packet having higher priority.

A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

A RICS microprocessor architecture is provided with a plurality of data registers and instruction registers each having a multi-bit extension for extending the width of the data and instruction words processed therethrough. A first plurality of bits within a tag field of the multi-bit extension are reserved for identifying the data type of the data words while a second plurality of bits provide instruction dependent control. The multi-bit extension allows full precision computation for the data words requiring the tag field to identify the data type thereof while retaining full precision compatibility for data words not needing tag field identifiers. At least two bits of the first plurality of bits in tag field are reserved for identifying one of several primary categories of data types and at least two bits identify one of several subtype categories within each of the plurality of primary categories. An extended set of machine instructions is also provided for efficient usage of the multi-bit extension appended to the data and instruction registers.