The fabrication of a printed circuit board (26) usually includes the step of testing the board with a testing machine (24) to verify operability. The testing machine accomplishes such testing by transmitting test signals to the board via a transmission line (36) and then analyzing each response signals returned from the board in response to the test signals. To reduce the incidence of error, the testing machine (24) is compensated for the propagation delay of the line (12) which is measured by launching a first string of pulses into one end of the line whose opposite end is left open. A second string of pulses is simultaneously launched into a programmable delay line (16) which delays each second pulse by an adjustable interval. After the generation of each first and second pulse, a check is made whether the first pulse has been reflected back to the first end of the transmission line at the same time the second pulse reaches the output of the delay line. If the pulses are not coincident, the delay setting of the delay line is increasaed and then a check is again made whether one of the first and second pulses are coincident. The delay of the delay line is successively increased until the pulses are coincident whereupon the delay of the delay line now equals twice the delay of the transmission line.
Circuitry and techniques are for transferring data between the automatic test equipment (ATE) and an integrated circuit under test pursuant to a slow clock that can have an arbitrarily long period, and for operating storage elements in the integrated circuit pursuant to a fast clock having a short period that corresponds to the clock rate at which combinatorial networks in the integrated circuit are to be tested. In one embodiment, input latches at inputs of the integrated circuit receive test data from the ATE, and output latches at the outputs provide test result data for the ATE. Pursuant the alternating single cycles of the slow clock and the fast clock, the delays through combinatorial networks between of a data propagation path between an input latch and an output latch are tested pursuant to the fast clock. In another embodiment, test data is serially scanned into scan registers pursuant to a series of slow clock cycles. After the test data has been scanned in, the scan registers are operated parallel to test the delays of combinatorial networks between the scan registers.
In particular in automatic testing equipment for integrated circuits, all signal sections at the test piece joint should ideally be of the same electrical length. The signal sections used in the test consist, in the case of reception, of cable, comparator, error logic, etc. If the signal sections are of different electrical durations, then in the case of reception, the transmitted signal must be connected. In a process for determining the electrical duration of signal sections, each of which has a transmitter and a receiver and at the end connecting points for example for an integrated circuit, the connecting points (AS) of all signal sections (SS) are short-circuited, all receivers up to the receiver of the signal section to be measured are then switched off, all transmitters up to the transmitter of the signal section to be measured are switched on and simultaneously emit a pulse which is transmitted to the connecting point. At the short-circuited connecting points (AS) of the signal sections (SS), a central pulse (21) is then produced which is transmitted over the signal section to be measured to its receiver (E). The time at which the pulse produced by the central pulse enters the receiver (E) is recorded and entered in a table. The above-mentioned process is carried out for all signal sections. The measurements so obtained give the relative durations of the various signal sections. The process for determining the duration of signal sections requires only that the connecting points of the signal sections be connected with one another through a short-circuit bridge (KB).
A programmable timing unit having a number of event markers circuits that receive a master clock signal and generate an output when a predetermined time occurs. Optionally, the event marker circuit can add an interpolated delay time to provide greater resolution than the master clock circuit. The output is programmably coupled to any of a number of function circuits. Each function circuit has a trigger input for receiving the event signal and output for providing the delayed output function.
A programmable timing unit having a number of event markers circuits that receive a master clock signal and generate an output when a predetermined time occurs. Optionally, the event marker circuit can add an interpolated delay time to provide greater resolution than the master clock circuit. The output is programmably coupled to any of a number of function circuits. Each function circuit has a trigger input for receiving the event signal and output for providing the delayed output function.
Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective application of bias voltages to the MOS varactors may be employed to selectively delay one pair of differential signals with respect to another pair of differential signals so as to change the relative phases of the signals. A logic circuit may be used to control the application of bias voltage to the MOS varactors so that signal phases may be adjusted in a manner that is predictable and programmable. These methods may be implemented to compensate for phase offsets between in-phase and quadrature signals of a local oscillator.
