Input apparatus of electronic system for extracting pitch data from input waveform signal

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus for extracting pitch data from an input waveform signal and an electronic system of a type for generating a musical tone having a pitch corresponding to extracted pitch data and, more particularly, to an electronic stringed instrument such as an electronic guitar or a guitar synthesizer.

2. Description of the Related Art

In recent years, various types of electronic systems have been developed to extract pitch (fundamental frequency) data from a waveform signal generated in accordance with human varies and/or tones of acoustic musical instruments and to control a sound source constituted by an electronic circuit so as to artificially obtain an acoustic effect such as a musical tone.

The following prior arts disclose the above technique:

U.S. Pat. No. 4,117,757 (issued on Oct. 3, 1978), inventor: Akamatsu,

U.S. Pat. No. 4,606,255 (issued on Aug. 19, 1986), inventors: Hayashi et al.,

U.S. Pat. No. 4,633,748 (issued on Jan. 6, 1987), inventors: Takashima et al.,

U.S. Pat. No. 4,688,464 (issued on Aug. 25, 1987), inventors: Gibson et al.,

Japanese Patent Publication No. 57-37074 (published on Aug. 7, 1982), applicant: Roland Kabushiki Kaisha,

Japanese Patent Publication No. 57-58672 (published on Dec. 10, 1982), applicant: Roland Kabushiki Kaisha,

Japanese Patent Disclosure (Kokai) No. 55-55398 (disclosed on Apr. 23, 1980), applicant: TOSHIBA CORP.,

Japanese Patent Disclosure (Kokai) No. 55-87196 (disclosed on July 1, 1980), applicant: Nippon Gakki Co., Ltd.,

Japanese Patent Disclosure (Kokai) No. 55-159495 (disclosed on Dec. 11, 1980), applicant: Nippon Gakki Co., Ltd.,

Japanese Utility Model Disclosure (Kokai) No. 55-152597 (disclosed on Nov. 4, 1980), applicant: Nippon Gakki Co., Ltd.,

Japanese Utility Model Disclosure (Kokai) No. 55-162132 (disclosed on Nov. 20, 1980) applicant: Keio Giken Kogyo Kabushiki Kaisha,

Japanese Patent Publication No. 61-51793 (published on Nov. 16, 1986), applicant: Nippon Gakki Co., Ltd., and

Japanese Utility Model Publication No. 62-20871 (published on May 27, 1987), applicant: Fuji Roland Kabushiki Kaisha.

U.S. patent application disclosing a system relating to the present invention was filed by Uchiyama et al. as U.S. Ser. No. 112,780 on Oct. 22, 1987.

In these prior arts, in order to extract pitch data from an input waveform signal, a time interval between two positive peaks, between negative peaks, or between zero-crossings immediately after these peaks of the input waveform signal is measured. A circuit for detecting a peak is generally exemplified by an analog circuit including capacitors and resistors. It is often difficult to perform good peak detection of the input waveform signal of the musical instrument due to variations in circuit components, durability, and deteriorations over time. The peak detector comprises an analog system which requires a large number of circuit components, resulting in high cost. It is also inconvenient to realize easy element mounting. In particular, in an electronic musical instrument incorporating a sound source circuit, a mounting space must be minimized. In a conventional circuit arrangement, it is impossible or is very difficult to obtain a mounting space. When condition parameters are to be changed for pitch extraction, special circuits must be prepared every time the parameters are changed. Therefore, it is very difficult to change such parameters.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an apparatus for extracting a pitch data from an input waveform signal or an input apparatus for an electronic system for generating a musical tone corresponding to the pitch data, wherein a circuit arrangement is simple and inexpensive, and peak detection can be performed with high precision, and condition parameters can be easily changed regardless of variations in circuit components and deteriorations over time.

A major part of a circuit arrangement for extracting a pitch data from an input waveform signal is constituted by a digital system.

According to an aspect of the present invention, there is provided an input control apparatus for an electronic system, comprising:

means for converting an input waveform signal into a digital waveform signal A;

memory means for storing a digital waveform signal B;

means for reducing a value of the digital waveform signal B stored in said memory means at a predetermined rate;

means for comparing the digital waveform signal B stored in said memory means with the digital waveform signal A supplied from said converting means; and control means for causing said memory means to store the digital waveform signal A supplied from said converting means as the digital waveform signal B when said comparing means detects that the digital waveform signal A supplied from said converting means is larger than the digital waveform signal B stored in said memory means, and for inhibiting changing the digital waveform signal B stored said memory means with the digital waveform signal A when said comparing means detects that the digital signal A supplied from said converting means is smaller than the digital waveform signal B stored in said memory means,

wherein a peak timing of the input waveform signal is detected on the basis of a comparison output from said comparing means.

The present invention is applied to an electronic stringed instrument having a plurality of strings, and there is provided an input control apparatus for an electronic musical instrument of a type having a plurality of strings to extract a pitch from a vibration signal generated upon vibrations of the strings and electrically generate an acoustic signal having a frequency corresponding to the extracted pitch, comprising:

means for converting an input waveform signal into digital waveform signals Ai, where i corresponds to a string number of the strings;

memory means for storing digital waveform signals Bj, where j corresponds to the string number of the strings;

means for subtracting a predetermined value from the digital waveform signal Bj of each string stored in said memory means at a predetermined rate;

means for comparing the digital waveform signal Bj stored in said memory means with the digital waveform signal Ai supplied from said converting means in units of strings (i=j); and

control means for causing said memory means to store the digital waveform signal Ai supplied from said converting means as the corresponding digital waveform signal Bj (j=i) in said memory means when said comparing means detects that the digital waveform signal Ai supplied from said converting means is larger than the corresponding digital waveform signal Bj (j=i) stored in said memory means, and for inhibiting changing the digital waveform signal Bj stored the memory means with the digital waveform signal A when said comparing means detects that the digital waveform signal Ai supplied from said converting means is smaller than the corresponding digital waveform signal Bj (j=i) stored in said memory means,

wherein peak timings of the input waveform signals generated upon vibrations of the plurality of strings are detected on the basis of a comparison result from said comparing means.

By developing the above arrangement, positive and negative peaks of the input waveform signal generated by each string can be detected. In this case, positive digital waveform signals Bju and negative digital waveform signals BjD having the inverted polarity for the respective strings are stored in the memory means. The positive peak value is output without processing and the negative peak value is output after its polarity is inverted, thereby obtaining digital waveform signal Ai. Digital waveform signal Ai is compared with digital waveform signals Bju and BjD to detect both positive and negative peak timings.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features, and advantages of the present invention will be apparent from a preferred embodiment in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram showing an overall arrangement of an embodiment of the present invention;

FIGS. 2A and 2B are diagrams showing a detailed arrangement of a pitch extraction analog circuit in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the pitch extraction analog circuit;

FIG. 4 is a diagram showing a detailed arrangement of a log converter in FIG. 2B;

FIG. 5 is a graph for explaining characteristics of a log converter in FIG. 4;

FIG. 6 is a timing chart for explaining the operation of the pitch extraction analog circuit shown in FIGS. 2A and 2B;

FIGS. 7(a) and 7(b) are graphs for explaining the function of the log converter shown in FIG. 4;

FIG. 8 is a block diagram of a pitch extraction digital circuit shown in FIG. 1;

FIGS. 9(a) and 9(b) are a diagram and a waveform chart, respectively, of a peak detector shown in FIG. 8;

FIG. 10 is a diagram showing a detailed arrangement of the peak detector;

FIG. 11 is a timing chart showing the operation of the circuit in FIG. 10;

FIG. 12 is a diagram showing a detailed arrangement of a time constant conversion control circuit in FIG. 8;

FIG. 13 is a diagram showing a detailed arrangement of a zero-crossing time receiving circuit in FIG. 8;

FIG. 14 is a diagram showing a detailed arrangement of a peak value receiving circuit in FIG. 8;

FIG. 15 is a timing chart for explaining the operation of the circuit shown in FIG. 10;

FIG. 16 is a timing chart for explaining the operation of the time constant conversion control circuit in FIG. 12;

FIG. 17 is a timing chart, for explaining the operation of the cicuit shown in FIG. 13; and

FIGS. 18(a) and 18(b) are timing charts for explaining an operation of the embodiment in response to an input waveform signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. The present invention is applied to an electronic guitar but can also be applied to electronic musical instruments of other types or other electronic systems.

FIG. 1 is a block diagram showing an overall circuit arrangement. Pitch extraction analog circuit PA to be described in detail later is arranged for each of six strings which are kept taut on an electronic guitar body (not shown). Circuit PA inclues a hexa pickup for converting string vibrations into electrical signals and a converting means such as analog-to-digital converter A/D (to be described in detail later) for outputting zero-crossing signals Zi and waveform signals Wi (i=1 to 6) on the basis of outputs from the pickup and converting these signals into time-divisional serial zero-crossing signal ZCR and digital output (time-divisional waveform signal) D1.

Pitch extraction digital circuit PD will be described later. Digital circuit PD includes peak detector PEDT, time constant conversion control circuit TCC, peak value receiving circuit PVS, and zero-crossing time receiving circuit ZTS, as shown in FIG. 8. Digital circuit PD detects the positive or negative peak value on the basis of zero-crossing signals Zi, serial zero-crossing signal ZCR, and digital output D1, all of which are output from pitch extraction analog circuit PA, generates MAXI and MINI (I=1 to 6) and outputs interrupt signal INT at a zero-crossing to microcomputer MCP. In addition, pitch extraction digital circuit PD outputs time information and peak value information at the zero-crossing, and an instantaneous value of the input waveform signal to microcomputer MCP through bus BUS. Peak detector PEDT includes a circuit for subtracting previous peak values and holding a subtracted value.

Microcomputer MCP includes memories (e.g., a ROM and a RAM) and timer T and controls signals supplied to musical tone generator SOB. Generator SOB comprises sound source SS, digital-to-analog converter D/A, amplifier AMP, and loudspeaker SP and generates a musical tone having a pitch designated by a pitch designation signal for changing a frequency and controlled by the signals of note-on (tone generation) and note-off (muting) which are supplied from microcomputer MCP. Interface MIDI (Musical Instrument Digital Interface) is arranged between the input side of sound source SS and the microcomputer MCP. In response to address read signal AR, address decoder DCD outputs string number read signal RDI, time read signal RDj (j=1 to 6), and MAX and MIN peak read signals RDAI (I=1 to 12) to pitch extraction digital circuit PD.

FIGS. 2A and 2B are circuit diagrams showing a detailed arrangement of pitch extraction analog circuit PA in FIG. 1. Input waveform signals corresponding to the respective strings and output from the hexa pickup are supplied to input terminals 11 to 16 of low-pass filters (LPFs) 21 to 26, respectively. These signals are amplified, and their high-frequency components are removed, so that the fundamental waveforms are extracted. Since a frequency of an output tone of each string falls within a predetermined two-octave range, these LPFs have different cutoff frequencies in units of strings.

Outputs from low-pass filters 21 to 26, are supplied as waveform outputs W1 to W6. The outputs from the low-pass filters 21 to 26 are also input to zero-crossing comparators 31 to 36, respectively, and are compared with a reference signal, thereby generating zero-crossing signals Z1 to Z6.

Zero-crossing signals Z1 to Z6 are input to an input section of zero-crossing parallel-to-serial converter 4 comprising AND gates a1 to a6 and OR gate .phi.1. More specifically, signals Z1 to Z6 are respectively input to AND gates a1 to a6 which are sequentially enabled in response to pulses .phi.1 to .phi.6 (to be described later), so that signals Z1 to Z6 are converted into serial zero-crossing signal ZCR. In this case, converter 4 outputs serial zero-crossing signal ZCR of logic "1" if values of signals Z1 to Z6 are positive. However, converter 4 outputs serial zero-crossing signal ZCR of logic "0" if the values of signals Z1 to Z6 are negative.

Waveform outputs W1 to W6 from low-pass filters 21 to 26 are input to the input section of analog parallel-serial converter 5, i.e., analog gates g1 to g6. Analog gates g1 to g6 are sequentially enabled in response to pulses .phi.1 to .phi.6, so that outputs W1 to W6 are converted into an analog serial signal. In this case, gates g1 to to g6 are enabled when pulses .phi.1 to .phi.6 are set at high level. However, analog gates g1 to g6 are disabled when pulses .phi.1 to .phi.6 are set at low level. An output from converter 5 is input to inverting amplifier (OPl) 6 connected to resistors r1 and r2. The positive and negative waveforms are converted into positive waveforms. More specifically, serial zero-crossing signal ZCR from converter 4 is directly input to analog gate g7 and to the gate terminal of analog gate g8 through inverter il. An output from inverting amplifier 6 is input to the input terminal of analog gate g8. Therefore, the output from analog gate g8 always has a positive value. Analog gate g7 is enabled in response to serial zero-crossing signal ZCR of logic "1", and outputs from analog gates g1 to g6 are gated to the output terminal. Therefore, the output signals always have positive values.

Outputs from analog gates g7 and g8 are input to log converter 7. The waveform data is log-converted by log converter 7 into compressed data. Necessary memory bits are eliminated. An output from log converter 7 is converted into digital output D1 by analog-to-digital converter (to be referred to as an A/D converter hereinafter) 8 in accordance with a logical state of A/D conversion clock signal ADCK.

FIG. 3 is a timing chart for explaining the operation of pitch extraction analog circuit PA in FIG. 2. Sequential pulses .phi.1 to .phi.6 are output from timing generator TG (FIG. 8) (to be described later) and are generated in order upon every interval corresponding to two periods of A/D conversion clock signal ADCK. Serial zero-crossing signal ZCR generated in response pulses .phi.1 to .phi.6 represents a zero-crossing of each string. Digital output D1 represents peak values (the polarity is inverted to obtain a positive value) of each string. Digital output D1 is delayed by a conversion time of A/D converter 8 from sequential pulses .phi.1 to .phi.6. This delay time can be corrected in a manner to be described later. Referring to FIG. 3, reference symbols Q5 and M05 denote timing signals output from pitch extraction digital circuit PD shown in FIG. 8, and functions of these signals will be described later.

FIG. 4 is a circuit diagram showing a detailed arrangement of log converter 7 in pitch extraction analog circuit PA shown in FIGS. 2A and 2B. Log converter 7 comprises a four-polygonal approximation log converter but is not limited thereto.

Log converter 7 comprises inverting amplifiers OP3 and OP4, transistors Tl, T2, and T3, and resistors R0, RO, Rl, R2, R3, R4, R, R, R/2, and R/4. Resistances of resistors R2 to R4 are determined to obtain voltage VOUT below:

R2=(1/2)VDD-0.6v

R3=(3/4)VDD-0.6v

R4=(7/8)VDD-0.6v.

With this arrangement,

(1) If condition VOUT <(1/2)VDD is established, transistors T1 to T3 are kept off. In this case, gain A can be calculated to be 4 according to the following equation:

A=VOUT/VIN=R/(R/4)=4.

(2) If condition (1/2)VDD<VOUT<(3/4)VDD is established, transistors T2 and T3 are kept off. However, since the emitter voltage vs. base voltage of transistor T1 exceeds -0.6 v, transistor T1 is turned on. Most of the emitter current flows in the collector. For this reason, a feedback resistance of second inverting amplifier OP4 is given as R/2. Gain A is reduced into 1/2 that of case (1), i.e., 2 as follows:

A=[1/(1/R+1/R)]/(R/4)=2.

(3) If condition (3/4)VDD<VOUT<(7/8)VDD is established, transistors T1 and T2 are turned on while transistor T3 is kept off. In this case, gain A can be calculated to be 1 according to the following equation:

A=[1/(1/R+1/R+2/R)]/(R/4)=1.

(4) If condition (7/8)VDD<VOUT is established, transistors T1 to T3 are turned on. Gain A can be calculated to be 0.5 according to the following equation:

A=[1/(1/R+1/R+2/R+4/R)]/(R/4)=0.5.

FIG. 5 is a graph of characteristics showing the relationship between input voltage VIN and output voltage VOUT in log converter 7 arranged as shown in FIG. 4.

FIG. 6 is a timing chart showing sequential pulse .phi.1, waveform output W1, input voltage VIN of log converter 7, output voltage VOUT, and serial zero-crossing signal ZCR in the arrangement of FIGS. 2A and 2B when the first string is picked. As is apparent from FIG. 6, data is log-compressed by log converter 7 to reduce the number of bits.

FIGS. 7(a) and 7(a) show string vibration envelopes before and after conversion in log converter 7. When the string vibration envelope shown in FIG. 7(a) is input to log converter 7, the envelope shown in FIG. 7(b) can be obtained. Attention should be paid for a note-on time. When the waveform shown in FIG. 7(a) is converted by A/D converter 8 to obtain a note-off region having a value below a given threshold value, the note-on time is short. However, when a note-off operation is performed with the threshold value after the log conversion, as shown in FIG. 7(b), the note-on time can be prolonged. Therefore, tone generation control can cope with an abrupt attenuation in string vibration in this embodiment.

Log converter 7 is not arranged in pitch extraction digital circuit PD, i.e., log conversion is not performed in the digital circuit. Log converter 7 is arranged in pitch extraction analog circuit PA to perform log conversion in the analog circuit due to the following reason. For example, assume that A/D converter 8 comprises an 8-bit converter and a note-off threshold value in FIG. 7(b) is 3. In order to prolong the note-on time in FIG. 7(a) as in FIG. 7(b), a threshold value must be set to be 3/4=0.75. This threshold value cannot be set without replacing the A/D converter. It is possible to perform the above setting if a 10-bit converter having the number of bits larger than the currently used converter by 2 bits is used. However, a circuit arrangement becomes expensive by an increase in cost of the converter.

FIG. 8 is a schematic block diagram of pitch extraction digital circuit PD in FIG. 1. Pitch extraction digital circuit PD comprises peak detector PEDT for receiving serial zero-crossing signal ZCR and detecting MAX and MIN peaks, time constant conversion control circuit TCC for converting a time constant of peak detector PEDT, zero-crossing time receiving circuit ZTS, peak value receiving circuit PVS, timing generator TG for generating various timing signals, e.g., sequential pulses .phi.1 to .phi.6, and timing signals ADCK, Q5, M05, and MC. These components will be described in detail below.

FIGS. 9(a) and 9(b) are a schematic diagram and a waveform chart, respectively, for explaining peak detector PEDT. More specifically, FIG. (a) is a circuit diagram of a positive side of the vibrations of one string. In principle, 12 circuits in FIG. 9(a) are required. In practice, however, 12 circuits need not be arranged to process vibrations of a plurality of strings according to a time-divisional technique. This technique will be described in detail later with reference to FIG. 10. A log-converted waveform signal from log converter 7 in pitch extraction analog circuit PA is input to A/D converter 8 and is converted into digital output D1 every time A/D conversion clock signal ADCK from timing generator TG in FIG. 8 is input. Digital output D1 is input to one input terminal of comparator 42 (this input value is defined as A). A/D converter 8 is identical with the one shown in FIG. 2. Its characteristics are also illustrated in FIG. (a) for illustrative convenience.

A storage value from memory 43 is input to the other input terminal B of comparator 42 (this value is defined as B). If A>B, comparator 42 outputs a signal of "H" level, i.e., logic "1". Otherwise, comparator 42 outputs a signal of "L" level, i.e., logic "0 ". Memory 43 can store an output from A/D converter 8 or an output from subtracter 44. Output selection is performed by data selection switch 46. That is, if the output from comparator 42 is set at logic "1", switch 46 is switched to the "1" side, so that the output from A/D converter 8 is loaded in memory 43. However, if the output from comparator 46 is set at logic "0", switch 46 is switched to the "0" side, so that the output from subtracter 44 is loaded in memory 43.

The storage value from memory 43 is directly input to one input terminal A of subtracter 44. A value obtained by multiplying the storage value of memory 43 with 1/n through, e.g., shifter 45 is input to the other input terminal B of subtracter 44. Subtracter 44 calculates a difference (A-B), and the difference appears at output terminal S. Shifter 45 subtracts, e.g., a 1/256 value of the storage value from the storage value of memory 43. Therefore, subtracter 44 performs the following calculation:

S=A-B=A-(1/256).multidot.A.

Value B may be a constant independently of value A. However, according to the above equation, S is exponentially changed, and good characteristics can be obtained.

the above arrangement, when the waveform signal (input to comparator 42) shown in FIG. 9(b) is input to comparator 42, a MAX peak detection signal shown in FIG. 9(b) is output from comparator 42. That is, when the out.put from A/D converter 8 which serves as an input to comparator 42 rises, the output from comparator 42 rises and goes to logic "1". When the input to comparator 42 is smaller than the storage value of memory 43, the output from comparator 42 falls and goes to logic "0". An output from A/D converter 8 advances to a negative half wave period and then toward the positive side. When the output from A/D converter 8 reaches the storage value of memory 43, the output from comparator 42 rises and goes to logic "1". When the output from A/D converter 8 reaches the MAX peak, the output from comparator 42 falls and goes to logic "0". In this manner, the MAX peak of comparator 42 can be detected. A divider may be used in place of shifter 45.

FIGS. 18(a) and 18(b) are timing charts for explaining the operation of the circuit in FIG. 9. More specifically, FIG. 18(a) shows the relationship between the peak and zero-crossing when the input waveform signal is large. FIG. 18(b) shows the relationship between the peak and zero-crossing when the input waveform signal is small. Peak and zero-crossing detection can be performed even if the magnitude of the input waveform signal is the one shown in FIG. 18(a) or 18(b).

FIG. 18(a) shows a waveform including second harmonic overtones. According to this embodiment, a time interval between zero-crossings immediately after the peaks can be measured, as will be apparent from a subsequent description. Therefore, the harmonic overtones are eliminated and period detection can be performed (T in FIG. 18(a) is the period).

Even in the waveform shown in FIG. 18(b), a reduction rate of memory 43 must be taken into consideration in order to eliminate harmonic overtones as in FIG. 18 (a). If the input waveform is large, processing must be fast; and if the input waveform is small, processing must be slow. In this embodiment, by attenuating the contents of memory 43 according to an exponential curve, good harmonic overtone elimination can be performed in both the cases in FIGS. 18(a) and 18(b).

FIG. 10 shows a detailed circuit arrangement of peak detector PEDT shown in FIG. 8. A storage value stored in memory 43, e.g., twelve 12-bit shift registers (6[strings].times.2[(maximum (positive) or minimum (negative) peak holding)]=12) is input to gate GATEI, and gate GATEI is enabled or disabled in response to control signal PR from gate control circuit GATEC. An output from gate GATEl is input to shifter 45, and an output from shifter 45 is input to one input terminal of subtracter 44. The storage value from memory 43 is directly input to the other input terminal of subtracter 44. Timing signal M05 from timing generator TG in FIG. 8 is input to clock terminal CK of memory 43. The contents of memory 43 are shifted to the right in response to the leading edge of timing signal M05. Shifter 45 performs shifting at a rate of, e.g., 1/256 (8-bit shifting) or 1/16 (4-bit shifting). Switching between 8- and 4-bit shifting is controlled by time constant change signal GX.

Gate control circuit GATEC comprises 2-bit counter COW1, OR gates OR1 to OR4, and AND gates a10 and all. Since sequential pulse .phi.1 is input to the input terminal of counter COW1, sequential pulses .phi.1 and .phi.2 input to OR gate OR2 are directly gated therethrough and are supplied as control signal PR, as shown in the timing chart in FIG. 11. Similarly, since pulses .phi.3 and .phi.4 are output through AND gate all, these pulses are output as one control signal PR per two cycles, i.e., during the period in which the QA output is set at logic "1". Similarly, pulses .phi.5 and .phi.6 are output as one control signal PR per four cycles, i.e., when QA and QB outputs are simultaneously set at logic "1". This control signal serves as a gate enable signal for gate GATE1. A subtraction operation for the first and second strings is performed by subtracter 44 every cycle. A subtraction operation for the third and fourth strings is performed every other cycle. A subtraction operation for the fifth and sixth strings is performed in every fourth cycle due to the following reason. The string vibration of the high-pitch strings (i.e., the first string side) tends to be abruptly attenuated. The string vibration of the low-pitch strings (i.e., sixth string side) tends to be slowly attenuated.

The reduction rate of the first- and second-string contents in memory 43 is large, while the reduction rate of the fifth- and sixth-string contents in memory 43 is small. The reduction rate of the third- and fourth-string contents in memory 43 is intermediate. The rate may be changed in units of strings. Alternatively, The change in rate may be performed for string groups, or for a group of first to third strings and a group of fourth to sixth strings. An output from gate GATEl enabled at high level of control signal PR, that is, an output read out from memory 43, is supplied to shifter 45. The shift amount of shifter 45 can be changed by time constant change signal GX, as described above. Subtracter 44 performs the following operations:

If time constant change signal GX is set at logic "0", the following operation is performed:

S=R(1-1/256)-1.

However, if time constant change signal GX is set at logic "1", the following operation is performed:

S=R(1-1/16)-1.

Subtracter 44 includes carry-in input terminal CIN. Therefore, an output can be reduced even if the other input terminal, i.e., the B input side, of subtracter 44 is set at logic "0".

If the operation of subtracter 44 is strictly synchronized with control signal PR from gate control circuit GATEC, control signal PR is supplied to carry-in input terminal CIN. With this arrangement, "-1" calculations in the above equations are performed whenever the content of memory 43 is supplied to subtracter 44 through gate GATEI and shifter 45.

When a signal of logic "1" is supplied from OR gate OR5, the upper eight bits of an output from subtracter 44 are input to memory 43 through data selection switch 46. The lower four bits are input to memory 43 through AND gates a7 to a10. When a signal of logic "0" is supplied from OR gate OR5, new digital output D1 from A/D converter 8 is supplied to memory 43 through data selection switch 46 due to the following reason. An output from OR gate OR5 is input to input terminal SE of data selection switch 46 and AND gates a7 to a10.

Digital output D1 from A/D converter 8 is input to one input terminal A of comparator 42. A storage value (upper eight bits) from memory 43 is input to the other input terminal B of comparator 42. Digital output D1 input to one input terminal A of comparator 44 is also input to the other input terminal of data selection switch 46. An output from comparator 42 is input to one input terminal of OR gate OR5 through inverter IVl. An output from exclusive OR gate EX is input to the other input terminal of OR gate OR5. Serial zero-crossing signal ZCR from pitch extraction analog circuit PA and AD conversion timing signal ADCK from timing generator TG are input to the input terminals of exclusive OR gate EX. Therefore, when signal ZCR coincides with signal ADCK, an output from exclusive OR gate EX is set at logic "0".

When the output from exclusive OR gate EX is set at logic "0", i.e., when signal ZCR coincides with signal ADCK a new digital output D1 exceeds a storage value of memory 43, an output from OR gate OR5 is set at logic "0". As described above, new digital output D1 is loaded in memory 43 through data selection switch 46 (in this case, lower four bits are all "0"s) When the output from exclusive OR gate EX is set at logic "1", i.e., when signal ZCR does not coincide with signal ADCK, an output from OR gate OR5 is set at logic "1". The output from subtracter 44 is input to memory 43, but new digital output D1 is not input thereto. Similarly, even if signal ZCR coincides with signal ADCK, if condition A<B is established in comparator 42, an output from OR gate OR5 is set at logic "1 ". Therefore, new digital output D1 is not supplied to memory 43.

Serial zero-crossing signal ZCR, the output from comparator 42, and timing signals Q5 and ADCK from timing generator TG are respectively input to AND gates Al to A4 in the serial-to-parallel converter. Outputs from AND gates Al to A4 and sequential pulses .phi.1, .phi.2,... .phi.6 from timing generator TG are supplied to AND gates a11max, a12max,... a62max and a11min, a12min,... a62min. Outputs from AND gates a11max, a11min,... a62min are input to flip-flops FFla, FFlb,... FF6b and converted into parallel peak signals MAXI and MINI (I=1 to 6) When A/D conversion clock signal ADCK is set at logic "1", outputs from up (positive) AND gates Al and A2 are set at logic "1". However, if A/D conversion clock signal ADCK is set at logic "0", outputs from down (negative) AND gates A3 and A4 are set at logic "1".

When serial zero-crossing signal ZCR is set at logic "1" and the output from comparator 42 is set at logic "0", AND gate A1 supplies a "1" output to AND gate aI1max (I=1 to 6) to set outputs of MAXI (I=1 to 6) to be low level while A/D conversion clock signals ADCK and Q5 are set at logic "1". Therefore, one of flip-flops FF1a to FF6a is reset.

Similarly, AND gate A2 suppli