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Description  |
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A number of digital systems include specialized separate devices devoted
respectively either to signal processing, or to system's management.
Signal processors require a fairly large amount of computing power, while
their memory requirements are not significant. For system's managing
devices, the requirements are reversed.
TECHNICAL BACKGROUND
The above statements may be illustrated by way of an example, e.g. a
digital voice and data transmission system. Assume a number of local voice
terminals are to be attached to a digital transmission network. Each voice
signal needs to be processed. It is first converted into digital form
prior to being transmitted over the network. For that purpose the outgoing
voice signal is submitted to more or less complex operations, designed to
get the best voice coding quality, e.g. in terms of quantizing noise for a
given bit rate. The processing workload required is fairly high, but it
mainly consists in repetitive computing operations on the same data. For
instance, the voice signal is processed by segments each 20 ms long. Each
voice segment is sampled at, say, 8 KHz, and thus provides a block of 160
samples. Each sample is coded in PCM with 8 bits. Then each 20 ms, the
whole block of PCM coded samples are reprocessed to lower the final number
of bits required to code the same samples, while keeping the coding
quality at the highest possible level.
A number of coders have been proposed to perform the above coding
operations. One may refer for instance to European Pat. No. 0002998 (U.S.
Pat. No. 4,216,354) to the same assignee for further details on these
coders. But, with any of these coders, the rate of input/output operations
is fairly limited (e.g. one operation per 20 ms) and requires little data
transfers when compared with the processing workload required for
compression and related signal processing operations.
A primary reason for doing the compression operations has to do with the
high cost of transmission channels. Important savings can be made by
compressing voice signal and concentrating (e.g. multiplexing) as many
voices as possible on the same transmission channel. Consequently several
voice coders can be attached to the same channel, through a Control Unit
made to manage the interface operations between a set of Voice terminals
(coders) and a common channel.
For the above cited coder example, for instance, the Control Unit would
have to control the coders I/O operations, for transferring each 20 ms the
bits derived from a voice segment processed by each of the signal
processors attached to the same Control Unit.
These transfers could be made using different methods. Some of these
methods would be fairly rigid, therefore not allow easy reconfiguration of
the network in the field.
A system architecture is proposed here, which conveniently combines hard
and soft devices enabling program parametering of the system to adjust to
the specific system configuration required.
This architecture is not however limited to voice multiplexing operations.
It may be generically used in all machines where several processors execute
Tasks which may be included in a fixed time frame.
The expression "signal processor" will thus be used in this application for
this kind of processor, even if the executed task is not related to signal
processing.
The above will be made apparent from the following description, made with
reference to the attached figures.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 is a block diagram of a system incorporating the invention.
FIG. 2 represents a time diagram.
FIG. 3 is a block-diagram illustrating the invention.
FIG. 4 is a circuit used in the invention, and
FIG. 5 is a timing diagram.
DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
FIG. 1 is a block diagram illustrating the basic architecture of a system
made according to this invention. Each one of a set of n Voice Terminal
Units is attached through an interface (VTU1 INT) through (VTUn INT) to a
converter device (A/D, D/A) for performing analog-to-digital and
digital-to-analog conversion respectively. In the A/D for instance, the
voice signal, limited to the telephone frequency bandwidth 300-3400 Hz, is
sampled at 8 KHz, and coded in PCM .mu.law with 8 bits per sample. The
voice signal is then considered by segments 20 ms long and each block of
samples is recoded to improve the signal to noise ratio of the coded
signal while keeping the bit rate required to a predetermined minimal
level. This target may be reached by processing the PCM coded signal in a
signal processor using BCPCM techniques combined with split band and
dynamic allocation of coding resources, as disclosed in the above
mentioned patent. According to the BCPCM technique, the 8-bit PCM coded
samples are processed by blocks of samples wherefrom a characteristic term
is derived (e.g. the largest sample) and then the samples of the block are
requantized relative to the characteristic term. In addition, in the above
mentioned patent, the voice signal is also split into several (p)
subbands, which means that each original block provides p different
blocks. The requantizing is performed within each subband with the
requantizing number of bits being dynamically assigned to the subband.
At the end of this signal processing, each signal processor provides a
block of bits resulting from the coding of a voice segment 20 ms long.
Every 20 ms, then, the transfer of a block of bits should be made from each
operating signal processor (1 through n) to the Unit Processor 20 and vice
versa. These transfers are made through a Signal Processor Adapter (SPA)
22.
The Unit Processor 20, is made to manage the transfer of voice originating
bits, and/or service bits, such as telephone signaling, to and from a line
interface through a High Speed Communication Adapter (HSCA) 26.
The data exchanges between the Unit Processor 20 and the n individual
Signal Processors is made on a time sharing basis as schematically
represented in FIG. 2.
The transfer between a given Signal Processor "i" and the Unit Processor,
is made active during a time interval Di, and inactive during a time
interval Pi. All the n Signal Processors should then be scanned within a
time interval equal to the time involved in processing one block of
samples within a Signal Processor, i.e. 20 ms.
The synchronization of the system is achieved by a logic system which gives
a "Start process" and a "Data exchange" order to the Unit Processor and to
the n different Signal Processors. The data exchanges are performed
through a single data exchange bus (DE Bus) on which contention is avoided
due to the above mentioned time distribution. Such a non-contention mode
of operation, also enables simplifying both system hardware and software.
In summary, once one has defined the number of Voice Terminal Units, for
instance "n", to be served by a given Unit Processor, and the voice
segment time length T, then the time slot Dn is set equal to T/n. In fact,
one may also choose to process the exchange of more than one voice segment
at a time. For instance assuming two voice segments are packed together,
then Dn=2T/n. And so on.
Also, should the number of Voice Units or their operating cycles require
adjustment in the field, then, the operator could adjust the system to the
required Dn.
In addition, to make the system operate even more smoothly, a so called
"ping-pong" technique is implemented as schematically represented in FIG.
3. The data transfers from and to the signal processor are performed
through double-buffering means (R1 and R2). Each pair of buffers is made
to operate in a ping-pong mode, which means, alternately. For instance,
assume at a given time slot Di, the A/D Buffer Register R1 is being loaded
with PCM coded samples, during the same time slot, the PCM coded samples
to be recoded using BCPCM and compression techniques as disclosed in the
above mentioned patent, are fetched out of A/D Buffer Register R2 by the
Signal processor.
The same operating process applies to the D/A Buffers and to the I/O means
connected to the D.E. Bus, as well.
The system synchronization is achieved by the Signal Processor adapter
(SPA) 22, normally and regularly requesting a Unit Processor interrupt
every T/n second and also feeding clock signals to the signal processors
SP1-SPn to start its operation.
Assuming the Voice signal is first to be sampled at 8 KHz and coded in PCM
with 8 bits per sample, then every 125 microsecond on an interrupt mode,
each signal processor SP1-SPn reads a byte (a sample) out of its
corresponding A/D PCM converter and feeds it into one of its A/D buffers
R1 or R2 alternately. At the same time, the Signal Processor reads a byte
out of one of its D/A buffers R1 or R2 and feeds it into the D/A PCM
converter.
The conversion from A/D PCM to compressed coding is performed over a block
of say 160 PCM coded samples representing a segment of voice signal 20 ms
long. The cycle is started by a special interrupt to the Signal Processor.
Obviously, when the transfer from/to A/D and D/A buffers affects the ping
(R1) buffers, then the compression/decompression is performed over pong
(R2) buffers.
In addition, assume n=8, and each voice segments is T=20 ms long, then T
should be divided into n=8 slots each 20/8=2.5 ms long, thus Di=2.5 ms and
Pi=17.5 ms.
The system synchronization is achieved by SPA22 through use of a SYSTEM
SYNCHRONIZATION REGISTER (SSR). The System Synchronization Register of
FIG. 4 is a 8-bit counter which may be preset by program to define the
maximum count cycle. In practice said counter is doubled for buffering
purposes (see SSR write and SSR Read).
The counter is divided into two parts. The four HIGH order bits will
determine the ping-pong bit, which controls two consecutive signal
processing cycles, and the start cycle flag, for each signal processor by
raising the level of one out of eight outputs labeled SCF TO SP1 through
SCF TO SP8 upon the decoding of the contents of bit positions 1-3 of SSR
Read.
The four low order bit positions are initialized by the Unit Processor to
fit with the number of PCM coded samples processed by the Signal
Processor. The input clock for this counter has been made to be a 500
microseconds clock the cycle of which corresponds to four PCM coded
samples.
If the counter is initialized by the Unit Processor to count "p" clock
periods, then, the number of samples processed by each signal processor
for analysis or compression and synthesis or decompression purposes will
be:
N=4.times.p.times.8=32 p.
A flexibility of the system may be achieved through the selection of the
"p" value.
The multiplication by four is made through hardware.
If the initial time of a total synchronization cycle is TO and if the SSR
has been initialized to count p clock periods, the following table shows
the details of the events occurring during the succeding synchronization
cycle.
__________________________________________________________________________
UC SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
P/P
__________________________________________________________________________
TO * SCF 0
TO + p .times. 500 .mu.s
* SCF 0
TO + 2 .times. p .times. 500 .mu.s
* SCF 0
TO + 3 .times. p .times. 500 .mu.s
* SCF 0
TO + 4 .times. p .times. 500 .mu.s
* SCF 0
TO + 5 .times. p .times. 500 .mu.s
* SCF 0
TO + 6 .times. p .times. 500 .mu.s
* SCF 0
TO + 7 .times. p .times. 500 .mu.s
* SCF
0
TO + 8 .times. p .times. 500 .mu.s
* SCF 1
TO + 9 .times. p .times. 500 .mu.s
* SCF 1
TO + 10 .times. p .times. 500 .mu.s
* SCF 1
TO + 11 .times. p .times. 500 .mu.s
* SCF 1
TO + 12 .times. p .times. 500 .mu.s
* SCF 1
TO + 13 .times. p .times. 500 .mu.s
* SCF 1
TO + 14 .times. p .times. 500 .mu.s
* SCF 1
TO + 15 .times. p .times. 500 .mu.s
* SCF
1
__________________________________________________________________________
The asterisk indicate an interrupt requested to the Unit Processor 22 (UP)
through the carry bit of upper part of SSR Read (see FIG. 4) section. The
Start Cycle Flag (SCF) position indicates which signal processor starts a
new signal processing cycle after transferring one block of samples to
coding buffer and from decoding buffer R1 or R2 (depending upon the
ping-pong P/P bit value).
In other words, the above table indications show the read/write data
exchange from/to Unit Processor and from/to a Signal Processor.
The interrupts are synchronized as indicated in FIG. 5. All the signal
processors will receive regularly the normal 125 microseconds interrupt.
Indications are given to each Signal Processor through the contents of a
status byte location in their Input/Output memory space. This space is
made to store a start cycle flag SCF and a ping-pong bit. In fact, the
start cycle flag will be up for a signal processor, 395 microseconds after
the raising of the related interrupt to up. The start cycle flag SCF will
be up for each signal processor, only once every N.times.125 microseconds.
This indication, together with the ping-pong bit value being at a one
binary value, will start the initialization of a new signal processing
cycle within the signal processor. The start cycle flag SCF timing chart
is represented in FIG. 5, with an emphasized portion showing the relative
phase of the 125 microseconds interrupt, with respect to the corresponding
Start Cycle Flag. The SCF signal will automatically go down to zero level
105.4 microseconds after the interrupt request has been made to the
corresponding signal processor SP.
In addition, the SSR counting can be inhibited by setting a CONTROL
REGISTER bit .phi. to zero level and thus inhibit Unit Processor
interrupts as well as start cycle flag generation.
* * * * *
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