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BACKGROUND OF THE INVENTION
The invention relates to a digital data error block detection and display
device, and more particularly, to a digital data error block detection and
display device for a playback unit for still pictures with sound.
SUMMARY OF THE INVENTION
The invention provides a digital data error block detection and display
.device for detecting and displaying digital data error blocks, including:
means for checking whether a device debug mode has been selected, means
for detecting data errors in digital data while transmitting this data,
means for terminating digital data transmission when a data error has been
detected, means for identifying a digital data block in which an error has
been detected, means for deciding whether digital data including the
digital data block in which data error has been detected is to be
transmitted, and means for continuing transmission of the digital data
including the digital data block in which data error was detected.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows block divisioning of one field of an image frame;
FIGS. 2A and 2B show expanded views of the V blanking interval of the video
format signal;
FIG. 3 is a diagram showing numbers of scanning lines corresponding to the
block in FIG. 1;
FIG. 4 schematically illustrates the format of a horizontal scanning line;
FIGS. 5A to 5E, 6 and 7 show instances of insertion of digital data and
picture information;
FIG. 8 is a block diagram of a circuit which operates in accordance with a
video format signal recording method of the invention;
FIG. 9 is a block diagram showing an example of a playback circuit;
FIG. 10 gives an example of a field SYNC waveform for a block a;
FIG. 11 shows an example of the waveform for a block c containing digital
data corresponding to 1H;
FIG. 12 shows another example of a playback circuit;
FIG. 13 is a circuit diagram of an example of a data synchronizing detector
used in the circuit of FIG. 12;
FIG. 14, is a diagram of an example of the control data;
FIG. 15 is a block diagram of another example of a playback circuit;
FIG. 16 is a timing chart for the playback circuit of FIG. 15;
FIG. 17 shows yet another example of a playback circuit;
FIG. 18 shows an example of the video software used with the invention;
FIG. 19 depicts a further example of a playback circuit;
FIG. 20 provides another example of the video software;
FIG. 21 is a block diagram of another example of a playback circuit;
FIG. 22 indicates another example of control data;
FIG. 23 is a block diagram of a yet further example of a playback circuit;
FIG. 24 is a diagram of another example of video software;
FIG. 25 shows the correspondence between a block c and data identification
codes;
FIG. 26 shows block diagram of still another example of a playback circuit;
FIGS. 27A to 27E indicate a further example of video software;
FIGS. 28A to 28C show arrangements of digital data;
FIGS. 29 and 30 show examples of control data;
FIG. 31 is a timing chart for playback system operations corresponding to
video software;
FIG. 32 is a block diagram of another example of a playback circuit; and
FIG. 33 is a flowchart describing the operations of the digital data error
block detection and display device of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The invention will now be described in detail on the basis of an example.
In FIG. 1, the number of horizontal scanning lines (in the available
picture area) for a signal corresponding to one field of a video frame is
divided arbitrarily into blocks a, b, c, and Q. Blocks a, b, and c are
composed of an integral number of horizontal scanning lines. The number of
scanning lines in c is evenly divisible by an integer x so that m=c/x
where m is an integer. Accordingly, c is made up of units of m scanning
lines each and can be divided into x sub blocks c1-c.sub.x. Q may be but
need not be an integer.
FIGS. 2A and 2B show, parts of video format signals in FIG. 1. FIG. 2A
shows a waveform corresponding to recording of picture data in blocks c
and Q. FIG. 2B gives an example of a waveform where digital data is
recorded in block c.
FIG. 3 provides concrete numeric data relating to the example of the
division of scanning lines into blocks a, b, c, and Q for the case of an
NTSC signal. Here, of the total of 262.5 scanning lines per field, 241.5
are treated as effective scanning lines. Blocks a and b are assumed to lie
outside the visible range on the TV monitor screen. In this example, a =1,
b =4, c =234, x =9, m =26 and Q =2.5. Interleaving is employed to avoid
error concentration due to drop-out, etc., when digital data is inserted
in blocks b and c. Correction codes are introduced to enable detection as
well as correction of errors. In this example, block b includes divisions
capable of independent interleaving and error correction. Similarly,
c.sub.1 -c.sub.x in block c are made capable of independent interleaving
and error correction.
In the example shown in FIG. 4, digital data is inserted on a horizontal
scanning line. The data transmission rate is 408 f.sub.H (where f.sub.H
represents the horizontal scanning frequency). A clock run-in signal, that
is, a clock synchronization signal, is inserted before the digital data.
Following this signal, a data synchronizing signal consisting of a few
bits is introduced for data synchronization. This data synchronizing
signal is followed by the data word and/or error detection and correction
code.
FIGS. 5A to 5E show different recording modes. FIG. 5A shows picture data
only inserted in blocks c and Q. Since blocks a and b are outside the
visible range, c and Q are displayed as ordinary TV images. FIG. 5B shows
block c with only digital data inserted therein. FIG. 5C shows block c
divided into 9 subblocks with digital data inserted into c.sub.1, c.sub.2,
c.sub.8, and c.sub.9 and picture data inserted into c.sub.3 -c.sub.7. In
the example of FIG. 5D, digital data is inserted into subblocks c.sub.1
and c.sub.2 and picture data into c.sub.3 -c.sub.9. In FIG. 5E, picture
data is inserted into subblocks c.sub.1 -c.sub.7 and digital data into
c.sub.8 and c.sub.9.
In FIG. 6, the frames (fields) of block c into which digital data is
inserted continue over period A only. The number of such frames may range
from a minimum of 3 to 4 to a maximum of 30 to 40 depending upon the
quantity of data required. During period B following A, block c is filled
almost completely with picture data. The picture data inserted normally
corresponds to the data in period A. As a result, the data may be
constituted by two pictures, pictures fed a frame at a time, or moving
pictures. Furthermore, the same image may be recorded over several frames
to avoid crosstalk of pictures between frames even in the case of still
pictures.
In the example shown in FIG. 7, a few to several frames of block c continue
over period A, digital data being inserted in subframes c.sub.1 and
c.sub.9, and picture data in c.sub.2 to c.sub.8. This is followed by
period B where picture data only is inserted in block b. In this case,
during period A, only part of the screen will contain the picture, but the
image will not be discontinuous.
FIG. 8 is a block diagram of a recording circuit which operates in
accordance with the recording method of this invention and which produces
video format signals. Analog audio signals are converted into digital
signals by A/D converter 80. For time-axis compression, the digital signal
is stored in buffer memory 81 at a sampling frequency of f.sub.1 (R). The
contents of memory 81 are read out at a frequency f.sub.2 (W) which is
larger than f.sub.1 (R). The control signal serving as the control data is
made up of the clock line signal and data synchronizing signal earlier
mentioned, and also the respective block data items, block capacities, and
the respective processing data items needed to regenerate the data. The
video signal, the digital data signal including the time-axis compressed
audio data in buffer memory 81, and the control data are fed to switching
circuit 82. Control over the selection operation of switching circuit 82
is performed by timing signal generator 83. Timing signal generator 83
also controls writing and reading for memory 81. An internal transmitter
in timing signal generator 83 is synchronized with the synchronizing
signal for the input video signals. This generator generates different
timing signals in response to control, signals supplied from the outside.
The video format signal to be recorded is obtained from the output of
switching circuit 82.
FIG. 9 provides a simplified block diagram of a general playback unit for
reproducing still picture signals with audio data. The playback video
format signals are separated by signal separator 1 into synchronizing
signals and digital data. The digital data is then further separated into
audio and control data. In response to the synchronizing signals, timing
signal generator 2 generates timing signals including a write pulse
f.sub.2 (W) and a read pulse f.sub.1 (R). Detection and correction of
control data errors are performed by corrector 4. After correction, the
control data is decoded by control code decoder 6 and applied to system
control generator 7. The digital data is written by pulse f.sub.2 (W) into
the memory via corrector 3 and is read from the memory with pulse f.sub.1
(R) for time-axis expansion. The system may be configured so as to have
the digital data errors corrected after time-axis expansion. The
time-axis-expanded digital data is converted into corresponding analog
data by digital-analog converter 9 to produce the playback audio signal.
In response to the control instructions decoded by control decoder 6,
various control signals are generated by system control generator 7. This
playback video signal is derived via screen processor 8 operating in
response to a specific control signal. The operation consists in, for
example, processing a block with digital data as a black level block and
applying the same as an output. As mentioned above, the video disk play
(VDP) playback control signals are derived from the player controller 10
to effect control for stop or run (play) operation.
It has already been mentioned in the context of FIG. 1 that several
combinations of, respectively, clock synchronizing signals, clock line
signals for data synchronization, and data with data synchronizing signals
are inserted in horizontal scanning lines in an initial block a of a
field. This signal establishes synchronization between the clocks and data
words at the start of respective fields. Block a is referred to as a field
SYNC block. Details of the horizontal scanning line 1H of this block
appear in FIG. 10.
The data transmission rate is 408f.sub.H, with no digital data being
inserted at the 64th bit from the trailing edge of the H SYNC pulse. For
field SYNC serial data, 320 bits are used. The 320 bits are further
divided into 10 units of 32 bits each, each of these units including,
respectively, a clock and a data synchronizing signal. Of the 32 bits, 24
bits represent the clock run-in signal, that is, 12 cycles of a pattern of
1010... 10 followed by eight bits, 111000100, representing the data
synchronizing signal. Ten of this 32 bit data, composed of these 24 bits
plus eight bits, are inserted. A field equivalent to 24 bits is used as a
front porch.
In this example, the above signal array is inserted at the 22nd H, a being
equal to 1. In block b, various control signals corresponding to the data
contained in block c are inserted. When digital data is inserted in blocks
b and c, the effective data will consist of 320 bits as in the case of the
field SYNC (FIG. 11). There are 64 bits from H SYNC to the beginning of
the serial-data, front porch corresponding to 24 bits. This is exactly
like the field SYNC shown in FIG. 10. Again, the 320 bits include 24 bits
at the beginning of the serial data, 12 cycles of the clock run-in signal,
and, following these, a data synchronizing signal of eight bits. The
remaining 288 bits are divided into 36 units of eight bits (1 byte) each.
Furthermore, in accordance with this invention, block b is assigned to 4H.
In other words, the control signals for, respectively, 23H, 24H, 25H, and
26H are recorded here. Also, the block b data is arranged in eight bit (1
byte) units so as to facilitate interleaving and error correction. To
record digital data in block c, it is assigned to 26H. Digital data can be
recorded with a maximum of nine blocks to a field and a maximum of 18
blocks to a frame. The screen may be made to contain exclusively digital
or picture data, or a combination of digital and picture data. The digital
data in a block is composed so as to facilitate interleaving and error
correction a block at a time.
FIG. 12 is a block diagram of a playback circuit of the invention. This
circuit is applicable to the case of audio signals added to still pictures
with the digital data being time-axis compressed. The circuit includes
video amplifier 11 used to amplify the video signals. TV synchronizing
separator 12 is provided to separate the V SYNC and H SYNC signals from
the video signals. ATC circuit 13 is provided to automatically set the
threshold level from the amplified video signals to an optimum value
following the data level, and to convert the analog video signals to NRZ
(Non Return To Zero) digital serial data. Clock run-in signals from the
digital data strings are detected by run-in detector 14. Data
synchronizing detector 15 reads the digital data synchronizing signals,
and, for each H, detects the initial position of the data within b and c.
In a similar manner, S/P converter 24 reads the serial data synchronously
with the clock and converts it into eight-bit parallel data. Switching
circuit 16 is provided to detect the data from 23H to 26H in the field,
separate the control data signals, and to switch the output. Clock pulse
sampler 17 samples the clock component from the serial data taking the
run-in signal as a reference. System clock generator 18 applies a PLL
(Phase-Locked Loop) operation to the sampled clock signals and generates
the clock signals necessary for system operation. The timing signal
generator 2 uses the clock signals obtained from the system clock
generator as a reference and is controlled by the V SYNC and H SYNC
signals separated by TV synchronizing separator 12 and the data starting
point detection signal obtained from data synchronizing detector 15.
Accordingly, it generates the different timing signals. Field SYNC
detector 19 is controlled by the timing signals generated by the timing
signal generator, detects the field SYNC signals, and synchronizes clock
signals and data at the starting point of the respective fields according
to the clock run-in signal and data period and pattern. Control buffer 20
temporarily stores the control codes separated by switching circuit 16.
Error corrector 4 corrects the errors, if any, in the control codes read
from the control code buffer. De-interleaver 21 processes the corrected
control codes according to a predetermined control sequence. System
controller 7 decodes the sequence of control codes and generates
corresponding control signals. Address counter 22 receives an initial
address signal from system controller 7 at the time data is written into
or read from large-capacity memory 5. Similarly, it receives the clock
pulses generated by timing signal generator 2 at the time data is written
or read thereinto or therefrom, in either case, eight bits at a time. In
either case it counts up and supplies address signals to buffer memory 5.
Large capacity buffer memory 5 temporarily stores the digital data in
block c in response to signal f.sub.2 (W) from timing signal generator 2,
and reads the data in response to f.sub.1 (R). Error corrector 3 corrects
the error in the large capacity buffer memory a block at a time.
De-interleaver 23 converts the corrected data into a succession of serial
data. Digital/analog converter 9 processes a series of digital data in
response to signal f.sub.1 (R) from timing signal generator 2 and converts
it into analog signals. Player controller 10 receives the control signals
from system controller 7 for the VDP and supplies the VDP with VDP control
signals.
The VDP will perform a normal playback operation for a period A if it is
playing back a video format signal recorded in, for instance, the pattern
shown in FIG. 6. During this interval, the digital data inserted in block
c will be recorded sequentially in memory 5. It is assumed that over the
next period B, the VDP will reproduce still pictures or playback frame-fed
data. The digital data stored in memory 5 will be applied as the present
output. If this is time-axis compressed audio digital data, its output
will occur at the corresponding still picture or frame-fed data playback
time as analog audio data after time-axis expansion. Furthermore, during
period A, the TV monitor will display the data clamped to a black level in
screen processors 8 (FIG. 9).
Similarly, the digital data in block c will be successively stored in the
memory during period A when the video format signal with the pattern shown
in FIG. 7 is played back. The top and bottom of the monitor screen are
made to remain at the black level, the image appearing in the intermediate
area.
Following this, the playback video format signal from the VDP video output
terminal is applied to video amplifier 11 and there amplified. The
amplified output is applied to synchronizing separator 12, and the
separated synchronizing signals (V and H) are fed to one of the input
terminals of timing signal generator 2. The amplified video signal is
applied to the input of ATC circuit 13. By detecting the peak and pedestal
levels of the data, the ATC circuit gradually and automatically sets the
threshold level while following the respective data, and extracts the
serial NRZ digital data from the video signals. Controlled by the timing
control signal from timing signal generator 2, run-in signal detector 14
detects the 24-bit 12-cycle clock run-in signal from the serial data
extracted by the ATC output of detector 14 and applied to the clock
sampling circuit 17, which extracts the clock component from the normal
serial data, taking the clock run-in signal as a reference. The extracted
clock component is applied to system clock generator 18. From the
extracted clock component, the system clock generator causes the PL1
circuit to generate system clock signals synchronized with the serial
data. These clock signals are employed for system operation. The clock
signals generated by system clock generator 18 are applied to timing
signal generator 2. Timing signal generator 2 generates timing signals
applied to the control terminals of field SYNC detector 19, which is
controlled by the synchronizing signals (V and H) with the clock signals
as a reference, and detects the horizontal scanning line 22H in each
field, and thereby the field SYNC. Timing signal generator 2 also
generates the timing control signals to separate control data after
detecting 23H to 26H, and generates control signals for data write and
read operations following detection of 27H.
Serial data obtained as output from ATC circuit 13 is applied to data
synchronizing detector 15 and S/P converter 24. All the data is read
synchronously with the clock, and, for each H, synchronous data detector
15 detects data synchronizing signals, applies a detection output to
timing signal generator 2, determines the initial position of data, and
thereby maintains a constant synchronizing relation between the data and
the timing signal. S/P converter 24 converts the serial data into
eight-bit parallel data. The eight-bit data is applied to switching
circuit 16. If timing signal generator 2 generates a signal indicating the
presence of 23H to 26H, switching circuit, 16 applies that signal to
control code buffer 20; at all other times, it applies the signal to
large-capacity buffer memory 5. The control code temporarily stored in
control code buffer 20 is applied to the input terminal of error
correcting circuit 4. The control code with its error corrected by the
error correcting circuit is applied to the input of deinterleaver 21.
De-interleaver 21 rearranges the control code according to the control
sequence and applies the rearranged code to system controller 7. The
system controller 7 decodes the control code and follows the timing
control signals from timing signal generator 2 to perform operations of
digital data writing, screen control, initialization of address counter 22
for the large-capacity buffer memory, and control of digital data. Control
signals operating and stopping the player are applied to player controller
10. These signals are converted by the player controller into signals for
driving the player, and are then supplied to the player. The horizontal
scanning line 22H signal from timing signal generator 2 is applied to the
control terminal of field SYNC detector 19. Based on a repetition of the
clock run-in signal and data synchronizing signal, the detector generates
the reference signal for the clock signal within the fields and data
synchronization. These are fed back to clock sampling circuit 17 and
timing signal generator 2. Next, when the signal indicating 27H, as
detected from the output of the timing signal generator and the control
codes, and the code indicating storage of digital data in the block are
decoded by system controller 7, they are successively stored in
large-capacity buffer memory 5 in response to signal f.sub.2 (W) generated
by timing signal generator 2 and in response to the control signal
generated by the system controller. When the storage of a specified amount
of data is complete, system controller 7 commands the player to generate
still pictures in the specified frame, and the player generates still
pictures. At that time, from large-capacity buffer memory 5, the initial
address read from system controller 7 is set in address counter 22 and is
read sequentially in response to signal f.sub.1 (R) generated by timing
signal generator 2. The data read sequentially from large-capacity memory
5 is fed to the correction circuit, there corrected, then applied to the
input of de-interleaver 23. In the de-interleaver, the data is rearranged
in the sequence of the original data, and then applied to the input of D/A
converter 9. In D/A converter 9, the signal is converted into a
corresponding analog audio signal and applied as an audio output. While an
audio output is present, the player generates still pictures. Once data in
the amount specified by large-capacity buffer memory 5 has been viewed and
heard, search or play control signals are fed to the player according to
the program codes.
The following describes clock synchronization and data synchronization in
run-in signal detector 14, data synchronization detector 15, and field
SYNC detector 19. Clock synchronization and data synchronization in a
field are established for the first time by the 10 clock run-in cycles and
data synchronizing signals included in the 22H field SYNC. In other words,
the clock component in the clock run-in signal is extracted by clock
sampling circuit 17, and the PLL circuit of clock generator 18 is
synchronized therewith. This circuit is then synchronized with the data
the initial position of which is detected by means of the data
synchronizing signal and is applied to timing signal generator 2. The
field SYNC includes 10 each of the clock run-in cycles and data
synchronizing signal so as to be able to synchronize the clock and data in
case part of the signal is lost, for instance, due to drop-out. After
synchronization has been established within the field SYNC, clock and data
synchronization are maintained while compensating for loss of clock signal
phase synchronization or missing bits by using the clock run-in and data
synchronization signals detected by, respectively, the run-in signal
detector and data synchronization detector from the initial position of
the respective Hs in the data. The clock run-in and data synchronizing
signals at the initial position of the respective Hs are also used for
synchronization if the clock signals or data go out of synchronization due
to, for instance, drop out.
FIG. 13 shows an example of data synchronizing detector 15. Here, pattern
filter 151 detects the data synchronizing signal pattern 1100100, after
which the detector issues detection pulses. Input of the detection pulses
to the subsequent circuit is restricted by NAND gate 152 and a signal (DSG
signal) at a specific timing because the detection pulse may be the result
of detection of noise or a false data synchronizing signal. The detection
pulse is latched by latch circuit 153, passes NOR gate 154, and is then
stored by the other latch circuit, namely latch circuit 155. It is then
successively fed to seven bit shift register 156. Whether the MSB of this
register and the corresponding detection pulse match at NOR gate 154 is
also detected. If they do, synchronizing pulses are issued after detection
of ten data synchronizing signals at 22H, as shown in FIG. 10. From 23H
onwards (FIG. 11), however, the output timing is changed to allow issuance
of the synchronizing pulses immediately after one data synchronizing
signal is detected. To this end, a gate signal (LDG signal) of a specific
timing is used at AND gate 157 to control the time of generation of the
synchronizing pulses. This makes it possible to make use of 222H.
Furthermore, AND gate 158 is also used to initially clear shift register
156.
Within block c, the picture and digital data must be distinguished from
each other. To make this possible, an indicator of the following block is
used as the control data, which indicator is inserted at the beginning and
the end of the picture data. An example of this appears in FIG. 14 where
four start block bits are used at the beginning of the picture data. The
four bits can take values from 1 to A (hexadecimal). Four end block bits
are used to designate where the picture data ends, taking any value from 2
to A (hexadecimal). These values of the respective four bits, however,
change according to the value of x dividing block c into subblocks. The
example here corresponds to x =9. Table 1 below shows the correspondence
between the video format signals in FIG. 5 and the respective start and
end block codes.
FIG. 15 is a block diagram of a playback circuit used for controlling the
playback operation using a code indicating the position of insertion of
the picture data. A divide-by-252 counter 25 is provided to detect 26H of
the H SYNC from among the synchronization signals separated by signal
separator 1 (FIG. 9), and also, at the same time, control the field
designation. The Q output of flip-flop (FF) 26, which goes to "1" when a
pulse is generated when the counter reaches 16, is employed as a clock
signal for counter 28, fed thereto via an AND gate 27. The other input of
the AND gate 27 receives H SYNC signals. A "1" output from gate 27 is
generated from 27H and later H SYNCs. 27H and later H SYNCs form the clock
input of the divide-by-26 counter 28, which is cleared by V SYNC. This
counter detects the m-th subblock from among subblocks c.sub.1 to c.sub.9
in block c. In this example, m =26, which is equal to the counter radix
26. Decimal counter 29 counts in response to the carry signal from the
counter 28 and is cleared by V SYNC. This counter counts the subblocks
within blocks c and Q.
Four-bit latch 30 temporarily stores the four start block code signal bits
from the control decoder 6 (FIG. 9) output, and four-bit latch 31
temporarily stores the four end block code signal bits. Coincidence
circuit 32 receives as one of its inputs the output signal from four-bit
latch 30 and as the other input the four-bit output signal Q.sub.1
-Q.sub.4 indicating the status of decimal counter 29. Coincidence circuit
32 compares the two inputs, and if the corresponding bits are identical,
sends out a pulse. Similarly coincidence circuit 33 receives as one of its
inputs the output of four-bit latch 31, and as another four bit input
Q.sub.1 -14 Q.sub.4 from decimal counter 29, compares the two inputs, and
if the corresponding bits agree, sends out a pulse. FF 35 receives as its
clock input the pulse signal issued by coincidence circuit 32, and
produces an output Q of "1" at that time. Output Q of FF 35 becomes "0" at
the output from OR gate 34, which receives as one of its inputs the output
from coincidence circuit 33 and as another input the V SYNC signal, thus
generating a "1" output in the presence of any one or both of these
inputs. When output Q is "1", it is connected to side a of switch 36, and
when it is "0", it is connected to b of this switch. Masking circuit 37 is
provided to set the black level of the picture. Switch 36 provides as its
output the input video signal when Q is connected to a of this switch.
When Q is connected to b of switch 36, masking circuit 37 issues its
output. The other output Q from FF 35, connected to AND gate 38, controls
application of write pulse f.sub.2 (W) to large-capacity buffer memory 5.
The above configuration makes it possible for the video format signal
combining picture and digital signals to be applied on the input side of
signal separator 1 and, at the same time, at terminal a of switch 36. Of
the components into which signal separator 1 separates its input signal, V
SYNC applied to terminal CLR of divide-by-252 counter 25, terminal CLR of
FF 26, terminal CLR of divide-by-m counter 28, terminal CLR of
divide-by-(x+1) counter 29, and one of the input terminals of OR gate 34.
This V SYNC initializes divide-by-252 counter 25, FF 26, divide-by-m
counter 28, divide-by-(x+1) counter 29, and FF 35. The H SYNC signal
separated by the signal separator is applied to clock terminal ck of
divide-by-252 counter and also to one of the input terminals of AND gate
27. Divide-by-252 counter 25 controls the respective fields of an NTSC TV
signal. For each field, the counter is cleared when V SYNC is active. In
other words, it starts its incrementing operation each time a H SYNC pulse
is applied starting from 11H. It issues a pulse after every 16 H SYNC
pulses. The pulse corresponds to 26H of the respective fields of an NTSC
TV signal. This pulse is applied to clock terminal ck of FF 26 when Q is
in the "1" state. FF 26 acts as a flag, Q remaining at logic "1" as long
as V SYNC continues to be applied to the CLR terminal after 26H. The Q
output of FF 26 is applied to one of the input terminals of AND gate 27
while to the other input terminal of AND gate 27 there is applied H SYNC
separated by signal separator 1. Accordingly, AND gate 27 generates an H
SYNC output following 27 H. This causes H SYNC from block c on the screen
(FIG. 1) to be applied on clock terminal ck of the divide-by-m counter.
The divide-by-m counter is used to control the subblocks of the various
blocks. In this example, m =26. The carry output of divide-by-m counter is
applied to clock terminal ck of divide-by-(x+1) counter. Divide-by-(x+-1)
counter 29 controls the position of the subblocks in a block. This counter
counts not only area c but area Q as well until the arrival of V SYNC,
and, therefore, has a radix (x+1). Since x is 9, the radix is 10 for this
counter. The four-bit output Q.sub.1 -Q.sub.4 indicating the status of
the counts is applied to input terminals of coincidence circuits 32 and
33. Further, a control data start block code separated by signal separator
1, indicating the beginning of picture data, is applied to the input
terminal of latch 30 and is stored therein. The period of this storage is
equal to either one field or one frame. The output is applied to the other
input terminal of coincidence circuit 32. The coincidence circuit compares
each of the four bits with the corresponding four bits, and if they are
identical, pulses are issued at the output. Similarly, a control end block
code separated by signal separator 1, indicating an address of the block
following the end of the picture data, is applied to the input of latch
31. The output is applied to the other input terminal of coincidence
circuit 33. The corresponding bits are compared, and if they coincide,
pulses are issued. The output of coincidence circuit 32 is applied to the
clock terminal of FF 35. Also, the output of coincidence circuit 33 is
applied to one input of OR gate 34. The output of OR gate 34 is applied to
clear terminal CLR of FF 35. If the coincidence pulse from coincidence
circuit 32 is applied to FF 35, its output Q goes to "1". If the
coincidence pulse from coincidence circuit 33 is applied to FF 35, its
output Q becomes "0", which is exactly opposite of output Q of FF 35 when
a pulse is received from circuit 32. Output Q from FF 35 is applied to
switch 36. The switch is set to a when output Q of FF 35 is logic "1", and
to b when Q is logic "0". The Q output of FF 35 is applied to one of the
input terminals of AND gate 38. To the other input terminal of AND 38 gate
is applied write pulse f.sub.2 (W) generated only within block c by timing
signal generator 2 (FIG. 9). When output Q from FF 35 is "0", AND gate 38
supplies write pulse f.sub.2 (W) to large-capacity buffer memory and
successively stores data separated by signal separator 1.
For the waveform shown in FIG. 5C, for example, the start block code is 3
and the block code is 8. Correspondingly, latches 30 and 31 are set to,
respectively, 3 and 8. Initially, the Q output of FF 35 is "0", so that
switch 36 is set to b. As a result, the video output is the output of
masking circuit 37. The masking circuit masks the video signals, excluding
the synchronizing signals and color burst, under a black level. The
resultant screen is black. Since output Q from FF 35 is a logic "1", AND
gate 38 will continue to generate the f.sub.2 (W) pulse as its output,
causing the data separated by signal separator 1 to be written
successively in buffer memory 5.
Coincidence circuit 32 generates pulses when divided-by-(x+1)- counter 29
has counted to 3. At the leading edge of this pulse, therefore, output Q
from FF 35 becomes "1". Accordingly, switch 36 gets set to a and input
video signals, namely the image information, is applied as an output.
Since output Q from FF 35 is "0", pulses are not generated from gate 38.
Accordingly, no data is written into buffer memory 5. Similarly, when the
divide-by-(x+1) counter has counted up to 8, pulses generated by
coincidence circuit 33 pass through OR gate 34 and are applied on terminal
CLR of FF 35. As a result, output Q from this FF becomes "0", and switch
36 is set to b. This makes output from masking circuit 37 possible again.
In other words, the screen will be black again. At the same time, output Q
from FF 35 becomes "1", and f.sub.2 (W) generated by the timing signal
generator makes the output from AND gate 38 write the data separated by
the signal separator in sequence into the large capacity buffer memory.
The timing for the above operations is indicated in FIG. 16. FIG. 16 shows
the first field of the first frame of an NTSC signal. The information
shown in this figure, however, applies to the video signals of the second
field as well. In the above example, control data differentiating between
picture and digital data and detecting the position of digital data is
constituted by the starting picture data block and the block following the
end of the picture data. However, the starting digital data block or the
block following the end of digital data can serve the same purpose. Even
the first and the last digital data blocks can be used as the control
data. The audio digital data (SWS data) to be inserted need not be
monaural and may be constituted by stereo data.
FIG. 17 is a block diagram of a playback unit used for video format signals
where the audio data comprises different types and has varying contents
and, at the same time, a complex tone content. The video format signal is
sent to synchronizing separator 12 which separates it into V SYNC and H
SYNC signals. At the same time, the video format signal is sent to timing
signal generator 2 in order to generate timing signals. The input video
format signals are fed also to an ATC circuit. The ATC circuit prevents
data reading errors caused due to errors in the video signal or
differences in video disks. Thus, the best threshold level is determined
on the basis of the peak and pedestal levels of data inserted in the video
signals, whereby th data of the analog video signals is changed into NRZ
digital signals with their waveform shaped. Fr | | |
