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Schottky-clamped transistor logic buffer circuit
   
Document Number
US Patent 4851715
Issued Date
July 25, 1989
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Abstract
A high speed interstage STL buffer (27) is disclosed having a low threshold and high driving capability. A first Schottky-clamped grounded emitter transistor (28) receives input signals through a Schottky steering diode (38) and inverts the input signal. The input signal is applied in parallel through a Schottky steering diode (20) to a second Schottky-clamped grounded emitter transistor (12). The collector (22) of the second transistor (12) provides an output of the buffer (27) for driving load current in one direction with respect to the buffer output. A third transistor (40) connected as an emitter follower has the emitter (42) thereof connected to the buffer output for driving load currents in the other direction. The base (46) of the emitter follower transistor (40) is coupled by a Schottky steering diode (50) to the collector (32) of the first transistor (28). The steering diodes (20, 38, 50) have a forward threshold voltage less than that of the Schottky-barrier diodes used to clamp the base-collector junctions of the first and second transistors (28, 12).
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Schottky-clamped transistor logic buffer circuit - US Patent 4851715 Drawing
Drawing from US Patent 4851715
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Number of Claims:
11
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Owner
Published
July 25, 1989
Application Number
07/287,682
Filed
December 20, 1988
US Classification
326/19   326/89
Int'l Classification
H03K   19/082   (20060101)   H03K   19/084   (20060101)  
Assistant Examiner
Parent Case
This application is a continuation of application Ser. No. 185,232 filed Apr. 18, 1988, now abandoned, which is a continuation of Ser. No. 851,055, filed Apr. 11, 1986, now abandoned.
USPTO Field of Search
307/270   307/254   307/446   307/263   307/268   307/458  
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Description
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