System for scan testing of logic circuit networks

What is claimed is:

1. A test block structure for scan testing a network of digital logic blocks, the test block structure comprising:

a first input node for receiving a first digital input signal,

a first output node for outputting a first digital output signal;

first switch means for selectively connecting said first input node to said first output node, the first switch means including first and second signal conducting portions for conducting signals through the first switch means;

a second input node for receiving a second digital input signal;

a second output node for outputting a second digital output signal;

data storage means, having an input terminal and an output terminal, for storing digital data received at the input terminal thereof from either of the first and second input nodes and for outputting the stored digital data through the output terminal thereof, said output terminal being connected to the second output node,

second switch means for selectively connecting the input terminal of the storage means to the second input node;

third switch means for selectively connecting said first input node to the input terminal of said data storage means, the third switch means being integrally formed with the first signal conducting portion such that signals passing through the third switch means must pass through the first signal conducting portion; and

fourth switch means for selectively connecting the output terminal of said data storage means to said first output node, the fourth switch means being integrally formed with the second signal conducting portion such that signals passing through the fourth switch means must pass through the second signal conducting portion.

2. A test block structure as recited in claim 1 wherein the data storage means comprises a first latch and a second latch coupled to the first latch wherein said first latch and said second latch function together as a master/slave flip flop circuit with said first latch functioning as the master latch and said second latch functioning as the slave latch.

3. A structure as in claim 1 further comprising input switch control means coupled to the second and third switch means for controlling said second and third switch means so that said second switch means is closed to thereby connect the first input node to the input terminal of the data storage means when said third switch means is open, and said third switch means is closed to thereby connect the second input node to the input terminal of the data storage means when said second switch means is open.

4. A structure as in claim 1 further comprising output switch control means coupled to the first and fourth switch means for controlling said first and fourth switch means so that said first switch means is closed to thereby connect the first input node to the first output node when said fourth switch means is open, and said fourth switch means is closed to thereby connect the output terminal of the data storage means to the first output node when said first switch means is open.

5. A structure as in claim 1 wherein said first switch means comprises a first pass transistor having a first signal passing terminal connected to the first input node and a second signal passing terminal connected to the first output node, said second switch means comprises a second pass transistor having a third signal passing terminal connected to the second input node and a fourth signal passing terminal connected to the input terminal of the data storage means, said third switch means comprises a third pass transistor having a fifth signal passing terminal connected to the first input node and a sixth signal passing terminal connected to the input terminal of the data storage means, and said fourth switch means comprises a fourth pass transistor having a seventh signal passing terminal connected to the first output node and an eighth signal passing terminal connected to the second output node.

6. A structure as in claim 5 wherein each of the first, third, and fourth pass transistors is a field effect transistor having a source and a drain, said sources and drains of the first, third, and fourth pass transistors being formed of first, second, third, and fourth diffusion regions arranged such that the source and drain of the third transistor are formed of the first and second diffusion regions, the source and drain of the first transistor are formed of the second and third diffusion regions, and the source and drain of the fourth transistor are formed of the third and fourth diffusion regions.

7. A structure as in claim 6 wherein the gate of said first pass transistor comprises a portion of an elongated serial line, said line having a first end and a second end wherein a signal applied on said first end and measured on said second end verifies the integrity of said elongated serial line.

8. A scan testable network comprising a first test block structure in accordance with claim 1 coupled to a second test block structure in accordance with claim 1.

9. A scan testable network comprising:

first through third test block structures, each having the structure recited in claim 1; and

first through third combinational logic blocks, each having plural combinational input leads and a combinational output lead;

wherein the first input node of each of the first through third test block structures is respectively coupled to the combinational output lead of the first through third combinational logic blocks and wherein the first output node of the first and second test block structures are respectively coupled to first and second combinational input terminals of the third combinational logic block.

10. A digital logic test block for scan testing a network of digital logic circuits, comprising:

a primary input node for receiving first primary data from one of the digital logic circuits of said network;

an auxiliary input node for receiving first auxiliary data;

a primary output node for outputting primary output node data to another of the digital logic circuits of said network;

an auxiliary output node for outputting second auxiliary output node data;

digital storage means for storing input data received at either of the primary and auxiliary input nodes, the storage means having an input line for receiving the input data and an output line for outputting stored data;

first switching means for selectively connecting the input line of the storage means to one of the primary and auxiliary input nodes, the first switching means including a first signal conducting portion for conducting signals between the primary input node and the storage means input line; and

second switching means for selectively connecting the primary output node to one of the primary input node and the output line of the digital storage means, the second switching means having a first signal conducting portion being adjoined to the first signal conducting portion of the first switching means such that the second switching means shares the first signal conducting portion with the first switching means and such that verification of signal conduction through the first switching means, from the primary input node to the input line of the storage means, assures the integrity of the first signal conducting portion of the second switching means.

11. The test block of claim 10 wherein the second switching means includes a second signal conducting portion for conducting signals both between the primary input node and the primary output node and between the output line of the digital storage means and the primary output node whereby verification of signal flow between the output line of the digital storage means and the primary output node assures the integrity of the second signal conducting portion.

12. The test block of claim 11 wherein the first switching means comprises a first pass transistor having a source/drain formed in a first semiconductor diffusion region and wherein the second switching means comprises a second pass transistor having a source/drain also formed of the first semiconductor diffusion region, the first semiconductor diffusion region defining part of the first signal conducting portion.

13. The test block of claim 12 wherein the second pass transistor has a second source/drain formed of a second semiconductor diffusion region and wherein the second switching means further includes a third pass transistor having a source/drain formed in the second semiconductor diffusion region, the second semiconductor diffusion region defining part of the second signal conducting portion.

14. The test block of claim 12 wherein the first pass transistor is a field effect transistor having a gate formed of a portion on an elongated serial line in a manner such that the integrity of the gate may be verified by verifying the continuity of the serial line.

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BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a system for scan testing logic circuit networks.

2. Description of the Prior Art

Scan testing is a widely accepted means for functional testing of large scale integrated circuits and very large scale integrated circuits. To implement scan testing a special shift register is usually added to an integrated logic circuit solely for the purpose of functional testing. The special shift register comprises interconnected test blocks which are connected to the logic circuit.

FIG. 1 shows a typical prior art scan testing circuit arrangement including a network of combinational logic circuits 1, 2, 3 . . . n. The primary inputs IN.sub.1, to the IN.sub.2, . . . IN.sub.n combinational logic circuitry and the outputs OUT.sub.1, OUT.sub.2, . . . , OUT.sub.n from the combinational logic circuitry remain unchanged, but test blocks 10, 20, 30 . . . n0 are connected respectively to the combinational logic circuitry 1, 2, 3 . . . n at points which permit surveillance of the functions performed in each logic circuit. The test blocks are interconnected to form a shift register 45 having a serial input terminal (scan-in input line) 4 and serial output terminal (scan-out output line) 5. The operation of the combinational logic circuits and the special shift register are generally dependent only upon the digital logic level, and correct operation is not dependent upon the rise time, fall time, or minimum delay of any individual circuit or signal.

Each test block in FIG. 1 has four input lines and one output line. For example, the test block 10 has a primary data input line 13 associated with combinational logic circuit 1, an auxiliary data input line 11, a scan control input line 14, and a clock input line 12. The auxiliary data input line 11 is connected to the scan-in input line 4. The output line 15 of the first test block 10 is connected to the auxiliary data input line 21 of the second test block 20, the output line 25 of the second test block is connected to the auxiliary data input line 31 of the third test block 30, and the output line of each test block is connected to the auxiliary data input line of the next test block up to the last test block n. The output line n5 of the final test block n is tied to the scan-out output line 5.

A scan test consists of two basic parts. The operation of the special shift register 45 comprising the interconnected test blocks 10, 20, 30, . . . , n0 is first checked. Then the operation of the logic system is checked. To verify operation of shift register 45 a test vector is scanned through shift register 45. A scan test is used to verify the operation of the logic system. Proper sequencing of the clock signal, scan control signal, test signals, and primary input signals is necessary to perform the scan test. The scan test applies known input signals to combinational logic circuits and then the output signals, generated by the logic circuit response to the known input signals, are measured. Comparison of the predicted output signals with the measured output signals indicates the functionality of the circuits.

The sequencing of the clock signals, scan control signal, test signals and the primary input signals will depend upon the configuration of the test blocks. A typical test block 10' which requires only a single clock line is shown in FIG. 2. A primary data input line 100 from a combinational logic circuit such as circuit 1, 2, 3, . . . or n of FIG. 1 is connected a first input terminal of the AND gate 120. A first line 101 connects the scan control line 103 to an inverter on the second input terminal of the AND gate 120. The auxiliary data input line 102 and the scan control line 103 are connected to the input terminals of a second AND gate 121. The output line 105 from the AND gate 120 and the output line 106 from the AND gate 121 are connected to the input terminals of OR gate 122. The output line 107 from the OR gate 122 is connected to the input terminal D of the master latch 123. A clock input line 104 is connected to the clock terminal C of the master latch 123 and to an inverter 126. The output line 109 from the master latch 123 is connected to the input terminal D of a slave latch 124. The output line 110 from the inverter 126 is connected to the clock input C of the slave latch 124. The test block output line 111 is connected to the output terminal Q of the slave latch 124.

The normal mode of operation for the test block shown in FIG. 2, requires a low signal on the scan control line 103. With a low signal on the line 103, the output signal of AND gate 121 on the line 106 is always low, and the signal from the inverter on the second input terminal of the AND gate 120 is high. If the signal on input line 100 to AND gate 120 is high, the output signal on line 105 is high, but if the signal on line 100 is low, the signal on line 105 is also low. Thus, the signal on the line 105 follows the signal on the primary input line 100.

The output signal of the OR gate 122 on line 107 follows the signal on the input line 105 because the signal on the other input line 106 to the OR gate 122 is low in the normal mode of operation. Therefore, since the signal of the line 105 follows the signal on the input line 100, the signal on line 107 follows the signal on the input line 100, i.e., the primary input signal is applied to the input terminal D of the master latch 123 in the normal mode of operation.

To pass the input signal on line 107 through the master slave flip-flop 125 to the output line 111, a clock signal is provided on line 104. The signal on line 107 is then passed through the flip-flop 125 to the output line 111. Thus, the user of a circuit which contains this test block must provide a sequence of clock signals to the flip-flop 125 which coincide with the signals on line 100 so that the circuit will function normally. Further, the test block also degrades the circuit's normal performance because it introduces additional delays associated with the switching of the master slave flip-flop 125.

To perform a scan test with the test block 10' of FIG. 2, a high signal is applied on the scan control line 103. This places the test block in the scan mode. In this mode, any signal applied on line 102 is present on the input line 107 of the master latch 123 and when a clock pulse is provided on line 104 the input signal is loaded into the flip-flop 125 and available on the output line 111. After this seqeunce of operations the test block is in the test mode because a known test signal is available on the output line 111 which is connected to an input line of the logic circuit under test. To determine the results of applying a known input signal to the logic circuit under test the logic circuit is given time to stabilize and then the data receive mode is used.

In the data receive mode, the high logic signal on the scan control line 103 is switched to a low logic level. As described previously, for a low signal on the scan control line 103, the signal on the input line 100 is applied to the input terminal D of the master latch 123. Thus, if the line 100 is connected to the output line of a logic circuit under test, the output signal is available to the input terminal D of the master latch. Application of a clock pulse on the clock input line 104 stores the test output signal in the flip-flop 125.

Next the signal on the scan control line 103 is again switched to a high signal, and a sequence of clock pulses is applied to shift the stored test signals out of the shift register 45 comprised of the interconnected test blocks, as shown in FIG. 1.

The implementation of this prior art scan technique requires that the flip-flops in the each test block remain in the normal signal path of the combinational logic circuit network even after the test is completed. The extra circuitry introduces timing delays as well as the need for clock pulses to pass the normal circuit logic signal through the latches.

While other prior art test blocks are used in scan testing, these other block tests also require that the normal combinational logic circuit output signals pass through one or more flip-flops before the signals are availale to the next portion of the combinational logic circuitry. This requires sequencing of one or more clock pulses to the flip-flops during normal operation of the combinational logic circuitry. The user must not only understand the general logic circuit but also the interaction of the test blocks with the circuits. A malfunction of the flip-flop in a test block under normal operation will directly affect the output signal from the combinational logic circuitry.

Another prior art system 150 for scan testing of logic circuits is shown in FIG. 3. The normal output lines 180 from the logic circuit under test are a first set of input lines to a multiplexer 191. The multiplexer output lines 184 are the input lines to a group of output registers 192 controlled by line 187. The output lines 185 from the output registers 192 are the output lines for the logic circuit. The lines 186 are connected to the output lines 185 and to the inputs of the scan register 190. The scan register 190 also has a clock input line 181, scan-in line 182, a mode control input line 183, a scan-out output line 193, and a set of output lines 188, which are a second set of input lines to the multiplexer 191. The scan register 190 is basically a register with shift capability. The mode control input line 183 is also connected to the multiplexer 191.

This system has some advantages over the other prior art scan testing systems because the normal signal path through this system requires only that the signal on the mode control line be set so that the multiplexer passes the signals on the input lines 180 to the output lines 184. Hence, the user is not required to sequence clock pulses with the normal signals from the logic circuit under test to pass the normal logic circuit signals through the scan testing system. Also, a test vector may be loaded into the scan register while the normal signals from the circuit are passed through the scan system.

However, this system requires additional hardware and the system still permits only a high degree of fault coverage. Therefore, the prior art scan testing systems while assisting in determining the functionality of a logic circuit are difficult for the user to use and introduce additional failure modes which may not easily be checked or verified by the user.

SUMMARY OF THE INVENTION

In accordance with my invention I solve the problems of the prior art by providing a primary test circuit incorporating at least one logic test block for verifying the functionality of the primary circuit. Logic test blocks incorporated in the primary circuit are transparent to the user during normal operation of the primary circuit, but yet the logic test blocks provide the capability for complete scan testing of the primary circuit. Further, each logic test block is designed such that every function performed by the logic test block may be tested so as to verify correct operation of the logic test block. Each logic test block comprises a plurality of switching elements that enable a multiplicity of modes of operation of the primary circuit.

The logic test block of this invention has a primary input terminal, a scan-in input terminal, an output terminal, a scan-out output terminal and a scan clock input terminal. The primary input terminal is connected to the output terminal by a first switch means. The scan-in terminal is connected to the input terminal of a data storage means by a second switch means, while the scan-out output terminal is connected to the output terminal of the data storage means. The scan clock input terminal is connected to the clock terminal of the data storage means. A third switch means connects the primary input terminal to the input terminal of the data storage means and a fourth switch means connects the logic test block output terminal to the output terminal of the data storage means.

This novel logic test block is inserted into each primary circuit line where it is desired to verify the logic signal. The primary circuit line is effectively separated producing two ends. A first end of the primary circuit line is connected to the input terminal of the logic test block while the second end of the primary circuit line is connected to the output terminal of the logic test block.

The scan-in and scan-out terminals of the logic test blocks incorporated in the primary circuit are interconnected to form a shift register. The logic test blocks may function in either the normal, scan, test, or data receive modes.

A novel feature of the invention is that during normal operation the first switch means and the third switch means are closed while the second switch means and the fourth switch means are open. Hence, the primary circuit's logic signal is passed from the primary input terminal through the first switch means to the output terminal of the logic test block. The user of the primary circuit does not have to be concerned with shifting data through the logic test block during normal operation. Rather, the signal from the primary circuit is passed directly through the logic test block in its normal configuration.

To perform the scan testing the switch means in the logic test blocks incorporated in the primary circuit are opened and closed in predetermined sequences. Clock pulses are applied to shift data into and out of the logic test block's data storage means. Using scan testing, the user can verify the functionality of the primary circuit.

During the scan testing, the first switch means in the logic test blocks will be open, so that the signals may be appropriately transferred through the data storage means from either the primary input terminal or the scan-in input terminal. However, the scan testing also verifies the functionality of the first switch means because of the unnique layout of the first switch means. In one embodiment, the first switch means is a transistor which shares its diffusion regions with other transistors, whose integrity is verified by scan testing. Also, the gate of the transistor is a part of a serial line, which includes the gates of similar transistors in other logic test blocks. The serial line is designed to permit easy verification of its integrity. The unique layout of the transistor permits the 100% functional testing and verification of operability of the logic test block.

Finally, this invention permits the user to monitor the logic signals in the primary circuit while the primary circuit is operating in its normal mode.

DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art scan test circuit.

FIG. 2 illustrates a prior art scan logic test block which uses only a single clock.

FIG. 3 illustrates another prior art scan test circuit.

FIG. 4A is a representational diagram of the scan logic test block of this invention.

FIG. 4B is a block diagram of another embodiment of a test block in accordance with the invention.

FIG. 5 is a schematic circuit diagram of an embodiment of a scan logic test block, made in accordance with this invention.

FIG. 6a is a block circuit diagram f an implementation of the novel scan logic test block in a combinational logic circuit so as to permit scan path testing of the combinational logic circuit.

FIG. 6b illustrates the signal levels during loading of a test vector into the logic test blocks.

FIG. 7 illustrates a novel layout of pass transistors in the logic test block of this invention which permits 100% testing for operability of the logic test block.

FIG. 8 illustrates the use of the novel scan logic test block in testing a flip-flop circuit with a feedback loop.

FIG. 9 illustrates the use of the novel scan logic test block in testing of the input/output circuitry of an integrated circuit.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 4A is a conceptual representational diagram of one logical test block of this invention. Conceptually, a logic test block 200 is comprised of two single pole double throw switches, a data storage means and lines interconnecting the switches, the data storage means and the logic circuit containing the logic test block. a first input line 210 of the logic test block 200 is connected to both the second terminal 232 of a first single pole double throw switch input switch 230 and to the first terminal 241 of a second single pole double throw switch (output switch) 240. A second input line, the scan-in input line, 220 is connected to the first terminal 231 of the first single pole double throw switch 230. The selector 233 of the first single pole double throw switch 230 is connected to the input terminal of a clocked flip-flop 250. The scan clock input line 222 is connected to the clock terminal of the data storage means, a flip-flop 250. The output terminal of the flip-flop 250 is connected to both a second terminal 242 of the second single pole double throw switch 240 and the scan-out output line 221 of the logic test block. The selector 243 of the second single pole double throw switch 240 is connected to the logic test block output line 211.

The logic test block of my invention as shown in FIG. 4A functions in the four modes, i.e., normal, scan, test, and data receive modes. The logic test block may be configured to perform some of these functions simulataneously. In the normal mode of operation the selector 233 of input switch 230 is either in contact with terminal 231 or left in the open position. The selector 243 of output switch 240 is connected to terminal 241. In this mode, the signal on primary input line 210 passes through output switch 240 to the test block output line 211 of the logic test block 200. The output of flip-flop 250 is isolated from the output line 211 and the input line 210. Hence, unlike the prior art, in the normal mode of operation the functionality of the logic test block's flip-flop 250 will not affect the operation of the circuit to which the logic test block is connected.

In the scan mode, data is shifted into and out of the logic test block's flip-flop 250. In the scan mode, the selector 233 of input switch 230 is connected to the terminal 231 while the selector of output switch 240 may be connected to terminal 241, terminal 242 or left in the open position. If the selector 243 is connected to terminal 241, a signal may be loaded into the flip-flop 250 without disturbing the normal functioning of the circuit in which the logic test block is located. During the scan mode, clock pulses are applied on the line 222 to shift data into and out of the flip-flop 250.

In the test mode, the signal stored in the flip-flop 250 is used to provide a known signal on the test block output line 211. Therefore, the selector 243 of output switch 240 is connected to terminal 242 and the signal on the output terminal of the flip-flop 250 is available on both the test block output line 211 and the scan-out output line 221. In the test mode, the selector 233 of input switch 230 may be connected to terminal 232, terminal 231, or left in the open position.

In the scan test data receive mode, the signal, which is being tested on the primary input line 210 is stored in the flip-flop 250. Therefore, the selector 233 of the first single pole double throw switch 230 is connected to the terminal 232. The selector 243 of the second single pole double throw switch 240 is connected to the terminal 242 since the data in flip-flop 250 is providing one of the stimuli for the test. A clock pulse is applied on the scan clock line 222 to load the signal being tested on the primary input line 210 into the flip-flop 250.

In addition to the scan test modes, the logic test block 200 can also be configured by selected switch positions to permit real time measurements of signals. For example, the selector 233 of input switch 230 is connected to terminal 232 while the selector 243 of output switch 240 is connected to terminal 241. In this configuration, the signal on the primary input line 210 passes through output switch 240 to the test block output line 211, but the signal on the primary input line 210 also passes to the input terminal of the flip-flop 250 through input switch 230. On the application of a clock pulse on the scan clock input line 222, the signal on the primary input line 210 is loaded into flip-flop 250 and then scanned out on line 221. Therefore, in this configuration, the signal on the primary input line 210 at the time the scan clock pulse is applied, is stored in the flip-flop 250 without interrupting the normal function of the circuit in which the logic test block is contained.

In yet another configuration formed by the switches, the logic test block 200 performs a function equivalent to that of the normal mode of operation of the prior art logic test block in FIG. 2. For this function, the selector 233 of the input switch 230 is connected to the terminal 232 and the selector 243 of the output switch 240 is connected to terminal 242.

In this selected configuration, the signal on the primary input line 210 is passed through input switch 230 to the input of the flip-flop 250, but the signal on the primary input line 210 is not passed through the output switch 240 to the test block output line 211 because the selector 243 of output switch 240 is in contact with terminal 242. Hence, to pass the primary input signal to the test block output line 211, a clock pulse has to be applied on scan clock line 222. In this configuration, the logic test block 200 is therefore functionally equivalent to the normal mode of operation of the prior art circuit 10' in FIG. 2.

To perform a scan test, the logic test block 200 of FIG. 4A or a multiplicity of such logic test blocks are placed in a logic circuit. Typically, the logic test blocks are utilized in a combinational logic circuit. The combinational logic circuit is comprised of combinational logic blocks (CLBs) wherein each CLB has a specified number of input and output lines. A logic test block is normally placed in each output line of the CLBs. Eack CLB output line in which a logic test block is placed is effectively separated producing two ends. A first end is connected to the primary input line 210 of the logic test block and the second end to the test block output line 211. For each group of CLBs which are mutually independent from other CLBs, the scan-in input line and the scan-out output line of the logic test blocks are interconnected to form a shift register.

To perform the scan test, the functionality of the shift register is verified by placing each of the logic test block comprising the shift register in the scan mode. Then a known sequence of signals is applied to the scan-in input line of the first logic test block in the shift register and clock pulses are applied to shift these signals through the shift register. The output signal on the scan-out output line of the last logic test block in the shift register is checked. Comparison of the input signals to the output signals reveals the functionality of the shift register.

After the functionality of the shift register is verified, a known test vector is loaded into the logic test blocks while they are in the scan mode. Then the selector 243 of the output switch 240 is set to the terminal 242 in each logic test block of the shift register. This puts the logic test blocks in the test mode. The signal stored in the flip-flop 250 is then available on both the test block output line 211 and the scan-out test block output line 221. Since the output line 211 of each logic test block is connected to an input line of the logic circuit, the test vector is applied to the input lines of the logic circuit.

After the logic circuit under test has stabilized, the selector 233 of the input switch 230 in each logic test block comprising the shift register is set to the terminal 232. This puts the logic test blocks in the data receive mode and the signal on the primary input line 210 of each logic test block is clocked into its flip-flop 250 by the application of a clock pulse. Next the logic test blocks are placed in the scan mode by placing the selector 233 of the input switch 230 in contact with the terminal 231. A series of clock pulses is applied and the signal on the scan-out line of the last logic test block in the shift register is checked and compared with the signal expected from the combinational logic block to determine its functionality.

Thus, the novel logic test block of my invention provides a means for scan testing. To further illustrate the novelty of the logic test block, a specific embodiment 200A of the logic test block is shown in in FIG. 5. The primary input line 210A is connected to both a drain/source region D/S.sub.1 of a first pass transistor 301 and a drain/source region D/S.sub.2 of a second pass transistor 302. Since the pass transistors in FIG. 5 are symmetric, the designation of source and drain is not important because the transistors pass a signal from the source to the drain or from the drain to the source when a voltage greater than the threshold voltage is applied. Therefore, the first terminal of the transistor is denoted the drain/source (D/S) and the second terminal is denoted the source/drain (S/D).

The scan-in input line 220A is connected to the drain/source D/S.sub.3 of a third pass transistor 303. The source/drain S/D.sub.3 of the pass transistor 303 is connected to both the source/drain S/D.sub.1 of the pass transistor 301, and the input terminal 263 of a first latch 260 (D/S.sub.4). A first control line 320 is connected to the gate of the pass transistor 303. A second control line 310, which supplies the complement of input control signal X.sub.i on line 320, is connected to the gate of the pass transistor 301.

The source/drain S/D.sub.2 of the pass transistor 302 is connected to the logic test block output line 211A. The drain/source S/D.sub.8 of a fourth pass transistor 308 is also connected to the logic test block output line 211A. The source/drain D/S.sub.8 of the pass transistor 308 is connected to the output line 274 of second latch 270. A third control line 330 is connected to the gate of the pass transistor 302. A fourth control line 311, which carries the complement of the output control signal X.sub.o on line 330, is connected to the gate of the pass transistor 308.

The first latch 260 is comprised of two inverters 261, 262 and two pass transistors 304, 305. The drain/source D/S.sub.4 of the pass transistor 304 is connected to the latch input line 263, while the source/drain S/D.sub.4 of the pass transistor 304 is connected to both the input terminal of the inverter 261 and the source/drain S/D.sub.5 of the pass transistor 305 in the latch 260. The output terminal of the inverter 261 is connected to both the output line 264 of the first latch 260 and the input terminal of the second inverter 262 in the latch 260. The output terminal of the inverter 262 is connected to the drain/source D/S.sub.5 of the second pass transistor 305 while the source/drain S/D.sub.5 of pass transistor 305 is connected to the input terminal of the inverter 261. One scan clock input line 222A is connected to the gate of the pass transistor 304. Another scan clock line 312, which carries a non-overlapping complement signal (SCAN CLK.sub.2) of the signal (SCAN CLK.sub.1) on the first scan clock input line 222A, is connected to the gate of the pass transistor 305. In other words, the signal on line 312 will be low when the signal on line 222A is high and high when the signal on line 222A is low.

The output line 264 of the first latch 260 is connected to the input line 273 of a second latch 270. The latch 270 is also comprised of two inverters 271, 272 and two pass transistors 306, 307. The drain/source D/S.sub.6 of the pass transistor 306 is connected to the latch input line 273. The source/drain S/D.sub.6 of the pass transistor 306 is connected to both the input terminal of a first inverter 271 and the source/drain S/D.sub.7 of the pass transistor 307 in the latch 270. The output terminal of the first inverter 271 is connected to both the output line 274 of the latch 270 and the input terminal of the second inverter 272 in the latch 270. The output terminal of the inverter 272 s connected to the drain/source D/S.sub.7 of the second pass transistor 307 while the source/drain S/D.sub.7 of pass transistor 307 is connected to the input terminal of the inverter 271. The scan clock line 312 is connected to the gate of the pass transistor 306. The gate of the other pass transistor 307 is connected to the other scan clock input line 222A.

For normal operation, a high signal is present on line 330 and line 320 (X.sub.i =H, X.sub.o =H). Since the signal on the line 311 is the complement of the signal on the line 330, the signal on the line 311 is low. Similarly, the signal on the line 310 is the complement of the signal on the line 320 and so the signal on the line 310 is also low.

The term "high signal" means a voltage such that when the voltage is applied to the gate of the pass transistor, the signal on the drain/source of the pass transistor is passed to the source/drain of the pass transistor, whereas a low signal means a voltage that is not sufficient when applied to the gate of a pass transistor to pass the signal on the drain/source of the pass transistor to the source/drain of the pass transistor.

The high signal (H.sub.o =H) on the line 330 drives the gate of the pass transistor 302 high. The pass transistor 302 then passes the input signal on the primary input line 210A to the the test block output line 211A. The signal on the latch 270 output line 274 does not pass to the test block output line 211A, since the signal on the line 311 is low and the pass transistor 308 does not conduct. Also, the pass transistor 301 does not pass any signal present on its drain/source D/S.sub.1 from the primary input line 210A because the signal on the line 310 is low.

The high signal on the line 320 drives the gate of the pass transistor 303 high and the signal on the drain/source D/S.sub.3 of the pass transistor 303 from the scan-in input line 220A is passed to the input line 263 of the latch 260. However, the signal on the first scan clock input line 222A is low during normal operation. Thus, the gate of the pass transistor 304 in the latch 260 is low and the pass transistor 304 does not pass the signal on the line 263 to the inverter 261. During normal operation, the state of the latch 260 is not of interest since no signal is being passed to it, and similarly the signal on the scan-out output line 221A is not of interest.

Notice that in the normal mode,