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Claims  |
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What is claimed is:
1. A semiconductor memory formed on one chip comprising:
a memory array including a plurality of word lines, a plurality of data
lines intersecting said word lines, and a between said word lines and said
data lines;
a first common data line for inputting and outputting input and output data
of said memory cells at random;
a plurality of first switch means interposed between each of said data
lines and said first common data line, wherein each of said plurality of
first switch means selectively connects a predetermined data line and said
first common data line;
a plurality of data latching means for latching said output data read out
from predetermined memory cells and said input data to be written into
predetermined memory cells;
second switch means for connecting said data lines and said plurality of
data latching means;
a second common data line for inputting and outputting said input and
output data of said memory cells in series;
a plurality of third switch means interposed between said second common
data line and said plurality of data latching means, wherein each of said
plurality of third switch means selectively connects a predetermined data
latching means and said second common data line;
serial input/output selection means for sequentially selecting said
plurality of third switch means;
first address selecting means for selecting one of said plurality of first
switch means in response to an external address signal and for designating
one of said plurality of third switch means to be selected at first by
said serial input/output selection means; and
second address selecting means for selecting one of said word lines in
response to an external address signal; wherein said plurality of first
switch means, said plurality of data latching means, said second switch
means, said plurality of third switch means, and said serial input/output
selection means are arranged on said chip between said memory array and
said first address selecting means.
2. A semiconductor memory according to claim 1, wherein said serial
input/output selection means comprises a shift register.
3. A semiconductor memory according to claim 1, wherein the random
inputting and outputting of said input and output data of said memory
cells are inhibited at least while said second switch means connects said
data lines and said plurality of data latching means.
4. A semiconductor memory according to claim 1, wherein on said one chip,
said second switch means is arranged between said plurality of first
switch means and said plurality of data latching means.
5. A semiconductor memory according to claim 4, wherein said plurality of
third switch means and said serial input/output selection means are
arranged on said chip between said plurality of data latching means and
said first address selecting means.
6. A semiconductor memory according to claim 1, wherein said first address
selection means generates a signal for designating one of said third
switch means to be selected at first by said serial input/output selection
means, said serial input/output selection means comprising a shift
register including a latch circuit for latching said signal which is
outputted from said first address selecting means.
7. A semiconductor memory according to claim 6, further comprising:
fourth switch means interposed between said first address selecting means
and said serial input/output selection means, for providing said signal
generated by said first address selection signal to said serial
input/output means,
wherein the random input and output of said input and output data of said
memory cells are inhibited at least while said fourth switch means
provides said signal to said serial input/output means.
8. A semiconductor memory according to claim 7, wherein the selections of
said first and third switch means are implemented in parallel.
9. A semiconductor memory formed on one chip comprising:
a first memory array including a plurality of first word lines, a plurality
of first data lines intersecting said first word lines and a plurality of
first memory cells respectively disposed at the points of intersection
between said first word lines and said first data lines, for storing
signals;
a second memory array including a plurality of second word lines, a
plurality of second data lines intersecting said second word lines and a
plurality of second memory cells respectively disposed at the points of
intersection between said second word lines and said second data lines,
for storing signals;
first latching means including a plurality of first latching circuits for
respectively latching signals read out from predetermined memory cells of
said first memory cells to said first data lines;
second latching means including a plurality of second latching circuits for
respectively latching signals read out from predetermined memory cells of
said second memory cells to said second data lines;
first output means for serially outputting said signals stored in said
plurality of first and second memory cells;
first selection means for sequentially selecting said first latching
circuits;
second selection means for sequentially selecting said second latching
circuits;
first address selection means for selecting each of said first data lines
and second data lines in accordance with external address signals, and for
first designating each of said first and second latching circuits to be
selected by said first and second selection means;
second output means for outputting signals stored in selected ones of first
and second memory cells at random;
first switching means for connecting said second output means and a first
data line selected by said first address selection means; and
second switching means for connecting said second output means and a second
data line selected by said first address selection means;
wherein said first address selection means is arranged on said chip chip
between said first memory array and said second memory array;
wherein said first latching means, said first selection means, and said
first switching means are arranged on said chip between first memory array
and said first address selection means, and wherein said second latching
means, said second selection means and said second switching means are
arranged on said chip between said second memory array and said first
address selection means.
10. A semiconductor memory formed on one chip according to claim 9, further
comprising:
first transfer means for transferring signals read out from said
predetermined memory cells of said first memory array to said first
latching means;
second transfer means for transferring signals read out from said
predetermined memory cells of said second memory array to said second
latching means; and
wherein said first and second transfer means are arranged on said chip
between said first memory array and said first address selection means and
between said second memory array and said first address selection means,
respectively.
11. A semiconductor memory formed on one chip according to claim 10,
wherein said first address selection means generates first and second
designating signals for respectively designating said first and second
latching circuits to be selected by said first and second selection means
at first, wherein said first selection means comprises a first shift
register including a first storing means for storing said first
designating signal, and said second selection means comprises a second
shift register including a second storing means for storing said second
designating signal.
12. A semiconductor memory formed on one chip according to claim 11,
further comprising:
first setting means for applying said first designating signal to said
first storing means and a second setting means for applying said second
designating signal to said second storing means;
wherein said first and second setting means are arranged on said chip
between said first address selection means and first selection means and
between said first address selection means and second selection means,
respectively.
13. A semiconductor memory formed on one chip according to claim 12,
further including:
first connecting means for connecting said first output means and a first
latching circuit selected by said first selection means;
second connecting means for connecting said first output means and a second
latching circuit selected by said second selection means; and
wherein said first and second connecting means are arranged on said chip
between said first selection means and said first latching means and
between said second selection means and said second latching means,
respectively.
14. A semiconductor memory formed on one chip according to claim 12,
wherein an outputting operation of said first output means and an
outputting operation of said second output means are provided in parallel.
15. A semiconductor memory formed on one chip according to claim 14,
wherein said outputting operation of said second output means is inhibited
at least while said first transfer means transfers signals read out from
said predetermined memory cells of said first memory cells to said first
latching means.
16. A semiconductor memory formed on one chip according to calim 14,
wherein said outputting operation of said second output means is inhibited
at least while said second transfer means transfers signals read out from
said predetermined memory cells of said second memory cells to said second
latching means.
17. A semiconductor memory formed on one chip according to claim 16,
wherein said outputting operation of said second output means is inhibited
at least while said first setting means is applying said first designating
signal to said first storing means.
18. A semiconductor memory formed on one chip according to claim 17,
wherein a sequential selecting operation of said first selection means and
a sequential selecting operation of said second selection means are
mutually implemented in accordance with a control signal.
19. A semiconductor memory formed on one chip according to claim 18,
further comprising a second address selection means for selecting one of
said plurality of first word lines in accordance with said external
address signals, and a third address selection means for selecting one of
said plurality of second word lines in accordance with said external
address signals.
20. A semiconductor memory formed on one chip comprising:
a first memory array including a plurality of first word lines, a plurality
of first data lines intersecting said first word lines and a plurality of
first memory cells, respectively disposed at the points of intersection
between said first word lines and said first data lines, for storing
signals;
a second memory array including a plurality of second word lines, a
plurality of second data lines intersecting said second word lines and a
plurality of second memory cells, respectively disposed at the points of
intersection between said second word lines and said second data lines,
for storing signals;
first input means for serially inputting signals to said first and second
memory cells;
first latching means including a plurality of first latching circuits for
respectively latching signals to be inputted to predetermined memory cells
of said first memory array;
second latching means including a plurality of second latching circuits for
respectively latching signals to be inputted to predetermined memory cells
of said second memory array;
first selection means for sequentially selecting said first latching
circuits;
second selection means for sequentially selecting said second latching
circuits;
first address selection means for selecting each of said plurality of first
data lines and each of said plurality of second data lines in accordance
with external address signals, and for first designating each of said
plurality of first and second latching circuits to be selected by said
first and second selection means;
second input means for inputting said signals to said first and second
memory cells at random;
first switching means for connecting said second input means and a first
data line selected by said first address selection means;
second switching means for connecting said second input means and a second
data line selected by said first address selection means;
wherein said first address selection means is arranged between said first
memory array and second memory array on said chip;
wherein said first latching means, said first selection means, and said
first switching means are arranged between said first memory array and
said first address selection means on said chip; and
wherein said second latching means, said second selection means, and said
second switching means are arranged between said second memory array and
said first address selection means on said chip.
21. A semiconductor memory formed on one chip according to claim 20,
further comprising:
first transfer means for transferring said signals latched by said first
latching means to said predetermined memory cells of said first memory
array; and
second transfer means for transferring said signals latched by said second
latching means to said predetermined memory cells of said second memory
array; and
wherein said first and second transfer means are arranged on said chip
between said first memory array and said first address selection means and
between said second memory array and said first address selection means,
respectively.
22. A semiconductor memory formed on one chip according to claim 21,
wherein said first address selection means first generates first and
second designating signals for respectively designating said first and
second latching circuits to be selected by said first and second selection
means, said first selection means comprises a first shift register
including a first storing means for storing said first designating signal,
and said second selection means comprises a second shift register
including a second storing means for storing said second designating
signal.
23. A semiconductor memory formed on one chip according to claim 22,
further comprising:
first setting means for applying said first designating signal to said
first storing means; and
second setting means for applying said second designating signal to said
second storing means;
wherein said first and second setting means are arranged on said chip
between said first address selection means and said first selection means
and between said first address selection means and said second selection
means, respectively.
24. A semiconductor memory formed on one chip according to claim 23,
further including:
first connecting means for connecting said first input means and one of
said first latching circuits selected by said first selection means;
second connecting means for connecting said first input means and one of
said second latching circuits selected by said second selection means;
wherein said first and second connecting means are arranged on said chip
between said first selection means and said first latching means and
between said second selection means and said second latching means,
respectively.
25. A semiconductor memory formed on one chip according to claim 24,
wherein an inputting operation of said first input means and an inputting
operation of said second input means are provided in parallel.
26. A semiconductor memory formed on one chip according to claim 25,
wherein said inputting operation of said second input means is inhibited
at least while said first transfer means transfers said signals latched by
said first latching means to said predetermined memory cells of said first
memory array.
27. A semiconductor memory formed on one chip according to claim 26,
wherein said inputting operation of said second input means is inhibited
at least while said first setting means is applying said first designating
signal to said first storing means.
28. A semiconductor memory formed on one chip according to claim 27,
wherein a sequential selecting operation of said first selection means and
a sequential selecting operation of said second selection means are
mutually implemented in accordance with a control signal.
29. A semiconductor memory formed on one chip according to claim 28,
further comprising a second address selection means for selecting one of
said plurality of first word lines in accordance with said external
address signals, and a third address selection means for selecting one of
said plurality of second word lines in accordance with said external
address signals. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and, more
particularly, to a technique which is effective when utilized in a
dual-port memory having a serial input/output function and a random
input/output function for image processing, for example.
As a memory for image processing effective for displaying letters and
drawings on the frame of a CRT (i.e., Cathode Ray Tube), there are known
in the art, for example, memories which are disclosed on pp. 219 to 229,
"NIKKEI ELECTRONICS" published by NIKKEI McGRAW-HILL, on Feb. 11, 1985 and
pp. 211 to 240, "NIKKEI ELECTRONICS" published on Aug. 12, 1985.
The former memory transfers the signals of a memory array in parallel to a
shift register and outputs them in series, or inputs the signals in series
to the shift register and writes them in parallel in the memory array.
On the other hand, the latter memory requires decoder circuits especially
for random access and serial output function of a memory array,
respectively. Moreover, the serial output function operates such a dynamic
latch circuit as an amplifier as will fetch the signals of data of the
memory array in parallel and output them in series.
SUMMARY OF THE INVENTION
Our investigations of the application of an image processing memory have
concluded that a relatively high-grade image processing memory is desired
to have the following functions: a random input/output function; a serial
input/output function; and a function to designate the head address of
serial input/output. These functions are desired to be simultaneously
realized by a simple circuitry.
An object of the present invention is to provide a semiconductor memory
which has both a random input/output function and a serial input/output
function.
Another object of the present invention is to realize the above-specified
two functions by a simple circuit construction.
Still another object of the present invention is to provide a semiconductor
memory which has a function to designate the head address of a serial
input/output in addition to the above two functions.
A further object of the present invention is to provide a semiconductor
memory which can execute the random input/output while it is executing the
serial input/output.
A further object of the present invention is to provide a semiconductor
memory which is intended to simplify the circuitry and to improve the
functions.
The aforementioned and other objects and the novel features of the present
invention will become apparent from the following description taken with
reference to the accompanying drawings.
A representative of the invention to be disclosed hereinafter will be
briefly summarized in the following.
By providing both a signal path for transmitting signals in parallel to the
data lines of a memory array and a latch circuit, and a switch path for
connecting the latch circuit and a serial input/output common data line in
response to a selection signal generated by a shift register, and by
feeding the output signal of a random input/output column decoder as a
start(head) value to the individual bits of said shift register, a column
decoder is used commonly for the random input and output and the serial
input/output.
According to the above-specified means, the serial input/output and the
random input/output can be effected, and the circuitry can be simplified
by generating a selection signal for the random input/output and head
address for the serial input/output by the common column decoder.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a dynamic memory according to one
embodiment of the present invention;
FIG. 2 is a circuit diagram showing one specific embodiment of the
individual essential features of the random input/output and serial
input/output of the memory of FIG. 1; and
FIGS. 3 and 4 are timing charts showing one example of the operations of
the memory of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a block diagram showing one embodiment of the present invention.
The individual circuit blocks of FIG. 1 are formed on a single
semiconductor substrate of single-crystal silicon or the like, although
not necessarily limited thereto by a well-known technique of fabricating a
semiconductor integrated circuit. The major circuit blocks of FIG. 1 are
drawn to coincide and be consistent with the actual geometrical
arrangement on one chip.
To the semiconductor memory of this embodiment, although not specifically
limited thereto, individual circuits for realizing the serial input/output
function for image processing actions, as will be described hereinafter,
are added by using as a basic component the memory array of a dynamic RAM
to be accessed at a unit of 1 bit (i.e., x 1 bit structure).
In the case where signals of 4 bits of red, blue, green and brightness are
to be stored, for example, for color image processings, memory arrays
M-ARY, a random input/output circuit I/O and a serial input/output circuit
SIO of FIG. 1 are formed with respect to constructing four groups so as to
correspond to the aforementioned respective signals.
In this embodiment, although not specifically limited thereto, a pair of
memory arrays M-ARY0 and M-ARY1 are arranged symmetrically with respect to
a column decoder C-DCR. Between this column decoder C-DCR and the paired
memory arrays M-ARY0 and M-ARY1, respectively, there are arranged random
input/output selectors C-SW0 and C-SW1, serial input/output selectors
SR&SW0 and SR&SW1, parallel transfer switch circuits S-SW0 and S-SW1 and
latch circuits DFF0 and DFF1, as will be described hereinafter.
The memory arrays M-ARY0 and M-ARY1 include matrix-arranged one-MOSFET type
dynamic memory cells and are constructed into the folded bit line type, in
which paired data lines (i.e., complementary data lines) are arranged in
parallel. The complementary data lines are extended transversely of FIG.
1. Each complementary data line is equipped with a precharge circuit, a
sense amplifier and an active restore circuit, although not shown. It
should be understood that these individual circuits can be included in
each of the memory arrays M-ARY0 and M-ARY1 of FIG. 1. A word line is so
extended longitudinally of FIG. 1 as to be connected with a row address
decoder R-DCR1 or R-DCR2 at its one end and to intersect each
complementary data line. This memory array construction is omitted in
detail because it is similar to that of a known dynamic RAM.
The complementary data lines of the aforementioned memory arrays M-ARY0 and
M-ARY1 are connected at their one-side ends through the column switch
circuits C-SW0 and C-SW1 with random input/output common data lines CD0
and CD1, respectively. The column switch circuits C-SW0 and C-SW1 connect
the complementary data lines selectively with the common data line CD0 or
CD1 in accordance with the signal which is generated on the basis of a
decode signal of the column address signal fed from the column decoder
C-DCR when in a random access mode.
The aforementioned complementary data lines are coupled at their other ends
through parallel transfer switch circuits S-SW0 and S-SW1 with the
input/output terminals of data holding latch circuits DFF0 and DFF1. These
latch circuits DFF0 and DFF1 have their input/output terminals connected
with serial input/output common data lines CD'0 and CD'1, respectively,
through the respective switch circuits SW of the serial input/output
selectors SR&SW0 and SR&SW1 each of which is composed of the switch
circuit SW and a shift register SR.
In a data transfer mode, data are transferred (or inputted and outputted)
in parallel between the memory array M-ARY0 or M-ARY1 and the latch
circuit DFF through the switch circuit S-SW0 or S-SW1 which is turned on
in response to a signal .0.s(.0..sub.S1 or .0..sub.S2). On the other hand,
data are transferred (or inputted and outputted) in series between the
latch circuit DFF and the common data lines CD'0 and CD'1. The serial data
input/output are transferred and as a result the switch circuit SW
connects the 1 bit (i.e., the unit circuit) of the latch circuit DFF
sequentially with the common data lines CD'0 and CD'1 in accordance with
the output signal of the shift register SR.
In this embodiment, in order to enable the serial input/output to start
from an arbitrary bit, the final-stage output signal of the shift register
SR is fed back to the side of an initial-stage circuit. This causes the
shift register SR to conduct a ring-shaped shifting action. The shift
register SR has its initial value set (or the signal at a logic level "1"
is located) by the decode signal of a column address signal fed from the
column decoder C-DCR when in a later-described serial transfer mode. In
other words, in the shift register SR, the selection signal of the logic
"1" is set at a bit corresponding to the complementary data line of the
memory array indicated by the column address signal. The shift register SR
conducts the shift operation of the selection signal (at the logic "1"in
response to shift clock signals .0.0 and .0.1 generated by the timing
control circuit TC on the basis of the clock signal fed from an external
terminal CLK. In this case, the shift clock signals .0.0 and .0.1 are made
to have a period two times as long as that of the clock signal fed from
the external terminal CLK and to have a half-period phase difference. As a
result, the signals of the left and right memory arrays M-ARY0 and M-ARY1
are outputted alternately in series. Thus, the shift action of the shift
register SR can be effected with one half of the frequency of the clock
signal CLK. This means that the serial signal can be inputted and
outputted with a frequency two times as high as that of the upper limit
action frequency, as viewed from the side of the shift register SR.
The aforementioned common data lines CD0 and CD1 are coupled to a random
input/output terminal D through the random input/output circuit I/O which
is constructed of an output circuit composed of a main amplifier and a
data output buffer and an input circuit composed of a data input buffer.
The aforementioned common data lines CD'0 and CD'1 are coupled to a serial
input/output terminal DS through the serial input/output circuit SIO which
is constructed of an output circuit composed of a main amplifier and a
data output buffer and an input circuit composed of a data input buffer.
Each of the aforementioned serial input/output circuits is constructed of
a static circuit.
A row address buffer R-ADB latches external address signals AX0 to AXn in
synchronism with a not-shown timing signal generated by a row-address
strobe signal RAS to generate internal complementary address signals ax0
to axn to be transmitted to the row address decoders R-DCR0 and R-DCR1.
The row address decoders R-DCR0 and R-DCR1 decode the address signals ax0
to axn and select a predetermined word line (and dummy word line) in
synchronism with a not-shown word line selection timing signal.
In synchronism with a not-shown timing signal generated by a column address
strobe signal CAS fed later than the signal RAS, a column address buffer
C-ADB latches external address signals AY0 to AYn to transmit internal
complementary address signals ay0 to ayn generated on the basis of the
latches to the column address decoder C-DCR. This column address decoder
C-DCR decodes the address signals ay0 to ayn and selects the data lines in
synchronism with a not-shown data line selection (or column switch
selection) timing signal. In a later-described parallel transfer mode of
the data of the memory array, the decode output corresponding to the
aforementioned data line selection signal of the column address decoder
C-DCR is used to produce the initial value (i.e., the logic "1") of the
aforementioned shift register SR.
The timing control circuit TC discriminates the action mode and generates a
plurality of corresponding timing signals in response to the address
strobe signals RAS and CAS, a write enable signal WE, a data transfer and
output enable signal DT/OE, and the clock signal CLK used for the serial
input/output actions, which are fed from the external terminals.
As has been described hereinbefore, the memory arrays M-ARY0 and M-ARY1 and
the individual circuit blocks arranged between the former, as shown in
FIG. 1, are actually arranged in such a geometric form on one chip. More
specifically, in order to use the output of the column decoder C-DCR
commonly for the column switch C-SW and the shift register SR, circuits
for the random input/output and serial input/output are interposed between
the memory array M-ARY and the column decoder C-DCR. The column switch
C-SW is provided as the random input/output circuit, and the parallel
transfer switch circuit S-SW, the latch circuit DFF, and the shift
register and switch circuit SR&SW are provided as the serial input/output
circuit. The order of arrangement of these individual circuit blocks can
be altered. Moreover, the column decoder is provided commonly for and at
the center of the two (or more) memory arrays or the random and serial
input/output circuits. This makes it possible to effect the random
input/output and the serial input/output, to enhance their functions, and
to improve the integration.
FIG. 2 is a circuit diagram showing one specific embodiment of each of the
aforementioned random input/output and serial input/output circuits. In
FIG. 2, P-channel MOSFETs are discriminated from N-channel MOSFETs by
adding arrows to their channel portions.
In the block diagram of FIG. 1, moreover, each circuit block has a numeral
added thereto for discrimination because it is paired. However, the
numerals for discriminating the paired circuits are omitted from the
embodiment circuit of FIG. 2 by constructing the paired circuits of an
identical circuit although they are differently arranged.
The aforementioned memory array M-ARY includes a dynamic cell having a
matrix arrangement and composed of an address selecting MOSFET (i.e.,
Insulated Gate type Field Effect Transistor) Qm and an information storing
capacitor Cs. The address selecting MOSFET Qm of the aforementioned memory
cell has its gate coupled to a corresponding word line W and its drain
coupled to a data line D. The word line W and the data line D are
constructed of the well-known folded bit line (or digit line) type, and
the drain of the address selecting MOSFET Qm of the memory cell is coupled
to corresponding complementary one D or D of a pair of data lines arranged
in parallel, i.e., complementary data lines D and D.
The complementary data lines D0 and D0 shown as representatives are
connected with random input/output common complementary data lines CD and
CD through switch MOSFETs Q16 and Q17 constructing a random input/output
unit column switch circuit UC-SW. These switch MOSFETs Q16 and Q17 have
their gates fed with a signal Y0 which is inverted from the selection
output signal Y0 of the column decoder C-DCR by a CMOS inverter N7.
The complementary data lines D0 and DO in the aforementioned memory array
M-ARY are coupled, on the other hand, to the input/output nodes N0 and N0
of a unit data latch circuit UDFF through the MOSFETS Q5 and Q6 composing
a unit parallel transfer switch circuit US-SW. The MOSFETs Q5 and Q6 have
their gates fed together with other similar MOSFETs with the transfer
timing signal .0.s, by which they are switched.
The unit latch circuit UDFF is constructed, although not necessarily
limited thereto, by crossly connecting the inputs and outputs of two CMOS
inverters composed of the N-channel MOSFETs Q7 and Q9 and the P-channel
MOSFETs Q8 and Q10.
The paired input/output nodes N0 and N0 of the unit latch circuit UDFF are
connected, on the other hand, with serial input/output common data lines
CD' and CD' through the switch MOSFETs Q1 and Q2 composing the serial
input/output unit switch circuit SW. The common gate of those switch
MOSFETs Q1 and Q2 is fed with the output signal SL0 of a unit circuit USR
(i.e., the unit circuit corresponding to the complementary data lines D0
and D0) of the shift register SR as the selection signal.
The unit shift registers USR has its front-stage half bit circuit composed
of two CMOS inverters N1 and N2 like the aforementioned unit latch circuit
UDFF, and the P-channel transmission gate MOSFET Q12 for transmitting
their output signals to a rear-stage half bit circuit. Incidentally, in
the unit circuit USR, the feedback inverter N2 is designed so that the
conductance of the MOSFET composing it is reduced. As a result, the input
signal of the inverter N1 is set at the level according to the signal
transferred from the front stage through the N-channel transmission gate
MOSFET Q11. In other words, the output signal of the inverter N1 is
inverted by the signal fed through the MOSFET Q11. The rear-stage half bit
circuit receiving the signal transferred by the aforementioned P-channel
type transmission gate MOSFET Q12 is also composed of CMOS inverters N3
and N4 similar to the above ones and the N-channel type transmission gate
MOSFET Q13. The aforementioned signal transmission MOSFETs Q11 to Q13 have
their gates fed commonly with the aforementioned shift clock signal .0..
The signal at the input terminal of the aforementioned rear-half bit
circuit is transmitted as the selection signal SL0 to the gates of the
aforementioned switch MOSFETs Q1 and Q2. Incidentally, inverters N5 and N6
construct a unit circuit of a next-stage shift register. The final-stage
output of the shift register does not pass through the transmission gate
MOSFET corresponding to the transmission gate MOSFET Q13, but the output
of the inverter constructing the latch circuit is fed back to the MOSFET
Q11. The final-stage output is amplified and fed back by a drive circuit
(not shown), taking the wiring length for this feedback into
consideration.
For initial value setting, the aforementioned unit circuit USR is fed with
the output signal YO of the column decoder C-DCR through the switch MOSFET
Q15. In other words, the signal YO has a phase opposite the phase to
signal YO which is fed to the random input/output switch circuit UC-SW
corresponding to the unit circuit USR. The switch MOSFET Q15 is switched
together with another similar switch MOSFET Q14 by a preset timing signal
.0. set. If the output signal YO generated by the column decoder C-DCR,
for example, is a low-level (i.e., the logic "0") selection signal, this
low-level signal is latched in the front-stage circuit of the unit circuit
USR in synchronism with the present timing signal .0.set. Another unit
circuit is fed through the switch MOSFET Q14 or the like with a high-level
(i.e., the logic "1") non-selection signal such as an output signal Y1
generated by the column decoder C-DCR. The signal Y1 which is inverted
from the signal Y1 is fed to the gates of MOSFETs (not shown) which
comprise the unit circuit US-SW corresponding to the MOSFET Q14.
Incidentally, in the case where the column decoder C-DCR consists of a
NAND gate circuit using the high-level (i.e., the logic "1") selection
signal, its output signal is fed to the gates of the MOSFETs Q16 and Q17
of the column switch such as illustrated. On the other hand, a signal
inverted from the output signal of the column decoder C-DCR in accordance
with the data selection timing signal is fed as an initial value to the
shift register SR. In the case, where one of the switch circuits US-SW and
SW comprises an N-channel MOSFET only and the other a P-channel MOSFET,
the signal having the same phase outputted from the column decoder C-DCR
can be used as the selection signal.
The operations of this unit shift register USR is as follows. When the
clock signal .0. is at the high level, the N-channel type transmission
gate MOSFETs Q11 and Q13 are turned on to effect the half-bit shift
action. For example, the low-level selection signal is transferred from
the front-stage circuit through the MOSFET Q11 to the input terminal of
the inverter circuit N1. Simultaneously with this, the output signal
(i.e., the high-level non-selection signal) of the inverter N3 is
transferred through the MOSFET Q13 to the next-stage circuit.
Subsequently, when the clock signal .0. varies to the low level, the
N-channel MOSFETs Q11 and Q13 are turned off whereas the P-channel MOSFET
Q12 is turned on so that the output signal (at the high level) of the
inverter N1 is transmitted to the input side of the next half-bit circuit.
As a result, the switch MOSFETs Q1 and Q2 are turned on so that the signal
latched in the unit latch circuit UDFF is transferred to the common data
lines CD' and CD' and outputted to the external terminals DS through the
not-shown main amplifier and output circuit.
Next, when the clock signal .0. restores the high level, the high-level
non-selection signal is transferred to the input of the inverter N1 from
the front-stage circuit. Simultaneously with this, the low-level selection
signal is transferred from the output of the inverter N3 to the next-stage
circuit. When the clock signal .0. is changed to the low level, moreover,
this low level is transmitted to the input of the inverter N3. As a
result, the switch MOSFETs Q1 and Q2 are turned off whereas the unit
switch MOSFET of the switch circuit SW corresponding to the next-stage
circuit is turned on so that the latch signal of the unit latch circuit
UDFF corresponding to the next-stage circuit is transferred to the common
data lines CD' and CD'. The serial output actions are conducted by
subsequently repeating similar actions.
On the other hand, the serial input actions can be conducted by controlling
the operation of the shift register SR similar to the aforementioned ones.
Input data synchronized with the clock signal .0. are continuously fed to
the common data lines CD' and CD' through the serial input/output circuit
from the serial input/output terminal DS. In synchronism with the clock
signal .0., the common data lines CD' and CD' are sequentially connected
with the unit latch circuit UDFF selected by the output of the shift
register SR to latch the input data. Incidentally, in the case where an
initial value such as the aforementioned one is set, the high-level
selection signal SLO is generated in synchronism with the low level of the
clock signal .0..
One example of the operation of the semiconductor memory of the present
embodiment will be briefly described with reference to the timing charts
shown in FIGS. 3 and 4.
The semiconductor memory of this embodiment is enabled for both random
input/output and serial input/output operation, and wherein serial
input/output and the random input/output opera | | |
