A method for passivating the surface of a compound semiconductor comprises annealing the substrate to form an anion rich surface layer containing cationic and anionic oxides and stripping the oxides to leave only a very thin anionic layer on the surface. The substrate is then subjected to an H.sub.2 plasma cleaning to remove chemisorbed oxygen. An N.sub.2 plasma cleaning is then performed to form an anionic nitride layer that is free of any cationic nitride. A layer of insulating material, such as, a native or other oxide, or a nitride, is deposited. The resulting structure has a very low interface state density such that the Fermi level may be swept through the entire band gap.
A method of forming a dielectric layer on a supporting structure of III-V material having a clean and atomically ordered surface to be coated with a dielectric layer including the step of depositing a layer of Ga.sub.2 O.sub.3, having a sublimation temperature, on the surface of the supporting structure by evaporation using a high purity single crystal of material including Ga.sub.2 O.sub.3 and a second oxide with a melting point greater than 700.degree. C. above the sublimation temperature of the Ga.sub.2 O.sub.3. The evaporation can be performed by any one of thermal evaporation, electron beam evaporation, and laser ablation.
A semiconductor device including a GaAs semiconductor substrate, an insulating layer which is made of material selected from the group MgS, MgSSe and CaZnS and is formed on the GaAs substrate, and a conductive electrode formed on the insulating layer.
A method of thermal processing a supporting structure comprised of various compound semiconductor layers having a Gd free Ga.sub.2 O.sub.3 surface layer including coating the surface layer with a dielectric or a metallic cap layer or combinations thereof, such that the low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure is conserved during thermal processing, e.g. during activation of ion implants of a self aligned metal-oxide-compound semiconductor gate structure. In a preferred embodiment, the semiconductor structure has a surface of GaAs, the Gd free Ga.sub.2 O.sub.3 layer has a thickness in a range of approximately 1 nm to 20 nm, and the insulating or metallic cap layer has a thickness in a range of approximately 1 nm to 500 nm.
Applicants have discovered that gallium arsenide surfaces can be dry passivated without heating or ion bombardment by exposing them downstream to ammonia plasma formation. Specifically, a workpiece having exposed gallium arsenide surfaces is passivated by placing the workpiece in an evacuable chamber, evacuating in the chamber, generating an ammonia plasma removed from the immediate vicinity of the workpiece, and causing the plasma products to flow downstream into contact with the workpiece. Preferably the plasma gas pressure is 0.5 to 6.0 Torr, the substrate temperature is less than 100.degree. C. and the time of exposure is in excess of 5 min. The plasma should be generated at a location sufficiently removed from the workpiece that the workpiece surface is not bombarded with ions capable of damaging the surface (more than about 10 cm) and sufficiently close to the workpiece that reactive plasma products exist in the flow (within about 30 cm). The workpiece should also not be placed within line-of-sight of the plasma to avoid radiation (UV, visible and X-ray) induced damage. The result is fast, stable, room temperature passivation, compatible with clustered dry processing techniques for integrated circuit manufacture.
Disclosed is a rocket engine having a low operating mode in which propellants are provided to the combustion chamber by the combined effect of boost pumps and the pressure differential between the propellant tanks and the combustion chamber, and a high operating mode in which primary pumps further increase the pressure at which propellant is provided to the combustion chamber.
