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Claims  |
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What is claimed is:
1. A logic circuit, comprising:
a system bus; and
a plurality of logic modules, at least one of said modules comprising:
functional circuitry connected to said system bus;
a shift input for receiving a shift signal;
a plurality of data latches, each of said data latches connected to a
predetermined location in said functional circuitry, and said plurality of
data latches serially interconnected so that the data stored in said data
latches shift in series responsive to said shift signal;
a scan data input, connected to a first one of said plurality of data
latches;
a scan data output;
a module enable latch for storing a first logic state corresponding to its
module being enable, and for storing a second logic state corresponding to
its module not being enabled;
bypass means, connected to said module enable latch, to said scan data
output, and to a second one of said plurality of data latches for
connecting said second one of said plurality of data latches to said scan
data output responsive to said module enable latch storing said first
logic state, and for disconnnecting said second one of said plurality of
data latches from said scan data output responsive to said module enable
latch storing said second logic state; and
bus control means, connected to said scan data input and to said functional
circuitry, for disconnecting said functional circuitry from said system
bus responsive to data received at said scan data input.
2. The logic circuit of claim 1, wherein said bus control means comprises:
a bus control latch, connected to said scan data input, for storing a logic
state; and
buffer means, connected between said functional circuitry and said system
bus, and connected to said bus control latch so that said functional
circuitry is connected to, or disconnected from, said system bus
responsive to the data stored in said bus control latch.
3. The logic circuit of claim 1, wherein said bypass means is further
connected to said scan data input, and is for connecting said scan data
input to said scan data output responsive to said module enable latch
storing its second logic state.
4. The logic circuit of claim 1, wherein said one of said modules further
comprises:
an enable signal input, connected to said module enable latch, for
receiving a module enable signal indicating whether or not its module is
to be enabled; and
an enable signal output, connected to said module enable latch for
outputting the logic state stored by said module enable latch.
5. The logic circuit of claim 4, wherein the enable signal output of a
first one of said modules is connected to the enable signal input of a
second one of said modules.
6. The logic circuit of claim 5, wherein said one of said modules further
comprises:
an enable shift input for receiving an enable shift signal, said enable
shift input connected to said module enable latch;
and wherein each module enable latch is loaded with the logic state
corresponding to its enable signal input responsive to said enable shift
signal.
7. The logic circuit of claim 6, wherein said bypass means comprises:
a bypass latch having an output connected to said scan output; and
control logic having a first input connected to said module enable latch,
having a second input connected to said second data latch, having a third
input connected to said scan input and having an output coupled to said
bypass latch so that said bypass latch stores data corresponding to said
second data latch responsive to said module enable latch storing said
first logic state, and corresponding to said scan data input responsive to
said module enable latch storing said second logic state.
8. The logic circuit of claim 7, wherein said bus control means comprises:
buffer means, connected between said functional circuitry and said system
bus, and connected to said bypass latch so that said functional circuitry
is connected to, or disconnected from, said system bus responsive to the
data stored in said bus control latch.
9. The logic circuit of claim 8, wherein said one of said modules further
comprises:
a scan enable input for receiving a scan enable signal indicating whether
or not said logic circuit is in a scan mode, said scan mode corresponding
to data being scanned from module to module in said logic circuit;
and wherein said bypass means further comprises:
buffer control logic, having a first input connected to said bypass latch,
having a second input connected to said scan enable input, and having an
output connected to said buffer means, so that said buffer means also
disconnects said functional circuitry from said system bus responsive to
said scan enable signal indicating that said logic circuit is in said scan
mode.
10. The logic circuit of claim 8, wherein said one of said modules further
comprises:
a test control input for receiving a test control signal indicating whether
said logic circuit is in a normal operating mode or in a test mode;
and wherein said bus control means further comprises:
buffer control logic, having a first input connected to said bypass latch,
having a second input connected to said test control input, and having an
output connected to said buffer means, so that said buffer means
disconnects said functional circuitry from said system bus responsive to
said test control signal indicating that said logic circuit is in said
test mode, depending upon the data stored in said bypass latch.
11. The logic circuit of claim 7, said bypass means further comprises:
a gate, having inputs connected to said module enable latch and to said
shift signal, and having its output connected to each of said plurality of
latches, for disabling said shift signal from causing the data in said
data latches from shifting in series therethrough responsive to said
module enable latch storing said second logic state.
12. A logic circuit comprised of a plurality of modules, at least one of
said modules comprising:
functional circuitry for performing a predetermined logic function;
a shift input for receiving a shift signal;
a scan data input;
a scan data output;
a global data latch, connected to a predetermined location in said
functional circuitry;
a local data latch, connected to a predetermined location in said
functional circuitry, and connected in series with said global data latch,
said scan data input and said scan data output so that the data stored in
said global and local data latches shift in series from said scan data
input to said scan data output responsive to said shift signal;
a module enable latch for storing a first logic state corresponding to its
module being enabled, and for storing a second logic state corresponding
to its module not being enabled; and
bypass means, connected to said module enable latch and connected to said
local data latch, for disconnecting said local data latch from said series
responsive to said module enable latch storing its second data state, so
that data shifts from said scan data input through said global data latch
to said scan data output responsive to said shift signal.
13. The logic circuit of claim 12, wheren said global data latch is
connected to said scan data input;
and wherein said local data latch is connected in series between said
global data latch and said scan data output.
14. A logic circuit comprised of a plurality of modules, at least one of
said modules comprising:
functional circuitry for performing a predetermined logic function;
a shift input for receiving a shift signal;
a scan data input;
a scan data output;
a plurality of global data latches, each global data latch connected to a
predetermined location in said functional circuitry, said plurality of
global data latches connected in series so that data shifts therethrough
responsive to said shift signal;
a plurality of local data latches, each local data latch connected to a
predetermined location in said functional circuitry, said plurality of
local data latches connected in series with said plurality of global data
latches, with said scan data input and with said scan data output so that
the data stored in said global and local data latches shift in series from
said scan data input to said scan data output responsive to said shift
signal;
a module enable latch for storing a first logic state corresponding to its
module being enabled, and for storing a second logic state corresponding
to its module not being enabled; and
bypass means, connected to said module enable latch and connected to said
plurality of local data latches, for disconnecting said local data latches
from said series responsive to said module enable latch storing its second
data state, so that data shifts from said scan data input through said
plurality of global data latches to said scan data output responsive said
shift signal.
15. The logic circuit of claim 14, wherein the first of said global data
latches in said series is connected to said scan data input;
wherein the last of said global data latches in said series is connected to
said first of said local data latches in said series;
and wherein said bypass means is connected to said last of said global data
latches in said series, to the last of said local data latches in said
series, and to said scan data output, said bypass means for connecting
said last of said global data latches to said scan data output responsive
to said module enable latch storing its second data state, and for
connecting said last of said local data latches to said scan data output
responsive to said module enable latch storing its first data state.
16. The logic circuit of claim 15, wherein said bypass means is also for
disconnecting said first of said local data latches from said last of said
global data latches responsive to said module enable signal storing said
second logic state.
17. The logic circuit of claim 16, wherein said bypass means is also for
disabling said plurality of data latches from shifting data stored therein
responsive to said module enable signal storing said second logic state.
18. A modular logic circuit, wherein at least one of said modules
comprises:
functional circuitry;
a scan input;
a data shift input for receiving a data shift signal;
a plurality of data latches, a first of said data latches connected to said
scan data input, each of said data latches connected to a predetermined
location in said functional circuitry, and said plurality of data latches
serially interconnected so that the contents of said data latches shifts
in series responsive to said data shift signal;
a module enable latch, connected to said scan input and receiving a module
enable load signal, for storing the logic state of said scan data input
responsive to said module enable load signal, a first logic state of said
scan data input corresponding to the module being selected and a second
logic state of said scan data input corresponding to the module not being
selected;
a scan output;
an output multiplexer having a first input connected to said module enable
latch, having a second input, having an output connected to said scan
output, and having a select input for receiving a scan/select signal, so
that said module enable latch is connected to said scan output responsive
to said scan/select signal being at a first logic state; and
bypass logic, connected between the last of said data latches in said
series and the second input of said output multiplexer, and controlled by
said module enable latch so that said last of said data latches is
connected to said second input of said output multiplexer responsive to
said module enable latch storing said first logic state, and so that said
last of said data latches is disconnected from said second input of said
output multiplexer responsive to said module enable latch storing said
second logic state.
19. The logic circuit of claim 18, wherein the scan output of a first one
of said modules is connected to the scan input of a second one of said
modules.
20. The logic circuit of claim 18, wherein said bypass logic is also
connected between said scan input and the first of said data latches in
said series, and is for disconnecting said first data latch from said scan
input responsive to said module enable signal storing said second logic
state.
21. The logic circuit of claim 18, wherein said one of said modules further
comprises:
a global data latch, connected to a predetermined location in said
functional circuitry, and connected in series between said scan input and
said series of data latches so that data shifts therethrough responsive to
said shift signal;
and wherein said bypass logic is also connected to said global data latch,
and is for connecting said global data latch to said second input of said
output multiplexer responsive to said module enable latch storing said
second logic state.
22. The logic circuit of claim 18, wherein said one of said modules further
comprises:
a plurality of global data latches, each connected to a predetermined
location in said functional circuitry, and connected in a series so that
the data stored in said global data latches shift in series responsive to
said shift signal, the first global data latch in said series connected to
said scan input and the last of said global data latches connected to said
first of said data latches in said series;
and wherein said bypass logic is connected to said last of said global data
latches so that, responsive to said module enable latch storing said
second logic state, a second global data latch of such series is connected
to said second input of said output multiplexer.
23. A modular logic circuit, comprising:
a first logic module, comprising:
functional circuitry;
a module scan input;
a module scan output;
a shift input for receiving a shift signal;
a plurality of data latches, each of said data latches connected to a
predetermined location in said functional circuitry, and said plurality of
data latches serially interconnected so that the data stored in said data
latches shift in series responsive to said shift signal, the first data
latch in said series connected to said scan data input; a module enable
latch for storing a first logic state corresponding to said first module
being enabled, and for storing a second logic state corresponding to said
first module not being enabled; and
bypass means, connected to said module enable latch, to said module scan
output and to the last data latch in said series, for connecting said last
data latch to said module scan output responsive to said module enable
latch storing said first logic state, and for connecting said module scan
input to said module scan output responsive to said module enable latch
storing said second logic state; and
a second logic module, comprising:
functional circuitry;
a module scan input, connected to said module scan output of said first
module;
a module scan output;
a shift input for receiving a shift signal;
a plurality of data latches, each of said data latches connected to a
predetermined location in said functional circuitry, and said plurality of
data latches serially interconnected so that the data stored in said data
latches shift in series responsive to said shift signal, the second data
latch in said series connected to said scan data input;
a module enable latch for storing a first logic state corresponding to said
second module being enabled, and for storing a second logic state
corresponding to said second module not being enabled; and
bypass means, connected to said module enable latch, to said module scan
output and to the last data latch in said series, for connecting said last
data latch to said module scan output responsive to said module enable
latch storing said first logic state, and for connecting said module scan
input to said module scan output responsive to said module enable latch
storing said second logic state.
24. The logic circuit of claim 23, wherein said module enable latches in
said first and second modules each have an input and an output, and are
controlled by said shift signal;
and wherein the input of said module enable latch in said second module is
connected to the output of said module enable latch in said first module,
so that data shifts through said module enable latches in series
responsive to said shift signal.
25. The logic circuit of claim 24, wherein said bypass means in each of
said first and second modules comprises:
a bypass latch having an output connected to said module scan output; and
control logic having a first input connected to said module enable latch,
having a second input connected to said last data latch in said series,
having a third input connected to said scan input and having an output
coupled to said bypass latch so that said bypass latch stores data
corresponding to said last data latch in said series responsive to said
module enable latch storing said first logic state, and stores data
corresponding to said module scan input responsive to said module enable
latch storing said second logic state.
26. A logic circuit including plural logic modules that each perform
certain logical operations, the modules being connected together over a
system bus that includes data, address and control leads, said logic
circuit comprising:
a test port connected to each logic module, each test port having a serial
data input lead, a serial data output lead and plural control leads, the
serial data input and output leads of said plural modules being connected
together in series, and a test bus of control leads separate from said
system bus and connected to the control leads of every test port, control
signals on said test bus control leads determining the passage of data at
said test ports over said serial input and output leads.
27. The logic circuit of claim 26 in which each test port includes a module
enable latch storing the state of a module enable signal.
28. The logic circuit of claim 27 in which said test bus control leads
include a select shift lead, a test enable lead and a scan enable lead,
the select shift lead connecting to said module enable latch and carrying
a select shift signal that loads the state of said module enable signal
into said module enable latch, the test enable lead carrying a test enable
signal that controls connection of the logic module to the system bus and
the scan enable lead carrying a scan enable signal that enables data to be
scanned through serial register latches of each logic module without
interference by and to said system bus.
29. The logic circuit of claim 27 in which each test port includes a module
enable input lead and a module enable output lead both connected to said
module enable latch, and the module enable input and output leads of said
plural modules are connected together serially.
30. The logic circuit of claim 27 in which said serial data input and
output leads connect to said module enable latch and carry multiplexed
test pattern data and module enable data.
31. The logic circuit of claim 30 in which said test port includes a
multiplexer having one output connected to said serial data output lead,
said serial data input lead connecting to said module enable latch and a
series of register latches, said multiplexer having one input connected to
an output of said module enable latch and another input connected to an
output of said series of register latches and said test bus including a
scan and select lead connected to said multiplexer to control application
of said one and another input to said output.
32. The logic circuit of claim 28 including a buffer connected between each
logic module and said system bus for electrically isolating said logic
module for said system bus and said buffer being coupled to said test
enable lead and said scan enable lead by gating for control by said test
enable and scan enable signals.
33. The logic of claim 27 in which each said logic module includes a series
of register latches serially connected between said serial data input and
output leads and a group of said serial register latches having at least
an output connected to said serial data output lead when said module
enable signal stored in said module enable latch disables the remainder of
said serial register latches from said serial data output lead.
34. The logic circuit of claim 26 including a decoder connected to said
test bus control leads and external terminals, said decoder receiving
signals from said external terminals and producing signals on said test
bus control leads.
35. The logic circuit of claim 26 in which said logic modules include a
central processing unit, a system bus controller and an interface. |
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Claims |
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Description |
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This application is in the field of electronic digital logic circuits, and
specifically is directed to circuits which enhance the testability of such
logic circuits.
As the technology for manufacturing integrated circuits advances, more and
more logic functions may be included in a single integrated circuit
device. Modern integrated circuit devices include over 100,000 transistors
on a single semiconductor chip, with these transistors interconnected so
as to perform multiple and complex functions such as those in a
general-purpose microprocessor. The manufacture of such circuits
incorporating such Very Large Scale Integration (VLSI) requires, however,
that no errors exist in the design of the circuit, and that no
manufacturing defect was generated during its manufacture, which preclude
it from performing all of the functions that it is intended to perform.
This requires verification of the designed circuit prior to its
manufacture and also electrical testing of each manufactured circuit.
However, as the complexity of the circuit increases, so does the cost and
difficulty of verifying and electrically testing each of the devices in
the circuit. From an electrical test standpoint, in order to totally
verify that each of the transistors in the VLSI circuit properly function,
one must theoretically be able to exercise each of the transistors not
only individually (in the digital sense, determining that it is neither
stuck-open or stuck-closed), but also in conjunction with the other
transistors in the circuit in all possible combinations of operation. In
addition, specific circuit configurations in the VLSI circuit may have
some of its transistors inaccessible for all but a special combination,
thereby hiding a fault unless a very specific pattern of signals is
presented. However, the cost of performing such testing on 100% of the
manufactured circuits is staggering, considering the high cost of the test
equipment required to exercise each circuit in conjunction with the long
time required to present each possible combination to each transistor.
This has in the past forced integrated circuit manufacturers to test less
than all of the active devices in a chip, with the quality levels of the
product becoming less than optimal.
Circuit designers have used stuck-fault modeling techniques in improving
the efficiency of the testing of such VLSI circuits. Stuck-fault modeling
is directed not to stuck-open or stuck-closed defects in individual
transistors, but to the effect of such defective transistors (and
defective interconnections) resulting stuck-high and stuck-low outputs of
the logic circuit. Minimum test patterns are then derived for the
exercising of the logic circuit, such test patterns being inputs to the
circuit designed to cause stuck-high and stuck-low outputs if defects are
present. Such techniques have been successful in improving the test
efficiency of VLSI circuits.
In conjunction with the stuck-fault modeling and associated pattern
generation, cooperative circuitry may be included in the VLSI circuit
specifically directed to improving its testability. One configuration of
this cooperative circuitry is a scan path in the logic circuit. The scan
path consists of a series of synchronously clocked master/slave latches,
each of which is connected to a particular node in the logic circuit.
These latches can be loaded with a serial data stream ("scan in") and can
present their contents to the nodes in the logic circuit, presetting the
logic circuit nodes to a predetermined state. The logic circuit then can
be exercised in normal fashion, with the result of the operation at the
latch nodes stored in the latches. By serially unloading the contents of
the latches ("scan out"), the result of the operation at the associated
nodes is read. Repetition of this operation with a number of different
data patterns effectively tests all necessary combinations of the logic
circuit, at reduced test time and cost. Techniques for scanning such data
are discussed by E. J. McCluskey in "A Survey of Design for Testability
Scan Techiques", VLSI Design (Vol. 5, No. 12, pp. 38-61, December 1984).
Also as this technology is advancing, users of integrated circuits are
desiring specially designed and constructed integrated circuits, for
performing functions specific for the user's application. The genre of
such integrated circuits has been termed Application Specific Integrated
Circuits (ASIC). For an ASIC device to be cost-competitive with general
purpose microcomputers which may have the special function software
programmable, and cost-competitive with a board design made up of smaller
scale integrated circuits, the design time of the ASIC circuit must be
short and the ASIC circuit must be manufacturable at a low cost.
Accordingly, it is useful for such circuits to be modular in design, with
each of the modules performing a certain function, so that a new circuit
may be constructed for a specific purpose by the combining of
previously-designed circuit modules. Such an approach can also be used for
non-ASIC microcomputers and microprocessors. Regardless of the end
product, the use of a modular approach allows the designer to use logic
which has previously been verified, and already been proven as
manufacturable. However, if logic modules which utilize a single scan path
in their original placement in an integrated circuit, are placed into a
new circuit application, new test patterns will be required for the new
device, thereby lengthening the design/manufacture cycle time. In
addition, the destruction of the original scan path may reduce the
effectiveness of the scan path in the new device.
As described in patent numbers 4,710,933, 4,710,931, 4,701,921 and
4,698,588 all filed October 23, 1985 and all assigned to Texas Instruments
Incorporated, a modular approach to utilizing scan paths and other
testability circuits has been used and provides thorough coverage of all
possible faults in an efficient manner. However, the described approach
utilizes system buses to set up and operate the scan test, so that even
though each of the modules is tested independently, the test pattern
designed for a given module depends upon the operation of other modules in
the logic circuit for purposes of bus control and module selection. This
results in the testability of a particular module depending upon the
fault-free operation of other modules. In addition, the test equipment
computer program which sets the conditions for test of a given module
depends upon the position of the module relative to other modules, and
upon the operating features of such other modules. While reduced test time
and cost are thus achieved by such modularity, the use of system buses to
load and unload the scan paths in the individual modules not only may
affect the operation of the particular module, but is likely to also
preclude "porting" of the test pattern and program for a given module from
one logic circuit to another.
It is therefore an object of this invention to provide a test port for a
logic module, so that the test data and enabling of a scan path within the
module may be made independent of the functional architecture of the logic
circuit containing the module.
It is a further object of this invention to provide such a test port which
provides isolation of the particular logic module from other modules
during the test operation.
It is a further object of this invention to provide such a test port which
allows enabling of the module's scan path without requiring the operation
of other modules in the logic circuit.
It is a further object of this invention to provide such a test port which
can allow enabling of the scan path within a module while other module
scan paths are enabled.
It is a further object of this invention to provide such a test port which
uses a single clock to load the scan paths in all modules having the port.
Other objects and advantages of this invention will be apparent to those of
ordinary skill in this field, with reference to the following
specification and accompanying drawings.
SUMMARY OF THE INVENTION
The invention may be incorporated into a logic circuit which is organized
in a plurality of functional modules, and where communication among the
modules occurs via a system bus. Testing of a functional module occurs
through a scan path comprised of a series of data latches, each of the
latches connected to a node in the functional circuitry. The scan paths of
the modules are connected in a series among each other, so that a single
dynamically configurable scan path exists in the logic circuit. Data is
"scanned", or shifted, into the data latches for application to said
functional circuitry nodes; after the operation of the functional
circuitry, the latch data is scanned out for analysis of the results. The
modules further comprise a module enable latch which, when loaded with a
particular logic state, enables the scan path in the module. When the
module is not selected, the scan path is bypassed, so that data may be
scanned through the module to the selected module, without passing through
the scan paths of the unselected modules. The module enable latches may
themselves be interconnected into a scan path, separate from the data scan
path, so that the function of enabling the modules may be done externally
from the logic chip through a minimum of device pins, thereby not
requiring intervention of other portions of the logic circuit (e.g., the
CPU) in the selection of a module or modules for test. The module enable
scan path may have a separate input and output from the data scan path, or
it may be multiplexed with the data scan input and output of the device.
During the testing of a given module, the test port can also be operable
to disable the system bus from the functional circuitry in the module, so
that control of the system bus by the CPU or another module is not
required for performing the test function and so that the operation of
unselected modules does not interfere with a module under test.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a modular logic circuit according to the prior
art.
FIG. 2 is a block diagram of two of the modules in the logic circuit of
FIG. 1.
FIG. 3 is a schematic diagram of a serial register latch.
FIG. 3a is a timing diagram for clock signals used in operation of the
serial register latch of FIG. 3.
FIG. 4 is a block diagram of a modular logic circuit constructed according
to the invention.
FIG. 5 is a block diagram of two of the logic modules of FIG. 4 constructed
according to a first embodiment of the invention.
FIG. 6 is an electrical diagram, in schematic form, of one of the modules
shown in FIG. 5.
FIG. 6a is an electrical diagram, in schematic form, of another embodiment
of the module of FIG. 6.
FIG. 7 is a timing diagram illustrating the operation of the test function
of the first embodiment of the invention.
FIG. 8 is a block diagram of two logic modules constructed according to a
second embodiment of the invention.
FIG. 9 is an electrical diagram, in schematic form, of one of the modules
shown in FIG. 8.
FIG. 10 is a timing diagram illustrating the operation of the test function
of the second embodiment of the invention.
FIG. 11 is an electrical diagram, in schematic form, of another embodiment
of a module according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, logic circuit 10 is shown according to the prior art.
Logic circuit 10 of FIG. 1 is a microcomputer, having on-board memory
consisting of read-only memory (ROM) 7 and random access memory (RAM) 9.
Certain logic functions, such as timing, peripheral and communication
interfacing, and analog/digital conversion, is performed by logic modules
26a through 26c, each of which are connected to control bus 12, address
bus 16, and data input/output bus 20. Of course, any number of logic
modules 26 may be included in logic circuit 10 and connected to buses 12,
16 and 20; three such modules 26 are illustrated in FIG. 1 by way of
example. Access to buses 12, 16 and 20 is controlled by bus/system
controller 13, which itself is under the control of central processing
unit (CPU) 15. CPU 15 is a central processing unit for the execution of
programming instructions, as is well known in the art. CPU 15 is
controlled by control ROM 17, which is used to decode instructions
received from ROM 7 or RAM 9 via memory bus 11. CPU 15 is responsive to
the output of control ROM 17 to perform the desired operations according
to the decoded program instruction, including control of system/bus
controller 13 so that the necessary access to address bus 16 and data
input/output bus 20 by modules 26 occurs, via the appropriate signals on
control bus 12. External interface to logic circuit 10 is done by way of
terminals 18 shown in FIG. 1 as connected to modules 26 and system/bus
controller 13; external connection of course may also be made by way of
terminals 18 connected to the other portions of logic circuit 10,
depending upon the function to be carried out by logic circuit 10.
Logic circuit 10 of FIG. 1 has scan paths and associated circuitry
incorporated into modules 26 for facilitation of electrical test. The data
path into these scan paths is shown in FIG. 1 by the line SDI entering
module 26a, lines SDM serially interconnecting modules 26a, 26b and 26c,
and line SDO exiting module 26c. As disclosed in said patent numbers
4,710,933, 4,710,931, 4,701,921 and 4,698,588, lines SDI and SDO may
instead by configured as buses, by interconnection to each of modules 26
in logic circuit 10; the arrangement shown in FIG. 1 is by way of example
only.
A schematic diagram of an example of a scan path and associated circuitry
is shown in FIG. 2, in the context of two modules, 26a and 26b. As
disclosed in said patent numbers 4,710,933, 4,710,931, 4,701,921 and
4,698,588, each of the modules 26 are addressable for test purposes via
address bus 16, by way of address decoder/selector 52. Each of the modules
further include scan register latches (SRLs) 34a through 34n, the output
of each being connected to predetermined nodes in functional circuitry 31
of each of the modules 26. In module 26a, the input of SRL 34a is
connected to scan data in line SDI via buffer 48, and the output of SRL
34n is connected to scan data line SDM via buffer 50; similarly, in module
26b the input of SRL 34a is connected to scan data line SDM via its buffer
48, while the output of SLR 34n is connected to scan data out line SDO via
its buffer 50. In each module 26, buffers 48 and 50 are controlled by
address decoder/selector 52, which receives signals on address bus 16 and
control bus 12. Buffer 51 in module 26a is connected between line SDI and
line SDM, and is controlled by address decoder/selector with the same
signal as which controls buffers 48 and 50, after inversion by inverter
49. Similarly, buffer 51 in module 26b is connected between line SDM and
line SDO and is controlled by the inverter signal controlling buffers 48
and 50. It should be noted that functional circuitry 31 is also connected
to address bus 16 and control bus 12 for use in the normal operating mode
of module 26, although such connection is not shown in FIG. 2 for the sake
of clarity. Functional circuitry 31 is of course connected to data
input/output bus 20.
Within each module 26, SRLs 34 are serially interconnected so that data can
be shifted from buffer 48 through SRLs 34 to buffer 50, responsive to
shift clock signals appearing on line 54 shown in FIG. 2. Line 54 carries
one or more clock signals required for the serial communication of data
among SRLs 34, said clock signals generated from the system clock of logic
circuit 10. While a single line 54 is shown in FIG. 2 for the sake of
clarity, more than one line may bring in said clock signals, depending
upon the number of stages in each of SRLs 34. For example, if each of SRLs
34 are master/slave latches, two clock signals carried on two lines are
necessary. Line 54 may be one of the lines in control bus 12, or may be
otherwise brought in to modules 26.
In operation of the test sequence, control signals on control bus 12 will
be generated by system/bus controller 13, for receipt by address
decoder/selector 52 to indicate that logic circuit 10 is to be placed in
test mode. Address decoder/selector 52 in each module 26 will then decode
the the logic state of the lines of address bus 16 to determine if its
module 26 is being addressed. If its module 26 is being addressed, address
decoder/selector 52 will enable buffers 48 and 50 and, because of inverter
49, disable buffer 51. As an example, if module 26a were addressed with
module 26b not addressed in test mode, buffers 48 and 50 in module 26a
would be enabled (and buffer 51 in module 26a disabled) so that SRLs 34a
through 34n would be connected between lines SDI and line SDM. Buffers 48
and 50 in module 26b would be disabled and buffer 51 enabled therein,
module 26b not being addressed, so that SRLs 34a through 34n in modules
26b are effectively removed from the scan chain. The data on line SDM from
SRL 34n in module 26a would then appear on line SDO via buffer 51 of
module 26b. In this example, as described in said copending applications
S.N. 790,569, S.N. 790,543, S.N. 790,541 and S.N. 790,598, module 26a can
be tested by the scan chain of SRLs 34 therein, without requiring the
scanning of data through SRLs 34 in module 26b.
Each of SRLs 34 can be constructed in any of a number of well-known forms
for latches. It is preferable, however, to use two-stage latches for SLRs
34 for purposes of data integrity. Examples of latches useful as SRLs 34
are described in U.S. Patent No. 4,667,339, issued on May 19, 1987 and
assigned to Texas Instruments Incorporated, and also in said patent
numbers 4,710,933, 4,710,931, 4,701,921 and 4,698,588.
By way of example, one preferred construction of an SRL 34 is schematically
shown in FIG. 3. SRL 34 shown in FIG. 3 is a static master/slave latch,
having two inputs SCANIN and IN, connected via pass gates 100 and 103 to a
master stage of SRL 34. Pass gate 100 is controlled by a clock signal
MSTR, while pass gate 103 is controlled by a clock signal CLK. Clock
signal MSTR is generated during the scan operation, and clock signal CLK
is generated during the functional operation of the logic circuit. The
master stage of SRL 34 consists of inverters 102 and 104, with the output
of inverter 104 connected to the input of inverter 102 and with the input
of inverter 104 connected to the output of inverter 102. A pass gate 101
connects the output of inverter 102 to the slave stage of SRL 34; pass
gate 101 is controlled by clock signal SHF which, as discussed above, is
the data shift signal utilized in modules 26 of the logic circuit. The
slave stage is similarly constructed by way of inverters 106 and 108, with
the output of one connected to the input of the other. Any of a number of
well known configurations of logic inverters may be used for inverters
102, 104, 106, and 108; the actual construction is likely to depend upon
the technology used in the construction of the functional circuitry 31 in
the logic circuit. It is useful, however, for the transistors comprising
inverters 104 and 108 to have less drive capability than the transistors
comprising inverters 102 and 106, so that if a logic state is driven at
the input of inverters 102 and 106 which is opposite that of the state
stored by the stages of SRL 34, inverters 102 and 106 will change state
responsive to the input (rather than having inverters 104 and 108 control
the state of the latch stage regardless of the input). Such design
considerations can easily be incorporated by one of ordinary skill in the
art.
In operation, clock signals MSTR, CLK and SHF are derived from a system
clock which is externally presented to the logic circuit, or may be
generated by the logic circuit itself having reference to a crystal
oscillator connected externally thereto. Clock signals MSTR and CLK are
signals substantially in phase with one another, except that clock signal
MSTR is generated only during scan operations and that clock signal CLK is
generated only during functional operations. Clock signal SHF is generated
during each system clock cycle in such a manner that it does not overlap
clock signals MSTR or CLK. FIG. 3a illustrates the timing relationship
among clock signals MSTR, CLK and SHF in both scan and functional cycles.
The two-phase non-overlapping clocks controlling SRL 34 prevents both pass
gates 100 (or 103) and 101 from being conductive at the same time. Clock
signals MSTR, CLK and SHF can generated from a system clock signal in a
manner well known in the art; as will be described below, the generation
of clock signal MSTR can be gated by an | | |
