Push-pull readout of dual gate CID arrays

What is claimed is:

1. In an IR sensitive charge injection device (CID), the combination comprising:

(A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, said configuration producing capacitive coupling (CRC) between the row gate and column gate at each pixel site, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line,

(B) a readout circuit comprising:

(a) a source (VRT) of row transfer potentials and m controllable row transfer switches (TS.sub.1-m) for injecting signal charge into the substrate and transferring charge via the column line during readout,

(b) shift register means (SRO,SRE) coupled to said row transfer switches for connecting a respective (jth) row line to said source (VRT) to begin injection, injection (duration ti) terminating with disconnection of said (jth) row line from said source (VRT)

(c) row reset means including a source (VRB) of row bias potentials and m controllable row bias reset switches (RS.sub.1-m), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange between column and row gates at a site, said reset switches being timed to disconnect said (jth) row from said source VRB when injection of said jth row begins, the reconnection of said (jth) row line to said source (VRB) for reset occurring at the same instant that the (j+1)th row line is connected to said source (VRT) to begin injection of said (j+1)th row line,

(d) n column video processors, each kth processor comprising:

(1) a gain amplifier (A1.sub.k) having the input thereof coupled to the (kth) column line at a first node (N1.sub.k),

(2) column reset means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0.sub.k), for applying a column bias potential (VCB) to said first node (N1.sub.k) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site,

(3) means including a series connected capacitor (C1.sub.k) and a shunt connected switch (S1.sub.k) coupled to the output of said gain amplifier for taking a first sample, means including a series connected switch (S3.sub.l) and a shunt connected a capacitor (C3.sub.k) coupled to the output of said first sample taking means for taking a second sample correlated to the first sample, and

(e) timing means including a timing generator for timing the operation of said shift register and said reset switches, the readout of each selected site (jth row, kth column) being effected by switches TS.sub.j, RS.sub.j, S0.sub.k, S1.sub.k and S3.sub.k,

the switches S0.sub.k and S1.sub.k being closed to reset the first node (N1.sub.k) to start readout of the jth row, switch S0.sub.k being opened after resetting, switch S1.sub.k being opened after settling to finish charging capacitor C1.sub.k to obtain a first sample, followed by closure of the jth row transfer switch (TS.sub.j) to inject signal charge into said substrate and to transfer charge to and from the column gates, said switch S3.sub.k being closed prior to the opening of the jth row transfer switch to obtain a second sample correlated with the first sample, closure of switch S0.sub.k at the end of injection resetting the first node (N1.sub.k) to terminate readout of the jth pixel,

the resetting of the j.sup.th row, which produces a negative going pulse due to said capacitive coupling (CRC), simultaneous with injection of said (j+1).sup.th row, which produces a positive going pulse due to said capacitive coupling (CRC), cancelling the extraneous injection pedestal and reducing the voltage excursion at the input of said amplifier (A1.sub.k).

2. The combination set forth in claim 1 wherein

said shift register means are implemented by an odd row shift register controlling odd row lines, via odd row transfer switches, and an even row shift register controlling even row lines via even row transfer switches,

said timing generator at pixel duration intervals simultaneously disconnecting all odd row lines from and connecting all even row lines to said source VRB; simultaneously connecting all odd row lines to and disconnecting all even row lines from said source VRB, and simultaneously connecting all even row lines to and disconnecting all odd row lines from said source VRB, etc. in a continuous sequence providing equal injection periods and equal reset periods between odd and even pixel sites.

3. In an IR sensitive charge injection device (CID), the combination comprising:

(A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m+1 rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, said configuration producing capacitive coupling (CRC) between the row gate and column gate at each pixel site, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line,

(B) a readout circuit comprising:

(a) a source (VRT) of row transfer potentials and (m+1) controllable row transfer switches the (TS.sub.1-m, TS.sub.d), for injecting signal charge into substrate and transferring charge via the column line during readout, of row bias potentials and (m+1) controllable row bias reset switches (RS.sub.1-m RS.sub.d), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange, between column and row gates at a site,

(c) row selection means including a shift register (SR') having m outputs for controlling said row transfer switches (TS.sub.1-m) for selected (jth) member of said set of m row lines to said source (VRT) to begin injection, injection (duration ti) terminating with disconnection of said (jth) row line from said source (VRT), and for controlling said row reset switches (RS.sub.1-m) for disconnecting said (jth) row from said row bias source (VRB) when injection of said selected jth row begins and for connecting said (jth) row to said bias source (VRB) when injection of said selected jth row ends,

said row bias reset switch RSd connecting said (m+1)th row line to said source (VRB) simultaneously with the connection of each selected (jth) row to said source (VRT), and said row transfer switch TSd connecting said (m+1).sup.th row line to said source (VRT) simultaneously with the connection of each selected (jth) row to said source (VRB),

(d) n column video processors, each kth processor comprising:

(1) a gain amplifier (A1.sub.k) having the input thereof coupled to the (kth) column line at a first node (N1.sub.k),

(2) column reset means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0.sub.k), for applying a column bias potential (VCB) to said first node (N1.sub.k) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site,

(3) means including a series connected capacitor (C1.sub.k) and a shunt connected switch S1.sub.k coupled to the output of said gain amplifier, for taking a first sample,

(4) means including a series connected switch (S3.sub.k)and a shunt connected capacitor C3.sub.k) coupled to the output of said first sample taking means for taking a second sample correlated with the first sample, and

(e) timing means including a timing generator for timing the operation of said shift register and said reset switches, the readout of each selected site (jth row, kth column) being effected by switches TS.sub.j and TSd, RS.sub.j and RSd, S0.sub.k, S1.sub.k, and S3.sub.k,

the switches S0.sub.k and S1.sub.k being closed to reset the first node (N1.sub.k) to start readout of the jth being opened after settling to finish charging capacitor C1.sub.k to obtain a just sample, followed by closure of the jth row transfer switch (TS.sub.j) to inject signal charge into said substrate and to transfer charge to and from the column gates, said switch S3.sub.k being closed prior to the opening of the jth row transfer switch to obtain a second sample correlated with the first sample, closure of switch S0.sub.k at the end of injection resetting the first node (N1.sub.k) to terminate readout of the jth pixel,

the resetting of the (m+1)th row, simultaneous with injection of each row, and the injection of the (m+1)th row, simultaneous with reset of each row, cancelling the injection pedestal and reducing the voltage excursion on all N1 modes.

4. The combination set forth in claim 3 wherein:

said means B(c) comprises a (1) shift register having m outputs, (2) m two input AND gates (T.sub.1-m), one input of each being connected to a respective output of said shift register, the output of each AND gate being connected to control a respective row transfer switch (TS.sub.1-m), (3) m+1 inverters (U.sub.1-m, Ud) the jth member of the set (U.sub.1-m) of inverters being connected to a respective output of each (jth) AND gate and the output of each jth inverter being connected to control a respective (jth) row reset switch (RS.sub.1-m), and wherein

(e') said timing generator provides a waveform (phi G) having a high state once each pixel period, the high state having a duration (ti) for timing injection and reset,

said waveform being coupled to the other input of all AND gates (T.sub.1-m) to time injection, and to control the (m+1)th row reset switch (RSd); and to the input of the (m+1)th inverter to control the (m+1)th row transfer switch (TSd).

5. In an IR sensitive charge injection device (CID), the combination comprising:

(A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, said configuration producing capacitive coupling (CRC) between the row gate and column gate at each pixel site, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line,

(B) a readout circuit comprising:

(a) a source (VRT) of controllable row transfer switches (TS.sub.1-m), for injecting signal charge into the substrate and transferring charge via the column line during readout,

(b) row reset means including a source (VRB) of row bias potentials and m controllable row bias reset switches (RS.sub.1-m), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange between column and row gates at a site,

(c) row selection means including a shift register (SR') having m outputs for controlling said row transfer switches (TS.sub.1-m) successively connecting a selected (jth) row line to said source (VRT) to begin injection, injection (duration ti) terminating with disconnection of said (jth) row line from said source (VRT); and for controlling said row reset switches (RS.sub.1-m) for disconnecting said (jth) row from said row bias source (VRB) when injection of said selected jth row begins and for connecting said (jth) row to said bias source (VRB) when injection of said selected jth row ends,

(d) n column video processors, each kth processor comprising:

(1) a gain amplifier (A1.sub.k) having the input thereof coupled to the (kth) column line at a first node (N1.sub.k),

(2) column reset means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0.sub.k), for applying a column bias potential (VCB) to said first node (N1.sub.k) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site,

(3) means including a series connected capacitor (C1.sub.k) and a shunt connected switch S1.sub.k coupled to the output of said gain amplifier, for taking a first sample,

(4) means including a series connected switch (S3.sub.k) and a shunt connected capacitor (C3.sub.k) coupled to the output of said first sample taking means for taking a second sample correlated with the first sample, and

(5) a pedestal cancellation network comprising

(i) a source of pedestal cancellation voltage (VC)

(ii) a capacitor (C0.sub.k) having one terminal coupled to a node N0.sub.k and the other to the node N1.sub.k

(iii) a first pedestal cancellation switch SC1.sub.k connected between said source VC and said node N0.sub.k

(iv) an inverter UC.sub.k having the output connected to control said first switch SC1.sub.k

(v) a second pedestal cancellation switch SC2.sub.k connected between ground and said node N0.sub.k

(e) timing means including a timing generator for timing the operation of said shift register, said reset switches and said pedestal cancellation network, the readout of each selected site (jth row, kth column) being effected by switches TS.sub.j, RS.sub.j, S0.sub.k, S1.sub.k and S3.sub.k, and pedestal cancellation being effected by switches SC1.sub.k and SC2.sub.k

the switches S0.sub.k and S1.sub.k being closed to reset the first node (N1.sub.k) to start readout of the jth row, switch S0.sub.k being opened after resetting, switch S1.sub.k being opened after settling to finish charging capacitor C1.sub.k to obtain a first sample, followed by closure of the jth row

transfer switch (TS.sub.j) to inject signal charge into said substrate and to transfer charge to and from the column gates, said switch S3.sub.k being closed prior to the opening of the jth row transfer switch to obtain a second sample correlated with the first sample, closure of switch S0.sub.k at the end of injection resetting the first node to terminate readout of the jth pixel,

switch SC1.sub.k being opened and switch SC2.sub.k being closed simultaneously with injection of each row, and switch SC1.sub.k being closed and switch SC2.sub.k being opened simultaneously with the resetting of each row to cancel the injection pedestal and reduce the voltage excursion on all N1 nodes.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to charge injection devices (CID) for sensing IR image intensity information obtained from a two dimensional array of dual-gate sensing sites on an InSb or HgCdTe substrate, and more particularly to a novel push-pull readout circuit which eliminates the pedestal due to capacitive coupling between gates on the same pixel of a dual gate CID.

2. Prior Art

Dual-gate charge-injection device focal plane mosaics are solid-state self-scanned sensors that employ surface charge transfer/injection to achieve full X-Y address capability for area arrays. The pixels are conventionally scanned one row at a time, with separate parallel processing of the columns which is later multiplexed into a serial format. The charge transfer takes place between the row and column sites (and vice versa) at a dual-gate site. Injection represents the injection of charge into the substrate from the dual-gate site accompanied by a flow of charge at the input of the column preamplifier of the readout circuit.

The now well-known Sequential Row Inject (SRI) readout is achieved by placing the inject pulse on the rows, one at a time, and sensing the injected charge on the column. As usual, the desired signal voltage is the change in column voltage as a result of the injected charge, and is obtained by sampling the column voltage before and after the injection pulse by correlated double sampling. A bias charge is always maintained in the potential wells of both row and column.

The success of SRI lies in the fact that charge transfer/injection occurs only once in the selected cell (row) of each column in the sequence of scanning all the rows. The other cells are left undisturbed, thus eliminating the possibility of charge contributions from them and providing greater tolerance to charge-transfer inefficiency due to the classical InSb/oxide interface problem.

The conventional approach to implementing the SRI readout mode in a pixel readout cycle is illustrated in FIG. 6C. The pixel readout cycle starts with a reset of brief duration (tr). The first sample of the correlated double sampling (CDS) process is taken after the waveform has settled from the reset disturbance (t1). The injection (ti) is applied right after the completion of the first sample with only a minimal delay which is required to insure that the leading edge of the injection pulse does not overwhelm the first sample. After injection, an additional delay (t2) is required to allow the trailing edge of the injection pulse to settle (the pause time determines the pre-CDS bandwidth) before the second sample is taken, which concludes the pixel readout cycle. The total pixel readout time tp is then the sum of tr, t1, ti, and t2. For a sequential readout, tp=Ti/m, Ti and m being the integration time (or line time) and number of pixels (rows) in the column, respectively.

With the growth in the size of the arrays from 32.times.32 to 128.times.128 to 256.times.256 the quantity m grows from 32 to 128 to 256. On the other hand, the integration time Ti is specified by the system requirement, but is limited to roughly 1.0 millisecond due to array dark current and storage capacity constraint. As a consequence, the available pixel readout time tp is no longer adequate for the normal readout process. Specifically, the injection time ti needs to be at least 1.0 microsecond to minimize the lag caused by incomplete charge injection, whereas low preamp noise requires long settling time (t1 and t2) for narrow pre-CDS bandwidths. Accordingly, the faster the readings, the higher the bandwith requirement of the preamplifier and the greater the sensitivity to input noise.

In the actual implementation of the conventional SRI readout, there are other complications. High performance sensor systems normally use CMOS parallel video processor (PVP) chips on the focal plane. The coupling of the injection pulse from row to column (preamp input) causes a pedestal which is usually large enough to saturate the amplifier chain. Consequently, waveform settling does not start during the "dead time" until the amplifiers recover from saturation.

The problem forces the preamplifier to be designed to handle a greater dynamic range. The other complication associated with the sample-after-inject readout is the CID noise due to tunneling breakdown which reduces the ultimate sensitivity of the array to weak IR radiation.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide improved readout in a two dimensional IR sensing array.

It is another object of the present invention to provide in a two dimensional IR sensing array, readout in which the demands of greater dynamic range and wider bandwidth upon the preamplifier are reduced.

It is still another object of the invention to provide in a two dimensional IR sensing array, readout in which injection breakdown effect is minimized in the interest of reducing dark current noise.

These and other objects of the invention are achieved in an IR sensitive charge injection device (CID) comprising an IR sensing array and a novel readout circuit.

The array comprises a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate connected in successive row lines and a conductive column gate connected in successive column lines. The charges at a site are free to flow at the interface between the column gate and row gate in the presence of a bias potential, the configuration providing between the row gate and column gate at each pixel site a capacitive coupling (CRC) which gives rise to an undesired pedestal in the output waveform.

The readout circuit, in accordance with a first embodiment of the invention, comprises a source (VRT) of row transfer potentials and individual row transfer switches for injecting signal charge into the substrate and transferring charge via the column line during readout the row selection process being controlled by a pair of shift registers, one for odd and the other for even rows.

Row reset is achieved by means including a source (VRB) of row bias potentials and individual row bias reset switches for establishing the charge storing potential wells at the row gates and for facilitating charge exchange between column and row gates at a site.

In accordance with a first embodiment of the invention, two complimentary reset waveforms are provided for odd and even rows respectively, each having alternate highs and lows of one pixel period duration. The reset waveforms are timed in relation to injection, such that as row bias is removed and the injection voltage applied to a given jth row, the (j-1)th row is reset with the effect of cancelling the pedestal.

The readout circuit further comprises n column video processors, each including a gain amplifier coupled to the (kth) column line, and a source (VCB) of column bias potentials and a controllable column bias reset switch (S0.sub.k), for establishing the charge storing potential wells at the column gates and for facilitating charge exchange between column and row gates at a site. Means are also provided to take a correlated double sample including a first switch (S1.sub.k) used in taking a first sample and second switch (S3.sub.k) used in taking the second sample, correlated to the first.

The configuration further comprises a timing generator for timing the operation of the CID. In particular, the switches S0.sub.k and S1.sub.k are closed to reset the kth column line to start readout of each row, switch S0.sub.k being opened after resetting, with switch S1.sub.k being opened to obtain a first sample before injection. Next the row transfer switch (TS.sub.j) is closed to inject signal charge into said substrate and to transfer charge to the column gates. Before injection is finished by opening closed to obtain a second sample correlated with the first sample and complete readout of the jth pixel.

As earlier stated, the resetting of the j.sup.th row, simultaneously with injection of the (j+1) .sup.th row, produces oppositely sensed pulses due to the capacitive coupling (CRC), the cancellation eliminating the extraneous injection pedestal and reducing the voltage excursion at the input of the column video amplifier. The taking of the second sample within the injection period facilitates narrow bandwidth operation of the preamplifier and lower noise for the same readout rate.

In accordance with a second embodiment of the invention, an additional row of pixel sites optically and electrically like the other rows is provided. The readout circuit is modified to provide an additional row transfer switch (TSd) and an additional row bias reset switch (RSd). The row selection means includes a single shift register for controlling the row transfer switches and row reset switches of the 1-m) rows. The row bias reset switch (RSd) connects the additional row line to the bias source simultaneously with the injection of each row selected by the register and the row transfer switch injects the additional row line simultaneously with the reset of each row selected. The result is cancellation of the injection pedestal and a reduction of the voltage excursion on all column lines.

In accordance with a third embodiment of the invention, a pedestal cancellation network is provided as part of each column video processor. It includes pedestal cancellation voltage source (VC), a coupling capacitor connecting the network to the column line, a first pedestal cancellation switch connected between the source (VC) and the coupling capacitor, and a second pedestal cancellation switch connected between ground and the coupling capacitor controlled through an inverter to maintain an opposite state to the first pedestal cancellation switch. The two pedestal cancellation switches operate simultaneously with injection and the resetting of each row to cancel the injection pedestal and reduce the voltage excursion on all column lines.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventive and distinctive features of the invention are set forth in the claims of the present application. The invention itself, however, together with further objects and advantages thereof may best be understood by reference to the following description and accompanying drawings, in which:

FIG. 1 is a circuit diagram of an IR sensing charge injection device (CID) comprising a two dimensional array of dual gate sensing sites on an InSb or HgCdTe substrate and a novel push-pull readout eliminating from the array output waveform the undesirable pedestal due to capacitive coupling between a row site and a column site on individual pixels in accordance with a first embodiment of the invention;

FIG. 2 is a circuit diagram of a column video processor suitable for use in the CID illustrated in FIG. 1;

FIG. 3 is an equivalent circuit of a pixel showing the capacitive coupling between a row site and a column site on an individual pixel;

FIG. 4 is an illustration showing the structures of a pair of adjacent pixels on the same column giving rise to the capacitive coupling which produce undesired pedestals and illustrating schematically the push-pull readout used to cancel the undesired pedestals from the array output waveform;

FIG. 5 is an illustration of the scanning and readout control waveforms used to provide push-pull readout to eliminate undesired pedestals from the array output waveform;

FIGS. 6A, 6B and 6C deal with conventional readout and FIGS. 6D, 6E and, 6F deal with push-pull readout as exhibited by the first embodiment; FIG. 6A showing a conventional readout waveform using correlated double sampling modified by omitting the pedestal occurring between the first and second sample; FIG. 6B is an illustration of the pedestal alone of a conventional array readout waveform; and FIG. 6C is an illustration of the conventional composite readout waveform (with the pedestal present); FIG. 6D shows the positive going pedestal appearing in Applicant's novel arrangement when row j is injected (as in each embodiment) to provide the "push" part of the readout operation; FIG. 6E illustrates the negative going pedestal when the j-1(th) row is reset (as in the first embodiment) to provide the "pull" part of the readout operation, and FIG. 6F illustrates the composite output waveform the jth pixel assuming push-pull operation;

FIG. 7 is an illustration of a second embodiment of the invention in which the undesired pedestal in the array output waveform is eliminated by push-pull operation using a row of dummy pixels on the array;

FIG. 8 is an illustration of the scanning and readout control waveforms used in the second embodiment, and

FIG. 9A is an illustration of a third embodiment of the invention in which the undesired pedestal in the array output waveform is eliminated by push-pull operation using a single network associated with each column video processor, and FIG. 9B is an illustration of two waveforms applicable to the third embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, a charge injection device (CID) for infrared (IR) imaging is shown. The CID comprises an IR area sensor array of dual gate charge storage sites combined with a novel readout. The novel readout has a principal advantage of requiring less dynamic range of the preamplifiers by eliminating the pedestal normally present in the CID output waveforms due to injection pulse coupling, and lower preamplifier noise, and lower CID dark noise as will appear in the following discussion.

The sensor array 9 comprises a substrate of IR sensitive semiconductor material, typically Indium antimonide (InSb) or mercury cadmium telluride (HgCdTe) supporting a layer of insulating material typically silicon dioxide (SiO.sub.2) or zinc sulfide (ZnS). A conductive row gate and a conductive column gate are coupled to form a pixel site, each gate defining a capacitive cell including the underlying portions of the insulating layer and of the semiconductor substrate. In the FIG. 1 illustration, the array consists of m rows and n columns of dual gate sites. Each site thus defines a common region consisting of two contiguous capacitive cells in which optically induced electron-hole pairs may be created by photons, and between and within which the charges are free to move. Customarily, the charges accumulate at the interface between the insulating material and the semiconductor material, and flow freely from the column cell to the row cell and vice versa, normally under the influence of voltages applied to the row and column gates. All the row gates in one line are interconnected by an odd or even conductive row line (10 or 11), and all the column gates in one column are interconnected by a conductive column line 12. Accordingly, m row lines and n column lines are provided for connection of the array to the readout circuit.

The readout circuit shown in FIG. 1 may be partitioned into four means (13, 14, 15 and TG). The odd row selection means 13 is connected to the odd row lines 10 of the sensor array. The even row selection means 15 is connected to the even row lines 11 of the sensor array. The means 14 derives parallel information from each column line (12), and as each row is selected for injection, combines the parallel streams of column data into a single serial stream representing the line output of the full sensor array. The means (TG) times the operation of the CID including the means 13, 14 and 15.

The odd and even row selection means 13 and 15, include connection to a source of row bias potentials (VRB) and m controllable row bias reset switches (RS.sub.1-m); connections to a source of row transfer potentials (VRT) and m controllable row transfer switches (TS.sub.1-m); and two shift registers (SRE,SRO) each having m/.sub.2 outputs at which a control pulse (Q.sub.j, Q.sub.j+1 etc.) appears for sequentially selecting single rows for injection in the readout process.

The sequential odd row selection means 13 operates successive odd rows of the sensor array 9. The odd row scanning shift register (SRO) which is implemented by a PMOS or NMOS dynamic bootstrap circuit controls odd row selection, under the control of the clock (phi 10, phi 20) and the sequence starting pulse (phi S), which are supplied from the timing generator (TG), yet to be described. The waveforms are shown in FIG. 5. Each jth output (Q.sub.j) of the odd row shift register is connected to control an odd row transfer switch (TS.sub.1, TS.sub.3, etc.). The source of row transfer potentials (VRT) is connected to a first terminal of all of the odd row transfer switches (TS.sub.1-(m-1)). The second terminal of each odd row transfer switch (TS.sub.j) is connected to the corresponding jth row of the array 9.

As seen in FIG. 5, the odd row scanner (SRO) produces a high on odd pixel periods, the waveform being confined within the second half of the pixel period. The waveforms on Q.sub.1, Q.sub.3, etc., define successive odd periods of injection as the odd row lines of the array are scanned. Similarly the even row selection means (SRE) produces waveforms on Q.sub.2, Q.sub.4, etc., for operating successive even rows of the sensor array. The even row selection means (SRE) produces a high on even pixels periods confined within the second half of the pixel period, which define successive even periods of injection as the even row lines of the array are scanned.

The reset switches are also grouped into even and odd groups. The source of row bias potential (VRB) is connected to a first terminal of all of the row bias reset switches (RS.sub.1-m). The second terminal of each reset switch (R.sub.j) is connected to the corresponding jth row of the array. The odd reset waveform phi RO, which is supplied by the timing generator, and which goes high once each even pixel period is connected to control the odd reset switches (RS.sub.1-(m-1)). Similarly the even waveform phi RE, which goes high once each odd pixel period is connected to control the even reset switches (RS.sub.2-m).

Reset of the odd and even rows occurs alternately with the duration of reset being high for one pixel duration and low for one pixel duration, the resetting being timed, in accordance with the invention, such that

resetting of the (j-1)th row begins at the same instant that injection of the jth row occurs.

Summarizing the array, the odd row selection means 13 sequentially selects the first elements in all the columns for injection, the even row selection means 15 sequentially selects the second elements in all the columns for injection, alternative with the odd row selection means and concluding with a selection of the mth (i.e. last) elements in all of the columns, after which the row selection cycle repeats. Resetting meanwhile occurs on every other row line, once every two pixel durations.

The means 14 of the readout circuit comprises n column video processors (CVP.sub.1-n), each connected to a column line 12 for deriving parallel information as each row is selected and a parallel to serial multiplexer (MUX) usually arranged to form one serial data stream.

Each column video processor (CVP.sub.k) as shown in FIG. 2 comprises four amplifiers (A1.sub.k -A4.sub.k), three capacitors (C1.sub.k -C3.sub.k), four switches (SO.sub.k -S3.sub.k), and a source of column bias potentials (VCB). Five nodes (N1.sub.k, N2.sub.k, N3.sub.k, N4.sub.k, N5.sub.k) useful in circuit description are present in the video processor: the node (N1.sub.k) representing the input and the node (N5.sub.k) representing the output, and the nodes (N2.sub.k, N3.sub.k, and N4.sub.k) representing internal nodes. Each input node (N1.sub.k) is coupled to a correspondingly numbered column (12) of the sensor array 9. Each output node (N5.sub.k) is coupled to a correspondingly numbered input of the parallel to serial multiplexer (MUX).

The column video processor is connected to obtain a correlated double sample at each site in the array corrected for subtractive error. The input node (N1.sub.k) is connected to the input of gain amplifier (A1.sub.k). The input node is also connected via the column bias reset switch (S0.sub.k) and the source of column bias potential (VCB) to ground. The switch (S0.sub.k) and source (VCB) act to reset the node (N1.sub.k) to bias potential. The output of amplifier (A1.sub.k) is connected via capacitor (C1.sub.k) to the node at the input of a buffer amplifier (A2.sub.k), typically of unitary gain. The node (N2.sub.k) is connected to ground by the switch ) which in cooperation with the capacitor (C1.sub.k) provides for dc referencing of the signal sample. The output of the amplifier (A2.sub.k) is connected via the capacitor (C2.sub.k) to the node (N3.sub.k) at the input of the buffer amplifier (A3.sub.k), also typically of unitary gain. The node (N3.sub.k) is connected to ground via the switch (S2.sub.k) which in cooperation with the capacitor (C2.sub.k) provides for subtractive error correction.

Continuing with a description of the column video processor, th output of the buffer amplifier (A3.sub.k) is connected via the switch (S3.sub.k) to the node (N4.sub.k) at the input of the output buffer amplifier (A4.sub.k), also typically of unitary gain. The capacitor (C3.sub.k) is connected between the node (N4.sub.k) and ground. Switch (S3.sub.k) in combination with the capacitor (C3.sub.k) provides for sampling and holding the signal, dc referenced, and corrected for subtractive error. The output of the buffer amplifier (A4.sub.k) which is a correlated double sample corrected for substractive error is then supplied to the kth parallel input of the parallel-to-serial multiplexer (MUX) where it is combined with the outputs of the other buffer amplifiers of the other column video processors to form a suitable signal for application to the display apparatus.

The readout circuit is completed by the timing generator (TG) which has outputs shown in FIG. 5 for timing the operation of the odd and even row scanning shift registers (phi S and phi 10, phi 20; phi 1E; phi 2E and phi RO; phi RE), the operation of the switches (S0, S1, S2, and S3) of the column video processors and the operation of the MUX (phi M).

The readout circuit (13, 14, 15 and TG) scans the array imager 9 in accordance with a method known as sequential row injection (SRI), which has been further modified as will be discussed below. The known SRI method together with certain limitations of that method are described in a paper entitled "Characteristics and Readout of an InSb CID Two Dimensional Scanning TDI Array" by Samuel Wang et al, appearing in the IEEE Transactions on Electron Devices, Vol. ED 32, #8, August 1985. The readout of the imager in the present FIG. embodiment generally follows the sequence described in FIG. 9 of U.S. Pat. No. 4,316,221 of John Swab, filed Aug. 5, 1980 and entitled "Apparatus for Sequential Row Injection Readout of CID Imagers". The readout in the present FIG. 1 embodiment incorporates subtractive error correction as set forth in U.S. Pat. No. 4,734,583 of Wang et al filed Oct. 16, 1986 and entitled "Readout Circuit for Dual-gate CID Imagers With Charge Sharing Corrected for Subtractive Error". The present embodiments depart from the prior methods in respect to the novel push-pull readout technique.

The scanning sequence of the first embodiment begins with the generation by the timing generator (TG) of a starting pulse (phi S) coupled to the odd and even shift registers (SRO), (SRE). The starting pulse initializes the shift registers which start the count by selecting successive odd and even row sites for readout. The odd shift register 13 is scanned with the odd two phase timing waveforms phi 10 and phi 20, while the even shift registers 15 is scanned with the even two phase timing waveforms phi 1E of phi 2E. The shift registers count the, rows in a consecutive numerical sequence until the final row (m) is selected and read out as will be explained below.

It is essential that all sites on the array under the row and column gates be maintained at a suitable state to integrate photon induced charges as the scanning proceeds until readout occurs. This requirement must be maintained consistently with the transfer of charge that occurs from row to column gates, and with the injection of charge into the substrate which occurs when the site is read out.

Every site on the array under a row gate is held at the row bias potential (VRB) except when the row has been selected for readout. When the row is selected, the row bias is released, injection is applied via row transfer voltage (VRT), VI=VRT-VRB, and then the row bias is reapplied. Maintaining a constant integrating bias voltage on the MIS (metal-insulator-semiconduct