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Geometry processor for graphics display system    
United States Patent4862392   
Link to this pagehttp://www.wikipatents.com/4862392.html
Inventor(s)Steiner; Walter R. (Ormond Beach, FL)
AbstractA geometry process for use in a graphics processing system, especially adapted to couple with a hierarchically structured graphics database memory, a special purpose processor for traversing the database, and a display processor, wherein the geometry processor includes double-buffered input registers, a first private data bus to the special purpose traversing processor, a second private data bus to the graphics database memory, a high-speed arithmetic processing module, a double-buffered output register, and a microprogrammable control system. The geometry processor is configured to process the graphics database in two passes. The first pass is a culling operation that culls out graphics data supplied from the database memory that is outside of a defined viewing volume, with the culled data being sent over of the first private bus to a stack memory in the traversing processor. The second pass retraverses the culled data, along with additional associated data from the database memory, from the traversing processor's stack memory and transforms that data from a three-dimensional mathematical format to a two-dimensional format suitable for display on a video display system.



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Drawing from US Patent 4862392
Geometry processor for graphics display system - US Patent 4862392 Drawing
Geometry processor for graphics display system
Inventor     Steiner; Walter R. (Ormond Beach, FL)
Owner/Assignee     Star Technologies, Inc. (Sterling, VA)
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Publication Date     August 29, 1989
Application Number     06/838,300
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     March 7, 1986
US Classification     345/427 345/502 345/506 345/539 345/559 345/561
Int'l Classification     G09B 009/08
Examiner     Harkcom; Gary V.
Assistant Examiner     Nguyen; Phu K.
Attorney/Law Firm     Spensley Horn Jubas & Lubitz
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Priority Data    
USPTO Field of Search     364/518 364/521 364/522 364/200 MS File 364/900 MS File 340/724 340/734 340/747 340/750 340/799
Patent Tags     geometry processor graphics display
   
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I claim:

1. A programmable electronic geometry processor circuit for use in a graphics display system that includes a database memory for storing segments of graphics data which represent three-dimensional objects to be displayed and which contain operation codes pertaining to the objects, a first processing means for writing segments of graphics data into the memory, a second processing means responsive to the first processing means for sequentially fetching graphics data stored in the memory and placing such fetched graphics data on a dedicated memory bus, and a third processing means for accepting processed graphics data from the geometry processor for display on a display device, where the geometry processor includes:

a. an input register means coupled to the memory by the dedicated memory bus, for temporarily storing graphics data fetched from the memory by the second processing means;

b. a buffer register means coupled to the second processing means by a dedicated stack bus, for buffering data transferred between the second processing means and the geometry processor;

c. an arithmetic pipeline module, coupled to the input and buffer register means, for mathematically processing graphics data temporarily stored in the input register means or the buffer register means;

d. an output register means coupled to the arithmetic pipeline module and to the buffer register means, for temporarily storing the output of the arithmetic pipeline module; and

e. a microcontroller means, coupled to the first and third processing means by a system bus, to the input, buffer, and output register means, and to the arithmetic pipeline module, for accepting from the first processing means a sequence of processing instructions, storing the instructions in an instruction memory, and selectively executing the instructions in response to the operation codes stored in each segment of graphics data, to:

(1) select during a first processing phase from the input register means and temporarily transfer to the second processing means over the stack bus only segments containing data that is at least partly within a defined viewing volume,

(2) accept during a second processing phase the selected segments from the second processing means over the stack bus and associated graphics data from the memory fetched by the second processing means over the dedicated memory bus, and use the arithmetic pipeline module to transform the graphics data from a three-dimensional representation to a two-dimensional representation, and

(3) transfer the transformed graphics data to the third processing means over the system bus for display.

2. The geometry processor of claim 1, wherein the register means are double-buffered.

3. The geometry processor of claim 1, further including intermediate register means, coupled to the input of the arithmetic pipeline module and the output register means, for temporarily storing intermediate calculation values during processing of graphics data and selectively transferring intermediate calculation values to the arithmetic pipeline module for further processing.

4. The geometry processor of claim 2, wherein the arithmetic pipeline module comprises a dynamically reconfigurable calculation pipeline, including:

a. a multiplier circuit, coupled to the inputs of the arithmetic pipeline module, for multiplying two input numbers;

b. an accumulator circuit, coupled to the multiplier circuit, for adding a sequence of products from the multiplier circuit;

c. a multifunction arithmetic logic unit, coupled to the inputs of the arithmetic pipeline module and to the output of the accumulator circuit, for selectively operating on input data or upon the output sum of the accumulator circuit;

d. a linear approximation transform circuit, coupled to the output of the accumulator circuit, for selectively operating on the output sum of the accumulator circuit; and

e. a bus buffer circuit, coupled to the output of the accumulator circuit, for selectively coupling the output sum of the accumulator circuit to the output register means.

5. The geometry processor of claim 1, further including a delay logic circuit coupled to the microcontroller means and the arithmetic pipeline module for selectively delaying the transmittal of portions of instructions to the arithmetic pipeline module to coincide with the processing of data therein.

6. A programmable electronic geometry processor circuit adapted for use in a graphics display system that includes a database memory for storing segments of graphics data which represent three-dimensional objects to be displayed and which contain operation codes pertaining to the objects, a first processing means for writing segments of graphics data into the memory, a second processing means responsive to the first processing means for sequentially fetching graphics data stored in the memory and placing such fetched graphics data on a dedicated memory bus, and a third processing means for accepting processed graphics data from the geometry processor for display on a display device, where the geometry processor includes:

a. a double buffered input register means coupled to the memory by the dedicated memory bus, for temporarily storing graphics data fetched from the memory by the second processing means;

b. a double buffered buffer register means coupled to the second processing means by a dedicated stack bus, for buffering data transferred between the second processing means and the geometry processor;

c. an arithmetic pipeline module, coupled to the input and buffer register means, for mathematically processing graphics data temporarily stored in the input register means or the buffer register means;

d. a double buffered output register means coupled to the arithmetic pipeline module and to the buffer register means, for temporarily storing the output of the arithmetic pipeline module;

e. an intermediate register means, coupled to the arithmetic pipeline module and the output register means, for temporarily storing intermediate calculation values during processing of graphics data;

f. a microcontroller means, coupled to the first and third processing means by a system bus, to the input, buffer, and output register means, and to the arithmetic pipeline module, for accepting from the first processing means a sequence of processing instructions, storing the instructions in an instruction memory, and selectively executing the instructions in response to the operation codes stored in each segment of graphics data, to:

(1) select during a first processing phase from the input register means and temporarily transfer to the second processing means over the stack bus only segments containing data that is at least partly within a defined viewing volume,

(2) accept during a second processing phase the selected segments from the second processing means over the stack bus and associated graphics data from the memory fetched by the second processing means over the dedicated memory bus, and use the arithmetic pipeline module to transform the graphics data from a three-dimensional representation to a two-dimensional representation, and

(3) transfer the transformed graphics data to the third processing means over the system bus for display.

7. The geometry processor of claim 6, wherein the arithmetic pipeline module comprises a dynamically reconfigurable calculation pipeline, including:

a. a multiplier circuit, coupled to the inputs of the arithmetic pipeline module, for multiplying two input numbers;

b. an accumulator circuit, coupled to the multiplier circuit, for adding a sequence of products from the multiplier circuit;

c. a multifunction arithmetic logic unit, coupled to the inputs of the arithmetic pipeline module and to the output of the accumulator circuit, for selectively operating on input data or upon the output sum of the accumulator circuit;

d. a linear approximation transform circuit, coupled to the output of the accumulator circuit, for selectively operating on the output sum of the accumulator circuit; and

e. a bus buffer circuit, coupled to the output of the accumulator circuit, for selectively coupling the output sum of the accumulator circuit to the output register means.

8. The geometry processor of claim 6, further including a delay logic circuit coupled to the microcontroller means and the arithmetic pipeline module for selectively delaying the transmittal of portions of instructions to the arithmetic pipeline module to coincide with the processing of data therein.
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BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electronic processing systems, and more particularly to an electronic system for manipulating data representing geometrical objects and related information in a computer graphics display system.

2. Background Information

The synthesis of visual scenes through the use of computers (computer graphics) is a growing area of computer science. There are innumerable applications of computer graphics, including computer-aided design (CAD), the synthesis of demonstrative charts, creation of titles and other graphics displays for television use, and the simulation of physical events.

In order to facilitate the generation of a scene including one or more objects by computer, normally the first step is to create a three-dimensional description of the objects to be displayed and to store them in mathematical form in a graphics data base. The data is then processed and manipulated so that the scene can be imaged on a display screen.

The processing of information from a graphics data base can be thought of as involving four basic functions:

1. Extracting data corresponding to some part of a graphics object from the graphics data base;

2. Determining which areas of the graphics object are to be visible on the display screen;

3. Transforming the three-dimensional description of the graphics object to a two-dimensional description in display screen coordinates; and

4. Selecting the pixels of the display screen which must be activated to display the object, defining their color and intensity, and activating them to form the desired graphics image.

The present invention is concerned with the second and third processing steps.

One format for storing a graphics data base is referred to as a "hierarchical display list", in which graphics data describing various objects (or pieces of objects) are stored in "segments". Each segment can be thought of as representing a graphics object. Each segment can have one or more segments associated with it in a "parent-child" relationship. The child segment of a parent segment may in turn have one or more child segments associated with it. This parent-child relationship between segments results in a hierarchical inverse "tree" structure.

Each segment of a hierarchical graphics data base typically has structural information which includes "pointers" to parent, child, and "sibling" segments. Sibling segments are those segments having the same parent segment. A pointer to a segment identifies the starting location of that segment in a computer system memory or storage device. In addition to the hierarchical structural data, each segment may also contain a graphics primitive and attributes of the primitive. A graphics primitive is typically a simple planar object, such as a polygon or a vector, defined by a list of coordinates in a convenient three-dimensional coordinate system for that particular graphics primitive. Attribute data for a graphics primitive may define the color or other characteristics of the primitive, and may also include a transformation matrix which specifies the spatial position and orientation of the graphics primitive of that segment with respect to the coordinate system of its parent segment. A feature of one type of hierarchical graphic data base is that attribute information, if not different from the parent segment, need not be defined in the child segment, but can instead be "inherited" from the parent segment.

Computer systems often include peripheral processors to increase the computational speed of the overall system. Peripheral processors are typically specialized computational systems designed to efficiently perform one or more functions. One such peripheral processor is a graphics processor which is designed to accept data from a graphics data base, select portions of that data to be further processed, perform the further processing, and transfer the processed data to another special purpose processor for display on a display screen.

Such graphics processors are used in a variety of applications. For example, interactive CAD systems often utilize graphics processors in conjunction with a host computer to store and display a model of the object or objects to be designed. A designer directs the system through various input devices to create the model, often on a piece-by-piece basis. The various pieces of the model form a graphics data base which is stored by the graphics processor and displayed on command. Changes to the model by the designer cause the system to modify the data base and update the display screen to image the modified model.

An appropriately designed graphics processor, in response to commands from a host computer, can create, copy, or delete segments of a hierarchical data base, which is typically stored in a separate memory of the graphics processor. The graphics processor further can delete, add, or modify various graphics data (such as the attributes, graphics primitives, and transformation matrix within each segment of the graphics data base) in response to host level commands. Once the hierarchical data base has been completed, the graphics processor reads and processes the graphics data base, producing images on a display screen of the objects represented by the graphics data base, as viewed through a user-defined "viewport". In reading the graphics data base, the graphics processor "traverses" the data base by reading data from a first segment of the data base and then moving to a relative segment (either parent, child, or sibling) identified by the first segment's pointers, in accordance with a traversal algorithm. In this manner, the graphics processor traverses the segment "tree" until the data in the graphics data base has been processed.

Because graphics processing is an extremely computation intensive processing task, in order to process the graphics data base in a reasonable amount of time, a peripheral graphics processor may employ a number of special purpose subprocessors to perform separate portions of the overall task. One such subprocessor is a geometry processor.

A sophisticated geometry processor can perform a number of processing function on the graphics data base of the segments. One important function is to test the graphics primitives of each segment to determine whether the primitives are within the field of view defined by the viewport. If not, the segment, and all of its children segments, can be ignored for purposes of further processing, thus increasing overall processing speed.

Additional geometry processor functions can include concatenation of transformation matrices to produce a transformation matrix for each segment which can transform the graphics primitive coordinate set of the segment into the coordinate set of the viewport segment at the "top" of the inverted tree structure. Also, the geometry processor can "clip" partially visible graphics primitives so that those portions of any primitives extending outside the field of view are not processed.

Graphics primitives which are defined in three dimensions must be projected to the two-dimensional image plane of the display. Two principal projection techniques are parallel projection and perspective projection. Parallel projection can be performed by simply ignoring the third coordinate (depth) of the three dimensional coordinate set. Perspective projection can be performed by dividing the components of the first two coordinates (height and width) by the third component (depth) to give the effect of a diminishment in size for those primitives which are "farther" from the viewer.

Once a graphics primitive has been clipped, projected, and/or otherwise transformed, a geometry processor can convert the coordinates of the primitive to the "hardware coordinates" used to display the primitives on a display screen. From the hardware coordinates, the primitives are "rasterized" by a display processor, which converts the hardware coordinates of the primitives into a collection of pixels. Once a primitive has been rasterized, hidden surfaces caused by overlapping primitives are removed.

It can be appreciated from the above that an extensive amount of calculation is often required to process and display the graphics primitive of a segment. Complex models can encompass a data base of thousands of segments. As a result, a graphics processor can require a significant amount of time to convert the data in a graphics data base into an image on a screen. Thus, it is desirable to develop a graphics processor architecture having a very high graphics processing speed. It is further desirable to develop a graphics processor architecture that uses a multitude of subprocessors to divide the complex task of processing a graphics data base into an image in order to achieve higher efficiencies and processing speed. It is therefore desirable to develop a high-speed graphics geometry processor to share the task of processing a graphics data base.

The present invention accomplishes these and other objects by means of a geometry processor having a novel internal processing architecture and system architecture that permits fast and efficient processing of a graphics data base with a simple yet powerful design.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a novel geometry processor that significantly improves the processing rate of graphics data in a graphics processing system. These and other objects and advantages are achieved in a geometry processor having a unique internal and system architecture which facilitates the processing of a graphics data base.

There are three characteristics that are highly desirable in a geometry processor. The first characteristic is a high data transfer rate in and out of the geometry processor. The second characteristic is provision for performing a large number of different mathematical operations, such as multiplication, division, matrix dot products, matrix cross products, square roots, etc. A sequence of these mathematical computations will be referred to as an algorithm. The third characteristic is high degree of programability, so that new algorithms and processes can be accommodated.

The more precision used in a mathematical operation, the wider the range of applications to which the geometry processor can be applied. Some applications require 32-bit floating point numbers, while others may only need 16-bit fixed point number precision. A balance must be achieved between higher precision (which involves a more expensive system), greater flexibility to perform various algorithms, and system processing speed. It is highly desirable to execute a variety of algorithms and transfer data as fast as possible in order to provide the user with a highly interactive graphics system. Generally, however, the higher the speed, the more the system will cost.

Therefore, a system comprising distributed processors for accomplishing the necessary steps to display a graphics data base has numerous advantages.

In the illustrated embodiment, the inventive geometry processor is coupled to (a) a terminal processor for creating and maintaining a graphics data base in response to commands from the host computer, (b) a tree traverser processor that independently traverses the data base, rapidly reading the segments of graphics data at a rate optimized for geometry processing, and (c) a display processor for converting processed data base segments into a visual image.

The tree traverser processor rapidly addresses the graphics processor memory storing the graphics data base, and provides a stream of graphics data segments over a high-speed display list memory bus to the geometry processor. The geometry processor culls out segments that will not be visible on the display screen, and transfers the attribute data of "visible" segments over a second, streamlined stack bus linking the geometry processor with a stack memory resident in the tree traverser processor. Such an arrangement has been found to markedly increase the rate at which graphics data may be read and processed from the graphics data base.

Once the last segment of a traversal path has been reached, the tree traverser reverses direction, retracing visible segments of the path by reading out culled segments from its stack memory. During the reverse traversal, the attribute data of the visible segments is transferred from the tree traverser stack memory over the stack bus back to the geometry processor. In addition, the tree traverser addresses the associated graphics primitives of the visible segments stored in the graphics data base, and transfers the graphics primitives over the display list memory bus to the geometry processor for further processing. Such an arrangement has been found to significantly increase the utilization rate of the geometry processor and the data processing rate of the graphics processor system as a whole. As a result, images on a display screen can be updated at a very fast rate in response to modifications to the graphics data base.

The inventive geometry processor described herein is part of a graphics processing system described in greater detail in a pending application entitled "Improved Graphics Processor", Ser. No. 06/840,459, by Walter Robert Steiner, Anthony John Pelham, and William Scott Didden, and assigned to the assignee of the present application.

The preferred embodiment of the geometry processor is capable of handling data transfer rates of more than 100 megabytes per second, and computational rates of 100 million instructions per second or 30 million 32-bit floating point instructions per second, with microprogram control of the geometry processor hardware to provide a high degree of flexibility in implementing a variety of geometry processing algorithms. The inventive geometry processor incorporates a special 32-bit floating point accumulator design to perform a sum of products very efficiently. This design is more fully described in the pending application entitled "Floating Point Accumulator Circuit", Ser. No. 06/818,284, by Paul A. Simoncic and Walter R. Steiner, and assigned to the assignee of the present application.

The geometry processor also incorporates a novel 32-bit floating point mathematical transformation circuit that performs division and square root operations, as well as curve approximation calculations, at a high data rate. This transformation circuit is more fully described in the pending application entitled "Linear Approximation Transform Circuit", Ser. No. 06/819,346, by Walter R. Steiner and William E. Peregoy, and assigned to the assignee of the present application now abandoned.

The present application also incorporates a multifunction arithmetic logic unit circuit having special decision hardware used to accelerate culling, clipping, and other algorithms programmed into the geometry processor. This circuit is more fully described in the pending application entitled "Multifunction Arithmetic Logic Unit Circuit", Ser. No. 06/824,053, by Walter R. Steiner and Paul A. Simoncic, and assigned to the assignee of the present invention.

The geometry processor in its preferred embodiment is a single board, pipelined, programmable, fixed-point or floating-point arithmetic processor specifically tailored to execute geometric algorithms used for graphics purposes. The invention will become better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings showing the preferred embodiment of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a graphics processor system incorporating the inventive geometry processor.

FIG. 2 is a diagramatic example of the inverse tree hierarchical data base structure used in conjunction with the present invention.

FIG. 3 is a diagramatic example of two graphics objects with different coordinate sets.

FIG. 4 is a schematic diagram of the overall geometry processor circuitry.

FIG. 5 is a schematic diagram of the internal control circuitry for the geometry processor.

FIG. 6 is a schematic diagram of the internal arithmetic pipeline circuitry of the geometry processor.

FIG. 7 is a block diagram of the possible data paths through the arithmetic pipeline circuitry of the geometry processor.

FIGS. 8a and 8b are schematic diagrams of the delay logic circuits of the geometry processor.

Like reference numbers in the various drawings refer to like elements.

DETAILED DESCRIPTION

Overview of Operational Environment

FIG. 1 shows a schematic diagram of a graphics processor system 100 incorporating the inventive geometry processor. The graphics processor system 100 includes a terminal processor 112 which executes host level commands received from a host computer (not shown) through a host interface 114. A majority of the host level commands are directed to building and managing a graphics data base in the form of a hierarchical display list which is stored in a display list memory ("DLM") 116. The terminal processor 112 communicates with the DLM 116 over a general purpose system bus 118 which, in the illustrated embodiment, is a standard 32-bit "VMEbus". The specifications for the VMEbus standard may be found in the VMEbus Specification Manual, Rev. B, August 1982, VMEbus Manufacturers Group.

Host level commands are sent by a host application program resident on the host computer. The user of the host application program can also input data directly into the graphics processor system 100 using a variety of graphics input devices, such as a graphics tablet 120, an alphanumeric keyboard 122, or various other input devices such as joysticks, mice, dial boxes, and track balls (not shown). The input from these devices can be utilized to issue graphics commands to modify the graphics data base, change viewing parameters, and pan or zoom the graphics display provided by a visual display 126. In this manner, applications such as CAD systems may have interactive local control of the display 126.

A geometry processing subsystem 130 couples to the terminal processor 112 by means of the system bus 118. The geometry processing subsystem 130 includes a tree traverser processor 132 for rapidly reading the hierarchical display list stored in the DLM 116. Coupled to the tree traverser 132 by a bidirectional stack bus 138 is the geometry processor 136 of the present invention.

The geometry processor 136 performs all graphics calculations for the geometry processing subsystem 130. The tree traverser 132 traverses the data base stored in the DLM 116 segment b segment, sequentially addressing the data of each segment by means of a DLM bus 134. This traversal converts the tree structure of the DLM 116 into a stream of data which is transmitted over the DLM bus 34 to the tree traverser 132 and to the geometry processor 136. The geometry processor 136 performs the processing functions of culling, clipping, projecting, and transformation matrix concatenation. The overall functions of the geometry processing subsystem 130 are more fully explained in the aforementioned application entitled "Improved Graphics Processor".

As will be explained in greater detail below, the geometry processor 136 does not fully process each graphics primitive before proceeding to the next primitive. Instead, the geometry processor 136 transfers graphics attribute data (such as color attributes) and transformation data directly to the tree traverser 132 over the stack bus 138 if, during the culling process, the geometry processor 136 determines that the associated graphic primitive is potentially visible. The tree traverser 132 stores the attribute and transformation data from the geometry processor on an internal stack memory on a first-in/last-out basis. Through constant communication with the tree traverser 132, the geometry processor 136 ensures that attribute and transformation data for visible segments only is stored in the tree traverser stack memory.

Once the tree traverser 132 reaches the last segment of a traversal, the tree traverser reverses direction, retraversing the potentially "visible" segments (that is, the segments having potentially visible graphics primitives) indicated by the data stored in the tree traverser stack memory. As the tree traverser 132 retraces the traversal path from segment to segment, the tree traverser transfers the graphics data for each segment stored in its stack memory back to the geometry processor 136 over the stack bus 138. At the same time, the tree traverser 132 addresses additional graphics data stored in the DLM 116 which comprises the graphics primitive associated with the current segment being transferred back to the geometry processor 136. The graphics primitive is transferred to the geometry processor 136 over the DLM bus 134. The geometry processor 136 utilizes the data from the tree traverser stack memory and from the DLM 116 to perform what is known as "face" processing, which transforms the graphics data for display. In the illustrated embodiment, the geometry processor 136 clips and projects the graphics primitive of a visible segment and performs a portion of the appropriate shading calculations. Once completed, the geometry processor 136 passes the graphics primitive along with inherited attributes in the format of an "edge packet" across the system bus 118 to a display processor 140. The display processor 140, in conjunction with a Z-buffer 146 and a frame buffer 142, performs rasterization, hidden surface removal, and the remainder of the shading calculations. The function of the display processor 140 is more fully described in the pending application entitled "Display Processor for Graphics Display System", Ser. No. 06/832,518, by William A. Kelly, David E. Orton, and Gregory N. Stock, assigned to the assignee of the present invention.

Thus, the architecture of the graphics processing subsystem 130 balances high-speed processing against system cost by utilizing the geometry processor 136 for both culling and face processing, and the tree traverser 132 for traversing and retraversing.

Hierarchical Data Base Structure

In order to better understand the operation and design of the graphics processor system 100, a simplified example of a tree-type hierarchical display list is illustrated in FIG. 2. The display list of FIG. 2 represents and describes the objects shown in FIG. 3, which include a cup and saucer 150 and a cube 152. These simple objects have been selected for purposes of illustration only. In actual practice, the objects which can be modeled may be significantly more complicated.

The cube 152 can be thought of as a collection of six faces 1-6, where each face is represented by a four-sided polygon having a particular color, shading, and spatial relationship to the cube considered as a whole. In this manner, complex objects can be modeled by breaking the object up into simple shapes (graphics primitives) which have associated attribute information.

The basic element in the display list of FIG. 2 is the segment. Each segment can have a graphics primitive (such as a polygon, vector, etc.), attributes (such as polygon color, a transformation matrix, etc.), and structural information (such as pointers to related segments). Each segment of data is divided into two buffers, a culling buffer and a primitive data buffer. The culling buffer contains attribute data and information needed to determine if the associated primitive is visible within a defined field of view. The primitive data buffer contains the data necessary to define the graphics primitive itself.

The root or top segment A of FIG. 2 is the "viewport" definition segment, which defines the vantage angle from which the graphics objects are viewed and the volume of space visible to the viewer. This segment has an associated reference coordinate set designated a "world" coordinate set and represented by the three orthogonal axes 154 in FIG. 3. The spatial relationship between the cup and saucer 150 and the cube 152 is defined in terms of their world coordinates.

An eye point 156 and a sight point 158 (specified in world coordinates) together with a roll angle .theta. define a second coordinate set, the "eye" coordinate set. The origin of the eye coordinate set is located at the eye point 156 with the Z axis extending along the line of sight in the direction of the sight point 158. The roll angle .theta. defines the angle of rotation of the X and Y axes about the Z axis. The viewing volume is defined by six "clipping planes", which typically form a frustrum. In this manner, the eye coordinate set identifies the vantage angle from which the objects are to be viewed.

A related coordinate set is the eye-scaled coordinate set, in which the X and Y coordinates of the eye coordinate set are scaled to simplify the clipping process. The viewport definition segment A has a transformation matrix to transform coordinates in the world coordinate set to coordinates in the eye coordinate set, and a second viewport matrix to convert the eye coordinates to the eye-scaled coordinate set.

Below the viewport definition segment A of FIG. 2 is a second segment of the display list, designated segment B. Segment B is a child segment of the parent segment A and represents the cup and saucer 150 considered as a whole. Associated with the cup and saucer 150 is a "model" coordinate set 160, which is defined by placing the origin of the model coordinate set at a convenient location and aligning the axes with respect to some of the primitive data. All of the primitive data within one segment is referenced to its associated model coordinate set. Segment B has a transformation matrix which transform points in the segment B model coordinate set to the coordinate set of its parent, segment A (which in this case is the world coordinate set).

Segment B also has pointers to one of its child segments, segment D, and to one of its sibling segments, segment C (which represents the cube 152). Segment C is also a child segment of the parent segment A, and has its own model coordinate set 162, which in this case has an origin placed at one of the vertices of the cube 160 and three axes aligned with edges of the cube. Segment C in turn has six child segments F-K for the six cube faces 1-6, respectively. The segments F-K are quite similar. Segment F, for example, has a pointer to the parent segment C, the sibling segment G, and to a child segment (if any). Segment F has its own model coordinate system in which the four vertices of the polygon defining face 1 are specified. This four-sided polygon is the graphics primitive of segment F. Segment F further defines the color and other attributes of the graphics primitive.

Each segment of the display list is formatted into a number of data buffers which contain the graphics data, and a control block which has pointers pointing to the memory locations in the DLM 116 at which the buffers are located. Each control block comprises a number of words (typically sixteen words) which comprise pointers, flags, and other control data.

One such control block, the segment control block, contains a pointer to the segment's culling buffer which stores the attributes of the associated graphics primitive. Among these attributes is a "bounding box" which is used by the geometry processor 136 in the culling process. The bounding box is a set of eight coordinate points which define a volume that completely contains the graphics primitive for a segment and all of the graphics primitives of all children segments. The bounding box allows the geometry processor 136 to quickly cull out segments that are completely outside the defined field of view by means of simple comparison tests.

Each time the terminal processor 112 enters new graphics data for a segment or alters a transformation matrix, the terminal processor 112 updates the bounding boxes for the entire display list. For example, if a new polygon is entered into one segment, this may increase the size of the bounding box for that segment. If the segment bounding box increases, it may be necessary to increase the size of the bounding box of its parent segment to ensure that the parent segment bounding box includes the new bounding box of the child segment. Thus, changes in one segment may ripple up the display list tree until a segment is reached which is not affected by the change. A flag word in each segment is set when the segment has been modified, indicating that the bounding box for the segment's parent segment may also have to be updated.

Besides the bounding box, the culling buffer also contains attribute data which defines certain characteristics of the segment's graphics primitive. If a particular characteristic is not defined in the culling buffer of a segment, the definition of that characteristic is inherited from the parent segment. For example, if segment C defines its associated graphics primitive (if any) as having the color "red", any of its children (the face segments F-K) which do not locally define the graphics primitive color will inherit the graphics primitive color of "red".

The culling buffer also contains the transformation matrix for transforming the local coordinate set of the segment to the coordinate set of its parent segment. Light source information may also be stored in the culling buffer.

One word of the segment control block defines a pointer to the data buffer which includes the segment's primitive data. The graphics primitive is defined in terms of the local model coordinate set of the segment.

The display list structure used by the graphics processor system 100 allows the "instantiation" of segments. That is, a single segment, once created, may be referenced any number of times by other segments in the display list structure. For example, a single segment defining a cube face might be invoked by each of the segments F-K of FIG. 2 rather than duplicating this information for each child of segment C. Each reference to the instanced segment can alter the attributes of the instanced segment since attributes may be inherited during traversal. Thus, each segment F-K would have a different transformation matrix to position the instantiated face in the correct location to form the cube 160.

In the illustrated embodiment, all quantities in the display list buffers (including control blocks) are stored in fixed length packets of either sixteen words or thirty-two words, wherein each word is thirty-two bits. These fixed length packets ease memory access, memory allocation, and memory deallocation tasks.

For a typical culling buffer or primitive data buffer packet, padding words are used to fill out the packet to sixteen or thirty-two words as necessary. Quantities that ordinarily would be longer than thirty-two words (such as many primitive data types) are broken up into sixteen word packets, and linked together via "next packet" pointers. A "last data buffer packet" pointer of the control block eliminates the need for traversing the entire linked list to find the last buffer packet in order to append segment data.

The above-described segments form a hierarchical display list which is created and stored in the DLM 116 by the terminal processor 112 in a conventional manner. The terminal processor 112 accesses the DLM 116 via the system bus 118. Once the display list has been stored in the DLM 116, the display list may be traversed and processed to produce the desired images of the stored object representations.

Geometry Processor Transformation Algorithms

The geometry processor 136 performs all matrix and vector operations, culling, clipping, projections, and screen scaling in projecting three-dimensional display list data into a two-dimensional screen space.

As noted above, the basic element in the display list memory is the segment, and each segment can optionally have a transformation matrix. This matrix takes data in the segment's coordinates set and transforms it into the parent's set. In FIG. 2, for example, segment D's transformation matrix, when applied to the data in segment D's data buffer, transforms it into segment B's coordinate set. Similarly, segment B's transformation matrix transforms its data into segment A's coordinate set. These transformations are accomplished by rotation, scaling, and translation components in each transformation matrix.

In the preferred embodiment of the present invention, scaling, rotation, and translation terms are stored in a 4.times.3 transformation matrix. The convention used in the matrix representation is as follows:

______________________________________ m00 m01 m02 m10 m11 m12 m20 m21 m22 m30 m31 m32 ______________________________________

Points of a graphics primitive are represented by their X, Y, and Z coordinate values, plus a constant term, in the following representation:

point P=[Px Py Pz 1]

Multiplying a point by a transformation matrix gives as an output the point in the new coordinate set defined by the transformation matrix. For example,

P'=P*M=[Qx Qy Qz],

where:

Qx=Px*m00+Py*m10+Pz*m20+m30

Qy=Px*m01+Py*m11+Pz*m21+m31

Qz=Px*m02+Py*m12+Pz*m22+m32

Rotation about any of the three coordinate axes can be accomplished with the following matrices (where is the angle of rotation):

______________________________________ X axis rotation: 1 0 0 0 cos.theta. -sin.theta. 0 sin.theta. cos.theta. 0 0 0 Y axis rotation: cos.theta. 0 sin.theta. 0 1 0 -sin.theta. 0 cos.theta. 0 0 0 Z axis rotation: cos.theta. -sin.theta. 0 sin.theta. cos.theta. 0 0 0 1 0 0 0 ______________________________________

Scaling about any of the three coordinate axes can be done by incorporating the desired scaling terms (denoted by "S") into the following matrix:

______________________________________ Sx 0 0 0 Sy 0 0 0 Sz 0 0 0 ______________________________________

Translation can be accomplished by setting desired translation terms (denoted by "T") into the following matrix:

______________________________________ 1 0 0 0 1 0 0 0 1 Ty Ty Tz ______________________________________

As noted above, the highest level segment in the tree-structure hierarchy of the present invention is the viewport definition segment. The coordinate set for the viewport definition segment is called the world coordinate set. It is in the world coordinate set that the eye point 156 and sight point 158 values are specified. The specification of an eye point and sight point, as well as a roll angle .theta., define the eye coordinate set.

The eye-scaled coordinate set is introduced to simplify the clipping