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Description  |
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1. Field of the Invention
This invention relates to a display controller for use in terminal
equipment for a computer or video machines and particularly to such a
display controller of the type in which animation pattern images can be
displayed on a display screen.
2. Prior Art
There have recently been proposed a video display controller for a video
game machine or the like by which a combination of an animation pattern
image and a still pattern image can be displayed on a display screen. For
displaying an animation pattern formed by, for example, 8.times.8 dots or
display elements on the screen, data representative of the animation
pattern image and composed of a bit pattern of 8.times.8 bits is read from
a video RAM and fed to a CRT display unit. The display position of this
animation pattern on the display screen is sequentially shifted to achieve
a mobile image. At this time, a still pattern image is also displayed on
the display screen as the background of the displayed image.
U.S. Pat. No. 4,243,984 discloses a video display controller of the kind
described above. With the conventional display controller, however, each
animation pattern can be displayed only in one selected color Thus, it has
not been possible to display a multi-color animation patterns on the
display screen. Also, with the conventional controller, when two animation
patterns overlap, the overlapping portion is displayed in whichever color
of the animation pattern has a higher priority. Thus, the overlapping
condition has not been properly expressed on the screen.
The conventional video display controller is so designed as to detect a
collision of one animation pattern with another on the screen. This
function is very useful for a game machine in which a collision of an
animation pattern, such as a cannonball, with another animation pattern
such as an airplane, has to be detected to play the game. The conventional
video display controller, however, does not detect the position on the
screen at which the collision occurs, and therefore a central processing
unit controlling the video display controller has to obtain the collision
position by executing a program for the detection of the collision
position. Furthermore, with this conventional video display controller,
any collisions which occur on the screen have detected, so that an
additional program must be provided for detecting only the required
collisions.
There has also been proposed another video display control system of which
block diagram is shown in FIG. 1. However, this conventional video display
controller is disadvantageous in that the number of animation pattern
images or sprites which can be displayed on one horizontal scanning line
is relatively small (for example, four). This has much limited a pattern
arrangement on the display screen. The reason for this will now be
described with reference to the drawings.
A central processing unit (CPU) 1 shown in FIG. 1 controls this
conventional video display controller 2 to cause selected pattern images
to be displayed on a screen of a CRT display unit 3. A memory 4 stores
programs which control the CPU 1 and provides for work areas for storing
data to be processed by the CPU 1. As shown in FIG. 2, a video RAM (VRAM)
5 comprises a still pattern table area 5a for storing data representative
of dot patterns of still patterns, a still pattern control table area 5b
for storing data representative of the display position of each still
pattern, a still pattern color table area 5c for storing a color code (4
bits) of each still pattern, an animation pattern table area 5d for
storing data representative of a plurality of animation patterns, and an
animation pattern control table area 5e for storing data representative of
the display position of each animation pattern. The animation pattern
table area 5d stores 256 animation pattern data P0, P1, P2 . . . P255 each
composed of 8 bytes (FIG. 3-(a)). Thus, each of the animation pattern
data P0 to P255 represents an animation pattern which is composed of
8.times.8 bits (one example is shown in FIG. 3-(b)). In this case, bits
"1" of each pattern data represent the foreground of the corresponding
animation pattern, while bits "0" thereof represent the background of the
animation pattern. As shown in FIG. 4-(a), the animation pattern control
table area 5e stores 32 tables C0, C1, C3 . . . C31 each composed of 4
bytes (FIG. 4-(b)). A name of a selected animation pattern Pi (i=0, 1, 2 .
. . 255) is stored in the third byte of each animation pattern control
table Ck (k=0, 1 . . . 31), and the column position (X coordinate) and row
position (Y coordinate) of the display position of the animation pattern
Pi are stored in the second byte and first byte of the table Ck,
respectively. A color code of the animation pattern Pi and EC bit are
stored in the fourth byte of the table Ck. As shown in FIG. 5, the display
position (X, Y) means that the number of display elements counting right
horizontally from the upper left end of the display screen representing
the origin (0, 0) is X while the number of display elements counting
vertically downwardly from the upper left end of the screen is Y. This
display position (X, Y) represents the upper left end of the animation
pattern Pi displayed on the screen.
The display controller 2 will now be described.
A timing signal generator 6 produces master clock pulses in accordance with
an output of a crystal oscillator provided therein, and based on these
clock pules, horizontal and vertical synchronization signals SYNC are
produced and fed to the CRT display unit 3. Also, the timing signal
generator 6 feeds dot clock pulses DCP to a clock input terminal of a
horizontal counter 7. The horizontal counter 7 serves to determine the
display position of each display element on the screen in the horizontal
direction, and the display position is shifted by one dot in the
right-hand direction each time the contents NH of the horizontal counter 7
are incremented by one. When the count NH is 0, the display element at the
left end of each scanning line on the screen is displayed, and when the
count NH is 255, the display element at the right end of each scanning
line on the screen is displayed. A horizontal non-display period is
established when the count NH is in the range of between 256 and 340. Each
time the count NH reaches 340, the horizontal counter 7 feeds a pulse
signal HP to a clock input terminal of a vertical counter 8. The vertical
counter 8 serves to determine the display position of each display element
on the screen in the vertical direction, that is to say, to determine the
number of the horizontal scanning line. The horizontal scanning line is
shifted downwardly by one each time the count NV of the vertical counter 8
is incremented by one. When the count NV is 0, the display elements on the
uppermost horizontal scanning line are displayed. When the count NV is
191, the display elements on the lowermost horizontal scanning line are
displayed. A vertical non-display period is established when the count NV
is in the range of between 192 and 261.
An image data processing circuit 9 is connected to the CPU 1 via an
interface circuit 10 and also to the VRAM 5. The image data processing
circuit 9 serves to write data, fed from the CPU 1, into the respective
table areas of the VRAM 5 and also to read the data written into the VRAM
5 therefrom under the control of the CPU 1 to effect various display
controls. More specifically, in the case of the still pattern display, the
image data processing circuit 9 reads from the still pattern control table
area 5b each of the data representative of the names and display positions
of the still patterns and color codes thereof, which are written thereto
during the above-mentioned vertical non-display period, immediately before
the display of the corresponding still pattern on the display screen, that
is to say, that time period corresponding to 8 display elements before the
display of this still pattern, and in accordance with the read data, the
image data processing circuit 9 reads from the still pattern table area 5a
the dot data representative of the still pattern to be displayed at this
time and loads the corresponding dot data and color code into a shift
register and a color information register, respectively. And, during the
display period, the bits contained in the shift register are shifted out
one by one, and the color code in the color information register, which
represents a color of the foreground of the still pattern, is fed to a
color palette circuit 11 in accordance with the output of the shift
register. The color palette circuit 11 converts each of the color codes
into color data RD, GD and BD representing red, green and blue,
respectively, and a digital-analog converter 12 converts the color data
RD, GD and BD into analog color signals R, G and B, respectively, and
feeds them to the CRT display unit 3 to thereby display the display
elements of the still pattern on the screen in the selected color.
The display of each animation pattern is effected by the image data
processing circuit 9 and four animation pattern processing circuits 13.
More specifically, under the control of the CPU 1, during the vertical
non-display period, the image data processing circuit 9 sequentially
writes into the animation pattern control table Ck the name data, display
position data, color code and EC bit data of each animation pattern Pi to
be displayed in the next frame. The image data processing circuit 9
sequentially reads and checks the Y coordinates of the animation patterns
in the control tables C0 to C31 during each horizontal scanning period to
determine whether any animation patterns should be displayed during the
next horizontal scanning period, and loads into a register address data
representative of those addresses of the animation pattern control tables
Ck containing data representative of animation patterns Pi to be displayed
next. During each horizontal non-display period, the data representative
of the X coordinates in those animation pattern control tables Ck
designated by the above address data are loaded respectively to X counters
of animation pattern processing circuits 13. Also, the dot data each
representative of a row of display elements of a respective one of the
animation patterns to be displayed on the next horizontal scanning line
are read from the corresponding addresses of the animation pattern table
area 5d which are determined by the count NV of the vertical counter 8 and
the Y coordinates in the animation control tables Ck, and are loaded into
corresponding pattern shift registers of the animation pattern processing
circuits 13. Thus, the dot data representative of the display elements of
the animation patterns to be displayed on the next horizontal scanning
line and the data representative of the display start positions X of the
display elements are sequentially stored in the pattern shift registers
and X counters of the animation pattern processing circuits 13. At the
same time, the color code of the foreground of each animation pattern is
transferred from the fourth byte of the animation control table Ck to each
animation pattern processing circuit 13. Then, the next horizontal
scanning is started, and each time the count NH of the horizontal counter
7 is incremented by one, the count of each X counter is decremented by
one. When the count of each X counter reaches "0", the bits contained in
the corresponding pattern shift register are sequentially shifted out one
by one in synchronization with the count-up of the horizontal counter 7 so
that the dot pattern corresponding to these bits are displayed on the CRT
screen in the selected color. In this case, when "1" signal is outputted
from the pattern shift register, the animation pattern processing circuit
13 feeds the color code to the color palette circuit 11, so that a display
element represented by the "1" signal is displayed on the screen in a
color corresponding to this color code. When the output of the pattern
shift register is "0", the animation pattern processing circuit 13 does
not output the color code but outputs a signal S2 which allows the image
data processing circuit 9 to display a display element of the still image.
Thus, the display elements of the still image are displayed in the
positions corresponding to the background of the animation pattern.
With the above-mentioned conventional display controller, when part of the
animation pattern image is hidden on the left side of the screen, the
value of X of the display position (X, Y) becomes negative. As a result,
even when the count of the X counter is decremented one by one, the count
will never reach 0, so that the proper display position of the animation
pattern image can not be determined. Therefore, to compensate for this,
the screen is shifted left by a predetermined number "m" of display
elements (for example, m=32) to provide an imaginary screen as shown by a
broken line in FIG. 5, and the counting of the X counter is started from
the left end of this imaginary screen so as to shift the position (X, Y)
on the imaginary screen to the position (X-m, Y) on an actual screen, so
that the animation pattern image displayed on the screen is shifted left
by "m" display elements. This is effected by the bit data EC in the
animation pattern control table Ck. More specifically, when the bit data
EC is "1", the count-down of the X counter is started earlier by count "m"
to effect the above operation. With this method, the above-mentioned
disadvantages can be eliminated, but since the count-down of the X counter
must be started earlier by count "m", the data required must be loaded
into the X counter and pattern shift register of each animation pattern
processing circuit 13 before the count-down of the X counter is started.
And, the time available for the loading of the data into the animation
pattern processing circuit 13 during the horizontal non-display period is
much shortened accordingly. For example, when magnifying an animation
pattern of 16.times.16 display elements twice, the pattern image must be
shifted by 32 display elements, in which case more than one thirds of the
horizontal non-display period is used by this shifting, this horizontal
non-display period corresponding to 85 count between count 256 and count
340 of the horizontal counter 7. As a result, the data which can be loaded
into each animation pattern processing circuit 13 is reduced, so that the
number of the animation patterns which can be displayed on one horizontal
scanning line is reduced.
There have also been proposed display controllers of the types shown in
U.S. Pat. Nos. 4,262,302, 4,286,320 and 4,374,395, however none of them
have overcome the above-described deficiencies of the conventional
controllers.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a video
display controller by which multi-color animation patterns can be
displayed on a screen.
It is another object of the present invention to provide a video display
controller by which an overlapping portion of animation patterns can be
displayed in a color which is obtained by effecting a certain operation on
color codes of the animation patterns.
It is a further object of the present invention to provide a video display
controller by which the position on the screen at which a collision of one
animation pattern with another can be detected.
It is a further object of the present invention to provide a video display
controller in which a collision of one animation pattern with another can
selectively be detected.
It is a further object of the present invention to provide a display
controller of the type by which an increased number of animation patterns
can be displayed on one horizontal scanning line of the screen.
According to a first aspect of the present invention, there is provided a
video display control system for displaying a video image on a screen of a
video display unit comprising (a) memory means for storing (i) animation
pattern data which represents an animation pattern composed of a
predetermined number of pattern elements each corresponding to at least
one of display elements on the screen, the pattern elements being divided
into at least two pattern element groups, (ii) display position data
specifying a display position which is a position on the screen, and (iii)
at least two color data specifying colors corresponding respectively to
the pattern element groups; and (b) display control means which comprises
(I) reading means for reading the animation pattern data, the display
position data and the color data from the memory means, and (II)
displaying means for displaying an animation pattern image corresponding
to the animation pattern at the display position on the screen in the
colors in accordance with the animation pattern data, the display position
data and the color data read from the memory means, the animation pattern
image being divided into at least two image parts corresponding
respectively to the pattern element groups and each of the image parts
being displayed in corresponding one of the colors.
According to a second aspect of the present invention, there is provide a
video display control system for displaying a video image on a screen of a
video display unit comprising (a) memory means for storing (i) first to
Nth (N.gtoreq.2) animation pattern data each representing an animation
pattern composed of a predetermined number of pattern elements, each of
the pattern elements corresponding to at least one of display elements on
the screen, (ii) first to Nth display position data which specify first to
Nth display positions, respectively, each of which is a position on the
screen, and (iii) first to Nth color data specifying first to Nth colors,
respectively; and (b) display control means which comprises (I) reading
means for reading the first to Nth animation pattern data, the first to
Nth display position data and the first to Nth color data from the memory
means, (II) processing means for receiving the first to Nth animation
pattern data, the first to Nth display position data and the first to Nth
color data read from the memory means and for outputting the first to Nth
color data in accordance with the first to Nth animation pattern data,
respectively, and (III) operation means for receiving the first to Nth
color data outputted from the processing means and for effecting, when the
processing means outputs at least two color data among the first to Nth
color data with respect to same display element on the screen, a certain
operation on the at least two color data to supply the operation result as
a new color data to the video display unit.
According to a third aspect of the present invention, there is provided a
video display control system for displaying a video image on a screen of a
video display unit comprising (a) memory means for storing (i) first to
Nth (N.gtoreq.2) pattern composed of a predetermined number of pattern
elements, each of the pattern elements corresponding to at least one of
the display elements on the screen, (ii) first to Nth display position
data representing first to Nth display positions each of which is a
position on the screen; and (b) display control means which comprises (I)
reading means for reading the first to Nth animation pattern data and the
first to Nth display position data from the memory means (II) processing
means for receiving the first to Nth animation pattern data and the first
to Nth display position data and for serially outputting each of first to
Nth pattern element data by which the first to Nth animation pattern data
are constructed, respectively, each of Kth (1.ltoreq.K.ltoreq.N) pattern
element data corresponding to one of pattern elements of the animation
pattern corresponding to the Kth animation pattern data, and (III)
detection means for receiving the first to Nth pattern element data
serially outputted form the processing means and for detecting the fact
that at least two pattern element data are outputted with respect to the
same display element on the screen from the processing means to output a
detection signal.
According to a fourth aspect of the present invention, there is provided a
video display control system for use with a video display unit having a
screen which provides, in accordance with a clock signal synchronized with
vertical and horizontal synchronization signal, a plurality of columns of
and a plurality of rows of display elements on the screen each for
displaying in a designated color, the video display control system
comprising (a) memory means for storing (i) animation pattern data
representing an animation pattern composed of at least one row of a
predetermined number of pattern elements, each of the pattern element
corresponding to at least one of the display elements, (ii) display
position data specifying a display position which is a position on the
screen; and (b) display control means which comprises (I) horizontal
counter means responsive to the clock signal for generating a horizontal
count representative of a current horizontal display position of display
element on the screen, (II) reading means for reading the animation
pattern data and the position data from the memory means, (III) shift
register means composed of a predetermined number of stages for storing
pattern element data representative of pattern elements which correspond
to a row of the animation pattern, each sta | | |
