A fault tolerant three port communications module has two control ports for receiving commands from two computers, and a communications port for transferring data over a communications channel in response to the commands. Each control port includes a select line which carries a select signal with true and false states, mode lines which carry codes that represent the commands, and a write line which carries a respective pulse in sync with each of the codes. The select line, mode lines, and write line of each control port are coupled in the module to a respective inter-processor command decoder having a lead stage and a trail stage. The lead stage detects when a predetermined code occurs on the mode lines and the select signal is false during a first one of the pulses; and, the trail stage generates an output signal that indicates the receipt of an inter-processor command for the module if, during a second pulse that immediately follows the first pulse, the compliment of the predetermined code occurs on the mode lines and the select line is true.

A method is provided for checking the integrity of a full duplex multi-word serial transfer between first and second devices, the transfer including an actual last word. The method includes transmitting a count word from the first device to the second device, the count word indicating a number of words to be transmitted including an expected last word, transmitting the actual last word from the first device to the second device, and transmitting, substantially simultaneously to transmission of the actual last word, a check code word from the second device to the first device, the check code word having a selected value if the actual last word is the expected last word, and another value otherwise. The method also includes determining a transfer error if the value of the check code word is other than the selected value. A system is also provided for performing the method.

A method and system for pipelining the processing of channel command words is provided. The channel is permitted to send commands and data to the control unit for several channel command words associated with a channel program without having to wait for responses from the control unit for prior commands sent. The channel can pipeline several commands to the control unit and the control unit can then process the commands in the order it receives them. The control unit sends responses to the channel for each command it receives acknowledging receipt of the commands.

An input/output channel apparatus includes a channel processing section and plural channel units transfers data between a main memory and peripheral devices in an electronic computer system. The data transfer speed is directly controlled by the data transfer speed changing mechanism in each channel unit in accordance with the operating condition of the data buffer. Further, the priority of the data chaining process is changed in accordance with the amount of data stored in the data buffer.

A network extender for a computer network including multiple computers interconnected with a shared, common memory. A computer system interface interconnects the multiple computers and controls data flow between the multiple computers and a memory controller connected to the memory. First and second identical interfaces are respectively connected in data communication with the computer system interface and the memory controller. Each interface includes a circuit for converting parallel data to serial data format and a circuit for converting serial data to parallel data format. The parallel to serial converting circuit and the serial to parallel converting circuit of the first interface are respectively connected to the corresponding serial to parallel and the parallel to serial converting circuits of the second interface by serial data communication conductors.