The fabrication of a printed circuit board (26) usually includes the step of testing the board with a testing machine (24) to verify operability. The testing machine accomplishes such testing by transmitting test signals to the board via a transmission line (36) and then analyzing each response signals returned from the board in response to the test signals. To reduce the incidence of error, the testing machine (24) is compensated for the propagation delay of the line (12) which is measured by launching a first string of pulses into one end of the line whose opposite end is left open. A second string of pulses is sinultaneously launched into a programmable delay line (16) which delays each second pulse by an adjustable interval. After the generation of each first and second pulse, a check is made whether the first pulse has been reflected back to the first end of the transmission line at the same time the second pulse reaches the output of the delay line. If the pulses are not coincident, the delay setting of the delay line is increased and then a check is again made whether one of the first and second pulses are coincident. The delay of the delay line is successively increased until the pulse are coincident whereupon the delay of the delay line now equals twice the delay of the transmission line.
Dummy cell test circuit for measuring delay times in embedded, said embedded circuits being connected to access circuits equipped with input access pads and output access pads, between which is comprised an electrical main path, said test circuit comprising a test input pad and a test output pad, between which is comprised an electrical dummy test path. According to the present invention the test input pad correspond to the access input pad (IN1' IN1") of the embedded circuit (2).
A circuit for verifying the accuracy a tester, for enhancing its calibration and for providing tracking between testers. The circuit includes a delay element, first and second multiplexers connected to the input and output of the delay element, respectively, and a feedback path linking outputs of the second multiplexer to inputs of the first multiplexer to provide an oscillation. The delay between an input of the first multiplexer to an output of the second multiplexer is measured and this delay is compared to the frequency domain measurement of the same to provide an indication of the accuracy of the tester.
In particular in automatic testing equipment for integrated circuits, all signal sections at the test piece joint should ideally be of the same electrical length. The signal sections used in the test consist, in the case of reception, of cable, comparator, error logic, etc. If the signal sections are of different electrical durations, then in the case of reception, the transmitted signal must be connected. In a process for determining the electrical duration of signal sections, each of which has a transmitter and a receiver and at the end connecting points for example for an integrated circuit, the connecting points (AS) of all signal sections (SS) are short-circuited, all receivers up to the receiver of the signal section to be measured are then switched off, all transmitters up to the transmitter of the signal section to be measured are switched on and simultaneously emit a pulse which is transmitted to the connecting point. At the short-circuited connecting points (AS) of the signal sections (SS), a central pulse (21) is then produced which is transmitted over the signal section to be measured to its receiver (E). The time at which the pulse produced by the central pulse enters the receiver (E) is recorded and entered in a table. The above-mentioned process is carried out for all signal sections. The measurements so obtained give the relative durations of the various signal sections. The process for determining the duration of signal sections requires only that the connecting points of the signal sections be connected with one another through a short-circuit bridge (KB).
A circuit and method for determining the operating performance of an integrated circuit which may be used to screen integrated circuits prior to sale or delivery, or to optimize the frequency of the integrated circuit during use. The circuit employs a comparison circuit to compare a first time of arrival of a clock pulse, which is propagating through the integrated circuit with a second time of arrival of the clock signal at a second input. The comparison circuit produces an output signal which may be used to reject or accept the integrated circuit, or to automatically adjust the frequency to minimize the delay.
An apparatus for testing a telephone line (12) includes a charge generator (4) for selectively charging a line capacitor (16) formed by the physical relation of at least two electrically conductive leads (8, 10) of the telephone line (12) to a predetermined DC voltage. A line clamp (6) selectively connects the leads (8, 10) together and a return detector (18) receives a discharge pulse (22) produced by discharge of the line capacitor (16) in response to the line clamp (6) connecting the leads (8, 10) together. The return detector (18) detects an end-of-line pulse (28) and/or a bridged-tap pulse (32) superimposed on the discharge pulse (22) and outputs an analog return signal as a function thereof.
