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BACKGROUND OF THE INVENTION
The present invention relates to a reactor and methods for performing
single and in-situ multiple integrated circuit processing steps, including
thermal CVD, plasma-enhanced chemical vapor deposition (PECVD), reactor
self-cleaning, film etchback, and modification of profile or other film
property by sputtering. The present invention also relates to a process
for forming conformal, planar dielectric layers on integrated circuit
wafers and to an in-situ multi-step process for forming conformal, planar
dielectric layers that are suitable for use as interlevel dielectrics for
multi-layer metallization interconnects.
I. Reactor
The early gas chemistry deposition reactors that were applied to
semiconductor integrated circuit fabrication used relatively high
temperature, thermally-activated chemistry to deposit from a gas onto a
heated substrate. Such chemical vapor deposition of a solid onto a surface
involves a heterogeneous surface reaction of gaseous species that adsorb
onto the surface. The rate of film growth and the film quality depend on
the wafer surface temperature and on the gaseous species available.
More recently, low temperature plasma-enhanced deposition and etching
techniques have been developed for forming diverse materials, including
metals such as aluminum and tungsten, dielectric films such as silicon
nitride and silicon dioxide, and semiconductor films such as silicon.
The plasma used in the available plasma-enhanced chemical vapor deposition
processes is a low pressure reactant gas discharge which is developed in
an RF field The plasma is, by definition, an electrically neutral ionized
gas in which there are equal number densities of electrons and ions. At
the relatively low pressures used in PECVD, the discharge is in the "glow"
region and the electron energies can be quite high relative to heavy
particle energies The very high electron temperatures increase the density
of disassociated species within the plasma which are available for
deposition on nearby surfaces (such as substrates). The enhanced supply of
reactive free radicals in the PECVD processes makes possible the
deposition of dense, good quality films at lower temperatures and at
faster deposition rates (300-400 Angstroms per minute) than are typically
possible using purely thermally-activated CVD processes (100-200 Angstroms
per minute) However, the deposition rates available using conventional
plasma-enhanced processes are still relatively low.
Presently, batch-type reactors are used in most commercial PECVD
applications. The batch reactors process a relatively large number of
wafers at once and, thus, provide relatively high throughput despite the
low deposition rates. However, single-wafer reactors have certain
advantages, such as the lack of within-batch uniformity problems, which
make such reactors attractive, particularly for large, expensive wafers
such as 5-8 inch diameter wafers. In addition, and quite obviously,
increasing the deposition rate and throughput of such single wafer
reactors would further increase their range of useful applications.
II. Thermal CVD of SiO.sub.2 ; Planarization Process
Recently, integrated circuit (IC) technology has advanced from large scale
integration (LSI) to very large scale integration (VLSI) and is projected
to grow to ultra-large integration (ULSI) over the next several years.
This advancement in monolithic circuit integration has been made possible
by improvements in the manufacturing equipment as well as in the materials
and methods used in processing semiconductor wafers into IC chips However,
the incorporation into IC chips of, first, increasingly complex devices
and circuits and, second, greater device densities and smaller minimum
feature sizes and smaller separations, imposes increasingly stringent
requirements on the basic integrated circuit fabrication steps of masking,
film formation, doping and etching.
As an example of the increasing complexity, it is projected hat, shortly,
typical MOS (metal oxide semiconductor) memory circuits will contain two
levels of metal interconnect layers, while MOS logic circuits may well use
two to three metal interconnect layers and bipolar digital circuits may
require three to four such layers. The increasing complexity,
thickness/depth and small size of such multiple interconnect levels make
it increasingly difficult to fabricate the required conformal, planar
interlevel dielectric layers materials such as silicon dioxide that
support and electrically isolate such metal interconnect layers
The difficulty in forming planarized conformal coatings on small stepped
surface topographies is illustrated in FIG. 16. There, a first film such
as a conductor layer 171 has been formed over the existing stepped
topography of a partially completed integrated circuit (not shown) and is
undergoing the deposition of an interlayer dielectric layer 172 such as
silicon dioxide. This is done preparatory to the formation of a second
level conductor layer (not shown). Typically, where the mean-free path of
the depositing active species is long compared to the step dimensions and
where there is no rapid surface migration, the deposition rates at the
bottom 173, the sides 174 and the top 175 of the stepped topography are
proportional to the associated arrival angles. The bottom and side arrival
angles are a function of and are limited by the depth and small width of
the trench. Thus, for very narrow and/or deep geometries the thickness of
the bottom layer 173 tends to be deposited to a lesser thickness than is
the side layer 174 which, in turn, is less than the thickness of top layer
175.
Increasing the pressure used in the deposition process typically will
increase the collision rate of the active species and decrease the
mean-free path. This would increase the arrival angles and, thus, increase
the deposition rate at the sidewalls 714 and bottom 173 of the trench or
step. However, and referring to FIG. 17A, this also increases the arrival
angle and associated deposition rate at stepped corners 176. For steps
separated by a wide trench, the resulting inwardly sloping film
configuration forms cusps 177-177 at the sidewall-bottom interface. It is
difficult to form conformal metal and/or dielectric layers over such
topographies. As a consequence, it is necessary to separately planarize
the topography.
In addition, and referring to FIG. 17B, where the steps are separated by a
narrow trench, for example, in dense 256 kilobit VLSI structures, the
increased deposition rate at the corner 176 encloses a void 178. Such
voids are exposed by subsequent planarization procedures and may allow the
second level conductor to penetrate and run along the void and short the
conductors and devices along the void.
SUMMARY OF THE INVENTION
Objects
In view of the above discussion, it is one object to provide a
semiconductor processing reactor which provides uniform deposition over a
wide range of pressures, including very high pressures.
It is another related object to provide a versatile single wafer
semiconductor processing reactor which can be used for a multiplicity of
processes including thermal chemical vapor deposition, plasma-enhanced
chemical vapor deposition, plasma-assisted etchback, plasma self-cleaning
and sputter topography modification, either alone or in-situ in a multiple
process sequence.
It is a related object to provide such a reactor which accomplishes the
above objectives and also is adapted for using unstable gases such as TEOS
and ozone.
It is another object of the present invention to provide a process for
forming highly conformal silicon dioxide layers, even over small dimension
stepped topographies in VLSI and ULSI devices, using ozone and TEOS gas
chemistry and thermal CVD.
It is also an object of the present invention to provide a planarization
process which provides excellent conformal coverage and eliminates cusps
and voids.
It is still another object of the present invention to provide a
planarization process which can be performed in-situ using a multiple
number of steps, in the same plasma reactor chamber, by simply changing
the associated reactant gas chemistry and operation conditions.
It is yet another object of the present invention to provide an in-situ
multiple step process including plasma deposition and isotropic etching of
a wafer for the purpose of optimizing coating conformality and
planarization, along with process throughput and wafer characteristics
such as low particulates.
Another object is to provide the above-described versatile process
characteristics along with the ability to vary the process sequence and
the number of steps, including but not limited to the addition of reactor
self-cleaning.
SUMMARY
In one specific aspect, our invention relates to a semiconductor processing
reactor defining a chamber for mounting a wafer therein and an inlet gas
manifold for supplying reactant gases to the wafer. The chamber also
incorporates a uniform radial pumping system which includes vacuum exhaust
pump means; a gas distributor plate mounted peripherally about the wafer
mounting position within the chamber and including a circular array of
exhaust holes therein; and a circular channel beneath and communicating
with the hole array and having at least a single point connection to the
vacuum exhaust pump for flowing gases radially from the inlet manifold
across the wafer and through the exhaust port. The channel is of
sufficiently large volume and conductance relative to the holes to enable
controlled uniform radial gas flow across the wafer to the exhaust holes,
thereby promoting uniform flow and processing (etching and deposition)
over a wide range of pressures, including very high pressures up to about
one atmosphere.
In another aspect, the present invention is directed to a semiconductor
processing reactor which comprises a housing forming a chamber for
mounting a wafer horizontally, a vacuum exhaust pumping system
communicating with the chamber, and an inlet gas manifold oriented
horizontally over the wafer mounting position The manifold has a central
array of process gas apertures configured for dispensing reactant gas
uniformly over the wafer and a second peripheral array of purging gas
apertures configured for directing purging gas downward to the periphery
of the wafer. The hole arrays are also arranged to eliminate radial
alignment of holes.
In another aspect, the reactor incorporates a system for circulating fluid
of controlled temperature within the manifold for maintaining the internal
surfaces within a selected temperature range to prevent condensation and
reactions within the manifold and for maintaining the external manifold
surfaces above a selected temperature range for eliminating unwanted
deposition thereon.
In still another aspect, the reactor of the present invention comprises a
thin susceptor for supporting a wafer, susceptor support means for
mounting the susceptor in a horizontal position precisely parallel to the
gas inlet manifold and means for selectively moving the wafer support
means vertically to position the susceptor and support parallel to the gas
manifold at selected variable-distance positions closely adjacent the gas
manifold In particular, the variable parallel close spacing can be 0.5
centimeter and smaller.
In still another aspect, the semiconductor processing reactor of the
present invention comprises a housing defining a chamber therein adapted
for the gas chemistry processing of a wafer positioned within the chamber.
A transparent window forms the bottom of the chamber. A thin high
emissivity susceptor is used for supporting a wafer within the chamber. A
radiant heating module comprising a circular array of lamps mounted in a
reflector module is mounted outside the housing for directing a
substantially collimated beam of near-infrared radiant energy through the
window onto the susceptor with an incident power density substantially
higher at the edge of the susceptor than at the center thereof, to heat
the wafer uniformly.
Preferably, a second, purge gas manifold is positioned beneath the wafer
processing area for providing purging gas flow across the window and
upward and across the bottom of the wafer. The combination of the high
pressure, the purge flow from the inlet gas manifold and that from the
purge gas manifold substantially eliminates deposition on chamber
surfaces.
In still another aspect, the reactor of the present invention comprises a
deposition gas feed-through device connected to the gas inlet manifold
which comprises tube means adapted for providing co-axial flow of
deposition gas on the inside of the tube and purge gas on the outside
thereof into the gas inlet manifold. The tube is adapted for connection to
ground at the inlet end and to an RF power supply at the outlet or
manifold end to provide RF power to the manifold, and has a controlled
electrical impedance along its length from the inlet to the outlet end for
establishing a constant voltage gradient to prevent breakdown of the gas
even at high RF frequencies and voltages.
These and other features discussed below permit reactor operation over a
wide pressure regime, that is, over a wide of pressures including high
pressures up to approximately one atmosphere. The features also provide
uniform susceptor and wafer temperatures, including both absolute
temperature uniformity and spatial uniformity across the susceptor/wafer;
uniform gas flow distribution across the wafer; and effective purging. The
variable parallel close spacing between the electrodes adapts the reactor
to various processes. These features and the temperature control of the
internal and external gas manifold temperatures enable the advantageous
use of very sensitive unstable gases such as ozone and TEOS in processes
such as the following.
That is, the present invention also relates to a method for depositing a
conformal layer of silicon dioxide onto a substrate by exposing the
substrate to a reactive species formed from ozone, oxygen,
tetraethylorthosilicate, and a carrier gas within a vacuum chamber, using
a total gas pressure within the chamber 10 torr to 200 torr and a
substrate temperature within the range of about 200.degree. C. to
500.degree. C. Preferably, a substrate temperature of about 375.degree. C.
.+-.20.degree. C. is used to obtain maximum deposition rates and the
chamber pressure is about 40 torr to 120 torr. In still another aspect,
the present invention is embodied in a method for depositing silicon
dioxide onto a film or substrate by exposing the substrate to the plasma
formed from tetraethylorthosilicate, oxygen and a carrier gas in a chamber
using a total gas pressure within the range of about 1 to 50 torr, and a
substrate temperature in the range of about 200.degree. C. to 500.degree.
C. Preferably, the chamber pressure is 8-12 torr and the substrate
temperature is about 375.degree. C..+-.20.degree. C.
In still another aspect, the invention is directed to a method for
isotropically etching a silicon dioxide surface comprising the step of
exposing a silicon dioxide surface to a plasma formed from fluorinate gas
such as NF.sub.3, CF.sub.4 and C.sub.2 F.sub.6 in a carrier gas in a
chamber using a wafer temperature in the range of from about 200.degree.
C. to 500.degree. C. Preferably, the chamber pressure is within the range
of about 200 mT to 20 torr, and 500 mT to 10 torr.
The invention is also embodied in a method for planarizing a non-planar
dielectric coating or composite within a vacuum chamber by depositing a
conformal layer of silicon dioxide onto the coating by exposing the
coating to a reactive species formed from ozone, oxygen,
tetraethylorthosilicate and a carrier gas, the total chamber gas pressure
being within the approximate range 10 torr to 200 torr and the substrate
temperature being within the approximate range 200.degree. C. to
500.degree. C., to thereby form a composite of the conformal layer on the
substrate; and isotropically etching the outer surface of the resulting
composite layer. Preferably, this planarizing process uses the plasma
oxide deposition to first form a layer of silicon oxide and also uses the
isotropic etch described above
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other aspects and advantages of the present invention are
described in conjunction with the following drawing figures, in which:
FIG. 1 is a top plan view of a preferred embodiment of the combined
CVD/PECVD reactor of the present invention, shown with the cover pivoted
open;
FIG. 2 is a vertical cross-section, partly in schematic, taken along line
2--2 in FIG. 1, with the reactor cover closed;
FIG. 3 is a vertical cross-section through the wafer elevator mechanism,
taken along line 3-3 in FIG. 1;
FIGS. 4-8 are sequential, highly schematized representations of the
operation of the wafer transport system in positioning wafers within, and
removing wafers from the reactor susceptor;
FIG. 9 is a reduced scale, horizontal cross-section through the
circular-array, radiant lamp heating assembly, taken along line 9--9 in
FIG. 2;
FIG. 10 is an enlarged, partial depiction of FIG. 2 showing the process gas
and purge gas distribution systems in greater detail;
FIG. 11 is a partial, enlarged bottom plan view of the gas distribution
head or manifold;
FIG. 12 depicts an enlarged, vertical cross-section of the RF/gas
feed-through system shown in FIG. 2;
FIGS. 13A-13C schematically depict various alternative embodiments of the
gas feed-through;
FIG. 14 illustrates breakdown voltage as a function of pressure for low
frequency and high frequency RF power without a constant voltage gradient
device;
FIG. 15 illustrates breakdown voltage as a function of pressure with and
without a constant voltage gradient device;
FIG. 16 is a schematic cross-sectional representation of an integrated
circuit which illustrates the arrival angles associated with the
deposition of a layer of material such as dielectric onto a surface of
stepped topography;
FIGS. 17A and 17B are schematic cross-sections, similar to FIG. 16, which
illustrate the effect of trench width on planarization;
FIGS. 18 and 19 are cross-sections of the surface topology of an integrated
circuit, in the manner of FIG. 16, illustrating the conformal, planar
qualities of oxide films resulting from the application of our
planarization process; and
FIGS. 20 and 21 depict the deposition rate as a function of temperature and
pressure, respectively, for our present oxide deposition process.
DETAILED DESCRIPTION OF THE INVENTION
I. CVD/PECVD Reactor
A. Overview of CVD/PECVD Reactor FIGS. 1 and 2 are, respectively, a top
plan view of the preferred embodiment of the single wafer, reactor 10 of
our present invention, shown with the cover pivoted open, and a vertical
cross-section of the reactor 10.
Referring primarily to these two figures and to others indicated
parenthetically, the reactor system 10 comprises a housing 12 (also termed
a "chamber"), typically made of aluminum, which defines an inner vacuum
chamber 13 that has a plasma processing region 14 (FIG. 6). The reactor
system 10 also includes a wafer-holding susceptor 16 and a unique wafer
transport system 18 (FIG. 1) that includes vertically movable wafer
support fingers 20 and susceptor support fingers 22. These fingers
cooperate with an external robotic blade 24 (FIG. 1) for introducing
wafers 15 into the process region or chamber 14 and depositing the wafers
15 on the susceptor 16 for processing, then removing the wafers 15 from
the susceptor 16 and the chamber 12. The reactor system 10 further
comprises a process/purge gas manifold or "box" 26 that applies process
gas and purging gas to the chamber 13, an RF power supply and matching
network 28 for creating and sustaining a process gas plasma from the inlet
gas and a lamp heating system 30 for heating the susceptor 16 and wafer 15
positioned on the susceptor to effect deposition onto the wafer.
Preferably, high frequency RF power of 13.56 MHz is used, but low
frequencies can be used.
The gas manifold 26 is part of a unique process and purge gas distribution
system 32 (FIGS. 2 and 10) that is designed to flow the process gas evenly
radially outwardly across the wafer 15 to promote even deposition across
the wafer and to purge the spent gas and entrained products radially
outwardly from the edge of the wafer 15 at both the top and bottom thereof
to substantially eliminate deposition on (and within) the gas manifold or
box 26 and the chamber 12.
A liquid cooling system 34 controls the temperature of the components of
the chamber 12 including, in particular, the temperature of the gas
manifold or box 26. The temperature of the gas box components is selected
to eliminate premature deposition within the gas box/manifold 26 upstream
from the process chamber 14.
The reactor system 10 includes a unique, RF/gas feed-through device 36
(FIGS. 2 and 12) that supplies process and purge gas to the RF-driven gas
manifold 26 from an electrically ground supply. Applying the RF energy to
the gas box or manifold 26 has the advantage of the wafer residing on the
grounded counter electrode or susceptor 16, which makes possible a high
degree of plasma confinement that would not be achievable if the RF energy
were applied to the wafer and the gas box were grounded. Additionally, the
hardware is mechanically and electrically simpler since electrical
isolation between wafer/susceptor and chamber is not required (or
permitted) Temperature measurement and control of the susceptor/wafer in
the presence of high frequency electric and magnetic fields is greatly
simplified with the susceptor 16 grounded. Also, the feed-through 36 is
rigid, eliminating flexible gas connections and the purge gas flow path
safely carries any leaking process gas into the chamber to the chamber
exhaust. The capability to apply RF power to the gas manifold is made
possible (despite the inherent tendency of high potential RF operation to
form a deposition plasma within the feed-through) by the unique design of
the feed-through, which drops the RF potential evenly along the length of
the feed-through, thus preventing a plasma discharge within.
B. Wafer Transport System 18
As mentioned, this system is designed to transfer individual wafers 15
between the external blade, FIG. 2, and the susceptor 16 and to position
the susceptor 16 and wafer 15 for processing. Referring further to FIG. 1,
the wafer transport system 18 comprises a plurality of radially-extending
wafer-support fingers 20 which are aligned with and spaced about the
periphery of susceptor 16 and are mounted to a semi-circular mounting bar
or bracket 38. Similarly, an array of radially-extending susceptor-support
fingers 22 are spaced circumferentially about the susceptor 16,
interdigitated with the wafer support fingers 20, and are mounted to a
semi-circular bar 40 positioned just outside bar 38. The arcuate mounting
bars 38 and 40 are mounted within a generally semi-circular groove 42
formed in the housing, and are actuated respectively, by vertically
movable elevator assemblies 44 and 46.
As shown in FIG. 3, the susceptor elevator mechanism 44 includes a
vertically movable shaft 48 that mounts the bar 38 at the upper end
thereof. The shaft can be moved vertically up and down by various moving
means 56, including a pneumatic cylinder, or, preferably, a stepper motor
operating via suitable gear drive. Wafer elevator mechanism 46 is similar
to the elevator 44.
The operation of the wafer transport system 18 is summarized by the
sequence depicted schematically in FIGS. 4-8. In FIG. 4, the external
blade 24 (with the wafer 15 to be processed supported thereon) is inserted
via opening 56 into chamber 13 to a position over the susceptor 16. One
example of a suitable blade 24 and associated robot wafer handling system
(and door 25, FIG. 6) is described in co-pending, commonly assigned U.S.
patent application Ser. No. 944,803 (A-44974), entitled "Multiple Chamber
Integrated Process System", filed concurrently in the name of Dan Maydan,
Sasson Somekh, David N. K. Wang, David Cheng, Masato Toshima, Isaac
Harari, and Peter Hoppe which application is hereby incorporated by
reference in its entirety. In this starting position, the wafer fingers
20-20 are positioned between the susceptor 16 and the blade 24.
Next, as shown in FIG. 5, the wafer elevator mechanism 44 raises the
wafer-support fingers 20--20 above the blade 24 to pick up the wafer 15.
The blade 24 is then withdrawn from the chamber 13.
As shown in FIG. 6, after retraction of the blade 24, a pneumatic cylinder
closes door 25 over the blade access slot 56 to seal chamber 13. The
susceptor elevator mechanism 46 is actuated to raise the susceptor-support
fingers 22 and susceptor 16 so that the susceptor 16 lifts the wafer 15
from the fingers 20--20 into position for processing in the area 14
immediately adjacent the gas distribution manifold 26. The spacing, d,
between the wafer 15 and manifold 26 is readily selected by adjusting the
travel of the elevator 46. At the same time, the susceptor fingers 22 and
elevator mounting 46 maintains the horizontal orientation of the susceptor
16 and wafer 15 and parallelism between the wafer 15 and manifold 26
independent of the spacing, d.
After processing, and referring to FIG. 7, the susceptor elevator mechanism
46 lowers the susceptor fingers 22 and the susceptor 16 to deposit the
wafer 15 on the wafer support fingers 20--20. The door 25 is then opened
and blade 24 is again inserted into the chamber 13. Next, as shown in FIG.
8, elevator mechanism 44 lowers the wafer-support fingers 20--20 to
deposit the wafer 15 on the blade 24. After the downwardly moving fingers
20--20 clear the blade 24, the blade is retracted, leaving the fingers 20
and 22 in the position shown in FIG. 4 preparatory to another wafer
insertion, processing and withdrawal cycle.
C. Near-IR Radiant Heating System 30
The radiant heating system shown in FIGS. 2 and 9 provides a reliable,
efficient and inexpensive means for heating the circular susceptor 16 and
wafer 15 (e.g., silicon) in a manner that provides uniform wafer
temperature, accurate absolute wafer temperature and rapid thermal
response at low temperatures, preferably .ltoreq.600.degree. C. In
achieving these objectives, a number of requirements must be met. First,
achieving uniform wafer temperature requires compensating the radiation
losses at the edge of the wafer. Secondly, high efficiency at low wafer
temperatures (.ltoreq.600.degree. C.) requires a high emissivity, high
thermal conductivity susceptor 16 because silicon wafers have low
emissivity at low temperatures in the near-infrared spectrum. In addition,
near-infrared radiation is used to obtain fast heating response and for
transmission through the inexpensive materials such as quartz window 70.
The circular thin susceptor 16 is low thermal capacitance for fast heating
and cooling response. These and the other objectives discussed below are
achieved by the radiation heating system 30 shown in FIGS. 2 and 9.
The heating system 30 preferably comprises an annular array of small,
inexpensive, single-ended vertically oriented lamps 58--58 which provide
radiation in the near-infrared portion of the electromagnetic spectrum. 30
The lamps 58--58 are mounted within an annular circular reflector module
60, preferably of aluminum. The module base 60 is formed from a block of
aluminum, and has a polished annular reflecting channel 62 machined
therein. The channel 62 has an arcuate, generally semi-circular reflecting
base 64. The module 60 and lamps 58--58 are cooled by an annular cooling
passage 66 that is formed within the collimating annular reflector 62.
Connections are provided for the inlet and outlet of cooling liquid which,
typically, is chilled water from a pressurized supply. Power is supplied
to the lamp sockets 63 and associated lamps 58 by an electrical supply
cable 68, typically from a variable power supply which automatically
varies the lamp power based upon a predetermined program setting that is
adapted to the requirements of the particular deposition process
The annularly-collimated light from the vertical oriented lamps 58--58 is
admitted into the chamber via a quartz window 70. Quartz is transparent to
near-IR radiation The transparent quartz window 70 is mounted to the
housing 13 at the bottom of the process chamber 13 using annular seals
72--72 to provide a vacuum-tight interface between the window 70 and the
housing. This mounting arrangement positions the radiant energy heating
source 30 outside the chamber 13 at atmospheric pressure and isolates the
vacuum of the processing chamber and the particulate-sensitive processing
therein from the lamps. A bracket 74 can be joined to the lamp mounting
base 60 and pivotally mounted by pivot pin 76 to a mating bracket 78,
which is joined to the housing 12. (Alternatively, the lamp module can be
bolted in place.) As a consequence of this pivotal mounting of the lamp
assembly 30 external to and isolated from the process chamber 13, the lamp
assembly is readily accessible for maintenance, lamp replacement, etc., by
simply disengaging a clamp 79 to allow the assembly to pivot downwardly
about pin 76.
As mentioned, the lamps 58--58 are small single-ended commercially
available quartz-tungsten-halogen lamps which provide the required
near-infrared radiation. One suitable lamp is the Ansi type "FEL" supplied
by Sylvania, G.E., Ushio or Phillips. Presently, fourteen 0.5 to 1
kilowatt quartz-tungsten-halogen lamps that provide a wavelength of about
0.9 to 1.5 micron provide an annularly-collimated power density of up to
about 94 W/cm.sup.2 at the top of the lamp module. The maximum power
density at the susceptor (substantially directed to the outer .about.1.5
in. radius of a 6 in. diameter susceptor) is .about.17 W/cm.sup.2 taking
all efficiency into account (.about.15-16% efficiency). More generally,
lamps concentrating their radiation in the range of about 0.7 to 2.5
microns wavelength would be particularly useful. The aluminum base 60 and
concave-bottom, annular groove 62 provide a high collection-efficiency
collimating reflector which directs a higher radiation power density at
the susceptor edge than at the middle. This non-uniform, concentrated
radiation heats the susceptor wafer circumferentially, which compensates
the wafer edge heat losses and, thus, provides uniform wafer temperature
over a wide range of chamber gas pressures and wafer temperatures.
In short, the desired uniform radiant wafer heating is provided by small,
inexpensive lamps mounted in a compact simple aluminum module 60 that is
easily cooled and maintained at a low temperature, and does not require
plating. In addition, the use of the near-IR lamps and a thin, low mass,
low thermal capacity, high emissivity susceptor of material such as
graphite, provides maximum efficiency, fast thermal response, excellent
temperature uniformity and transmission through the quartz window 70.
Other susceptor materials include anodized aluminum, graphite coated with
layers such as aluminum oxide (Al.sub.2 O.sub.3), or silicon carbide, or a
composite ceramic coated with Al.sub.2 O.sub.3 or SiC or other materials.
Also, interchangeable modules 60 having channels of different heights or
diameters can be used to accommodate different susceptor and wafer
diameters. A present version of the reactor is designed for 5-6 in.
wafers. However, different lamp modules can be provided for smaller or
larger diameter wafers by changing the module height and/or the radius of
the module and the filament circle. Finally, the heating system 30 may
employ a controller (not shown) such as a closed loop temperature control
system using phase angle power control to provide rapid thermal response
and rapid wafer temperature stability.
It should be noted that the simplicity, low mass and high performance
characteristics of the heating system 30 are in contrast to prior wafer
heating approaches which typically use a rectangular array of double-ended
quartz-tungsten-halogen lamps. Conventional radiation heating practice has
been to use a more massive susceptor and, if excellent temperature
uniformity is required, to merely block radiation from the wafer center,
thus sacrificing efficiency, rather than redirecting radiation. The
advantages of the radiant heating system 30 over the conventional
practices include in addition to the aforementioned uniform wafer
temperature and much faster response time (both heating and cooling),
smaller, less bulky more easily maintained equipment of higher reliability
(long lamp lifetime); more efficient operation; and lower cost.
The use of the easily accessible, external radiant heat source 30 is
facilitated and maintained by a gas purge system. As described in the
succeeding section, this system directs purge gas flow across the vacuum
side of the quartz window 70 to prevent deposition on the window and keep
the window clean. Thus, the purge is a major contributor to lamp
efficiency. This increases the number of process cycles between cleaning
and, as a result, decreases the associated system downtime required for
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