Direct memory access apparatus and methods for transferring data between buses having different performance characteristics

What is claimed is:

1. Direct memory access means having a plurality of operating states each indicated by a status signal for transferring data to and from a first bus to which a first set of devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of devices, having performance characteristics differing from said first set of devices, is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices without adversely affecting the performance of said first set of devices and said second set of devices, comprising:

(a) access means, operating independent of CPU intervention, coupled to said first bus and to said second bus, including at least one direct memory access channel means for determining data transfer addresses, wherein said direct memory access channel means has said plurality of operating states each of which is indicated by a status signal, and further wherein said access means is utilized for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus;

(b) means for interconnecting said first bus to said access means;

(c) means for interconnecting said second bus to said access means; and

(d) a set of internal registers included within said access means, coupled to and receiving inputs from said first bus, wherein said set of internal registers are accessed by said direct memory access channel means for determining said data transfer addresses, where the contents of the set of internal registers are used for controlling and maintaining a given direct memory access channel operating state and the status indication associated therewith.

2. Direct memory access means as set forth in claim 1 wherein said means for interconnecting said second bus to said access means further comprises packing and funneling network means, coupled to said access means, for accommodating variable width data transfers between said first bus and said second bus.

3. Direct memory access means as set forth in claim 2 further comprising means coupled to said second bus, for prioritizing access to said channel means whenever a plurality of direct memory access channel means exists.

4. Direct memory access means as set forth in claim 2 wherein said access means further, comprises:

(a) queue means, coupled to both said first and second buses for buffering data being transferred between said first bus and said second bus; and

(b) programmable internal register means for controlling the operation of said queue means.

5. Direct memory access means as set forth in claim 4 wherein each of said direct memory access channel means further comprises:

(a) first multiplexing means for selectively transferring word length data input to said access means from said first bus and for selectively transferring packed data, input to said access means from said packing and funneling network means, into said queue means;

(b) first packing/funneling register means, coupled to said first mutiplexing means and said packing and funneling network means, for storing data during packing and funneling operations;

(c) second multiplexing means for selectively transferring data output from said queue means, to be funneled to said packing and funneling network means via said first packing/funneling register means, and for selectively transferring packed data input from said packing and funneling network to said first multiplexing means via said first packing/funneling register means.

6. Direct memory access means as set forth in claim 4 wherein the data buffered in said queue means may be directly manipulated by said CPU to avoid latency associated with data transfers between said first bus and said queue means.

7. Direct memory access means as set forth in claim 4 further comprising means, coupled to said second bus and said queue means, for performing bus sizing.

8. Direct memory access means as set forth in claim 2 wherein said packing and funneling network means further comprises:

(a) means for packing data on a transfer from said second bus to said first bus, including means for converting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and

(b) means for buffering data being packed, by said means for packing data, in order to facilitate full word transfers of packed data to said first bus.

9. Direct memory access means as set forth in claim 2 wherein said packing and funneling network means further comprises:

(a) means for funneling data on a transfer from said first bus to said second bus, including means for converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus; and

(b) means for buffering data being funneled, by said means for funneling, in order to enable said means for funneling to extract half words and bytes of buffered data one at a time for transfer to said second bus.

10. Direct memory access means as set forth in claim 1 wherein said means for interconnecting said first bus to said access means further comprises means for initializing said set of internal registers.

11. Direct memory access means as set forth in claim 10 further comprising a plurality of signal paths used for carrying signals between said CPU and said set of internal registers, in order to initialize and control data transfer operations.

12. Direct memory access means as set forth in claim 11 wherein said plurality of signal paths comprise the pins of an integrated circuit package.

13. Direct memory access means as set forth in claim 1 wherein said access means is programmable.

14. Direct memory access means as set forth in claim 13 wherein said access means is programmed during initialization by said CPU to determine data transfer addresses independent of said CPU during transfer operations.

15. Direct memory access means as set forth in claim 1 further comprising means for decoupling the operation of said access means from program execution by said CPU to thereby permit said CPU and said access means to operate concurrently.

16. Direct memory access means as set forth in claim 1 wherein said access means further comprises means for performing nonsequential transfers independent of CPU intervention.

17. Direct memory access means as set forth in claim 1 wherein said access means further comprises transfer rate control means for controlling the rate of data transfer between said first bus and said second bus.

18. Direct memory access means as set forth in claim 1 operative to permit direct memory access channel means operation to overlap with the operation of said set of devices attached to said first bus.

19. Direct memory access means as set forth in claim 1 further comprising means, coupled to both said first and second buses, for performing data packing and unpacking.

20. Direct memory access means as set forth in claim 1 further comprising means, coupled to both said first and second buses, for swapping data packet location in words being transferred.

21. Direct memory access means as set forth in claim 1 wherein said access means further comprises means for decoupling the latency and bandwidth of accesses on said first bus from the latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses.

22. Direct memory access means as set forth in claim 1 wherein said access means may be configured to support block and pattern transfers between said first and second buses.

23. Direct memory access means as set forth in claim 1 suitable for transferring data between two synchronous buses.

24. Direct memory access means as set forth in claim 1 suitable for transferring data between two asynchronous buses.

25. Direct memory access means as set forth in claim 1 having a test mode of operation.

26. Direct memory access means as set forth in claim 1 operable in parallel with at least one data transfer controller, to which it is connected, in a master/slave relationship.

27. A method for transferring data to and from a first bus, to which a first set of devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of devices, having performance characteristics differing from said first set of devices, is attached, comprising the steps of:

(a) transferring data between said first bus and said second bus, at a variable transfer rate, utilizing direct memory access means, for performing a CPU independent data transfer, wherein said direct memory access means includes at least one direct memory access channel means, coupled to said buses for determining data transfer addresses, wherein said direct memory access channel means has a plurality of operating states each of which is indicated by a status signal, and further wherein said direct memory access means is utilized for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus;

(b) decoupling, via said direct memory access channel means, the latency and bandwidth of accesses on said first bus from the latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses, so that the performance of said first set of devices and said second set of devices each having differing performance characteristics are not adversely affected when transferring data between said first and second bus via said direct memory access means; and

(c) initializing a set of registers included within said direct memory access means, coupled to said first bus, wherein said set of registers are accessed by said direct memory access channel means for determining said data transfer addresses, where the contents of said set of registers are used for controlling said direct memory access means.

28. A method as set forth in claim 27 wherein said step of transferring further comprises the step of packing data being transferred from said second bus to said first bus to accommodate variable width data transfers.

29. A method as set forth in claim 28 wherein said step of transferring further comprises the step of funneling data being transferred from said first bus to said second bus to accommodate variable width data transfers.

30. A method as set forth in claim 29 wherein said step of transferring further comprises the step of multiplexing address signals and data signals being transferred to said second bus by said direct memory access means.

31. A method as set forth in claim 29 wherein said step of decoupling via said direct memory access channel means further comprises the step of storing data being transferred between said first bus and said second bus, into a storage means, having a queue organization, used for buffering data, under the control of programmed register means used for controlling said buffering.

32. A method as set forth in claim 31 wherein the step of decoupling via said direct memory access channel means further comprises the step of multiplexing word length data input to said direct memory access means from said first bus with packed word length data being transferred via said direct memory access means from said second bus, for buffering in said storage means.

33. A method as set forth in claim 31 wherein the data buffered in said storage means may be directly manipulated by said CPU to avoid the latency associated with data transfers between said first bus and said storage means.

34. A method as set forth in claim 27 wherein the step of transferring further comprises the step of funneling data on a transfer from said first bus to said second bus wherein said step of funneling further includes the step of converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus.

35. A method as set forth in claim 34 wherein said step of converting further comprises the steps of:

(a) buffering data being funneled; and

(b) extracting half words and bytes of buffered data, one at a time, for transfer to said second bus.

36. A method as set forth in claim 27 wherein said step of transferring further comprises the step of prioritizing access to said direct memory access channel means whenever a plurality of channel means exists.

37. A method as set forth in claim 27 wherein said step of transferring further comprises the step of checking parity for both data and address transfers.

38. A method as set forth in claim 27 wherein said step of decoupling when transferring via said direct memory access means is accomplished by decoupling the operation of said direct memory access means from program execution by said CPU.

39. A method as set forth in claim 27 wherein said step of decoupling via said direct memory access channel means further comprises the step of initializing, via said CPU during initialization, said direct memory access means to determine data transfer addresses independent of the CPU operation.

40. A method as set forth in claim 27 wherein said step of transferring via said direct memory access means is performed nonsequentially.

41. A method as set forth in claim 27 wherein the step of decoupling via said direct memory access channel means further comprises the step of controlling said variable transfer rate between said first bus and said second bus.

42. A method as set forth in claim 27 wherein the step of transferring further comprises the step of performing bus sizing.

43. A method as set forth in claim 27 wherein said step of decoupling via said direct memory access channel means further comprises the step of overlapping direct memory access channel means operation with the operation of said set of devices attached to said first bus.

44. A method as set forth in claim 27 wherein the step of transferring further comprises the steps of:

(a) packing data on a transfer from said second bus wherein said step of packing further includes the step of converting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and

(b) buffering data being packed in order to facilitate full word transfers of packed data to said first bus.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to methods and apparatus used for transferring data to and from a first bus, to which a first set of high performance devices, including a central processor ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the CPU's performance. The preferred embodiment of the invention more particularly relates to novel direct memory access ("DMA") apparatus and methods suitable for performing the aforesaid data transfer function between a high performance channel, hereinafter referred to as the "Local Bus", to which a CPU constituting a part of a reduced instruction set computer (RISC) system is attached, and one or more, typically lower performance, peripheral buses, each hereinafter referred to as a "Remote Bus". The novel DMA may be used as part of a data transfer controller ("DTC") having other components, such as I/O ports, or may be used independently for transferring data between unmatched buses in, for example, computer systems, data transmission systems, and the like.

2. Description of the Related Art

Methods and apparatus for achieving a high performance system interface between a RISC processor and a set of devices, including memory means internal to the RISC system, are described in copending application Ser. No. 012,226, filed 2/19/87, assigned to Advanced Micro Devices, Inc. This copending application is hereby incorporated by reference. The novel system interface taught in the copending application includes, according to its preferred embodiment, two 32 bit wide buses referred to as the "Address Bus" and "Data Bus". For the purpose of this application these two buses collectively correspond to the Local Bus.

In order to permit a RISC system to utilize and access a wide array of commercially available peripheral devices that typically operate at lower speeds than a RISC processor, the Local Bus needs to be coupled in some manner to a Remote Bus to which one or more of said peripheral devices are connected. The Remote Bus could also be a complete I/O subsystem with its own processor.

Currently, no devices or methods are known which interconnect and permit data transfers between buses having different performance characteristics (like the aforesaid Local Bus and Remote Bus),while at the same time not appreciably having an affect on the performance of the devices attached to the buses. In addressing this problem it would be a particularly desirable feature to insulate the performance of any high speed processor, e.g., a RISC processor attached to the Local Bus, from the comparatively lower performance of peripherals and/or any I/O subsystem connected to the Remote Bus. Ideally, the bandwidth and latency of accesses on the Local Bus needs to be decoupled from the bandwidth and latency of accesses on the Remote Bus, with concurrency between accesses on both buses.

Another problem to be solved is to provide methods and apparatus which allow I/O port and direct memory access ("DMA") operations to overlap with (i.e., operate in parallel with) devices attached to the Local Bus. Such a parallelism feature would further enhance the performance of the overall system of which the DTC forms a part and more particularly, in a RISC system, would free the RISC processor from having to wait for I/O completion.

I/O controller functions and DMA functions in and of themselves are well known in the prior art. However no combination of these functions are performed by any known methods or apparatus which, (1) interconnect and buffer a high performance RISC system Local Bus and a Remote Bus of the type described hereinbefore; (2) solve the aforementioned problem of interconnecting buses having different performance characteristics and (3) provide the parallelism referred to hereinbefore.

Furthermore, no DMA channel by itself is known which supports a bus to bus interface of the type described hereinabove, i.e., a DMA channel which accounts for differing bus characteristics and parallelism versus a DMA channel that only performs straight address sequencing.

Finally, although systems, such as the IBM 370 (a large main frame computer) are known that include a channel controller network with direct memory access features, no prior art is known at the microprocessor level, in particular in combination with a RISC processing system, that provides both DMA and I/O controller functions on a single chip. Such features would be a desirable adjunct to RISC processing systems which themselves are currently being fabricated at the chip level.

SUMMARY OF THE INVENTION

According to the invention, methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the aforesaid transfer function in a manner that facilitates communication between the first and second set of devices while insulating the performance of the first set of devices from the comparatively lower performance of the second set of devices.

According to the preferred embodiment of the invention, data memory access ("DMA") apparatus and methods are disclosed that include a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DMA interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.

It is an object of the invention to provide methods and apparatus that interconnect and permit data transfers between buses having different performance characteristics (like the aforesaid Local Bus and Remote bus), while at the same time not appreciably having an affect on the performance of the devices attached to the buses.

It is a further object of the invention to provide methods and apparatus which permit a RISC system to utilize and access a wide array of commercially available peripheral devices that typically operate at lower speeds than a RISC processor.

It is still a further object of the invention to insulate the performance of any high speed processor, e.g., a RISC processor attached to a Local Bus, from the comparatively lower performance of peripherals and/or any I/O subsystem connected to a Remote Bus in a manner in which the bandwidth and latency of accesses on the Local Bus may be decoupled from the bandwidth and latency of accesses on the Remote Bus, with concurrency between accesses on both buses.

Further yet, it is an object of the invention to provide methods and apparatus which allow DMA operations to overlap with (i.e., operate in parallel with) devices attached to the Local Bus in order to enhance overall system performance.

The preferred embodiment of the invention meets the aforesaid objects in the context of a RISC processing environment, with both the RISC processor and DTC being fabricated at the chip level.

The invention features a reduction in the amount of hardware required to connect peripherals on the Remote Bus to the Local Bus. Additional features of the invention include the flexibility to perform bus sizing, data packing and unpacking, and conversions between byte and half word data packed into words.

These and other objects and features of the invention will become apparent to those skilled in the art upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts the novel DTC interfacing, in accordance with the preferred embodiment of the invention, with a RISC system via a Local Bus, and interfacing with a Remote Bus to which a set of peripherals, I/O subsystem, etc. may be attached.

FIG. 2 depicts a pin-out diagram for an integrated circuit package that houses the novel DTC and facilitates its interconnection, in accordance with the preferred embodiment of the invention, to both a RISC system via a Local Bus and to a set of peripherals via a Remote Bus.

FIG. 3 is a functional block diagram of a DTC, built in accordance with the teachings of the invention, having 4 I/O ports and 4 DMA channels.

FIG. 4 depicts the established conventions for the location of bytes and half-words within half-words and words, which are supported by the novel DTC taught herein.

FIG. 5 illustrates the swapping of bytes within half-words and words when the DTC is used to convert between the addressing conventions depicted in FIG. 4.

FIG. 6 is a block diagram illustrating I/O port data flow for one I/O port.

FIG. 7 is a flow chart illustrating how the DTC supports overlapped I/O.

FIG. 8 is a block diagram illustrating DMA channel data flow for one DMA channel.

FIG. 9 illustrates empty, partially full and full DMA queues.

FIG. 10 is an example of how commercially available devices may be used to interconnect the novel DTC to the Remote Bus.

FIG. 11 illustrates data location for Local Bus data transfers, on D0-D31, both to and from the novel DTC.

FIG. 12 illustrates data location for Remote Bus data transfers, on RAD0-RAD31, both to and from the novel DTC.

DETAILED DESCRIPTION

According to the preferred embodiment of the invention, the DTC implements four address-mapped input/output ports on the Local Bus. These ports provide a gateway from the Local Bus to the Remote Bus, so that a processor attached to the Local Bus can directly access devices and memories on the Remote Bus.

Each I/O port, according to the preferred embodiment of the invention, is a power-of-two number of bytes in size, and can begin on any corresponding power-of-two address boundary on the Local Bus. The ports can appear on the Local Bus in either the data-memory address space or the I/O address space. These address spaces are defined in the incorporated copending application. The ports are address-mapped, so that addressing on the Local Bus is independent of addressing on the Remote Bus. Optional read-ahead and write-behind features on these ports allow Remote-Bus accesses to be overlapped with Local-Bus accesses. These features will be described in detail hereinafter.

The DTC also implements four buffered DMA channels, supporting DMA transfers from the Remote Bus to the Local Bus, and from the Local Bus to the Remote Bus. For DMA accesses, data, according to the preferred embodiment of the invention, is buffered in one of four 64-word queues. There is one queue per DMA channel.

The DMA queues reduce the overhead of DMA transfers on the Local Bus, by allowing the transfers of large amounts of data for each Local-Bus acquisition. This is particularly effective if the burst-mode capability, as described in the incorporated copending application, of the Local Bus is used. The queues may be manipulated directly by software executing on, for example, the RISC processor.

As indicated hereinabove, FIG. 1 depicts, in block diagram form, the DTC interconnecting a Local Bus of a RISC system with a Remote Bus.

More particularly, the DTC, unit 104, is shown interconnected to 32 bit Address Bus 111 and 32 bit Data Bus 112 via links 111a and 112a respectively.

It should be noted that the Local Bus referred to herein and shown as Local Bus 110 in FIG. 1, is comprised of Address Bus 111 and Data Bus 112.

RISC processor 101, Program Store 102, Data Memory 103, the interconnections between these devices i.e., 111b, 111c, 111d and 112b, Address Bus 111 and Data Bus 112, are all described in detail in the incorporated copending application. The novel DTC will be described herein in the context of the RISC system set forth in the copending application for the sake of illustration only. One of ordinary skill in the art will readily appreciate how the DTC may be adapted to provide an interface for devices having different performance characteristics without departing from the spirit and scope of the invention described herein.

Not shown in copending application Ser. No. 012,226 are DTC 104 and interface unit 105. Interface unit 105 may, but is not required to, be used to interconnect DTC 104 to Remote Bus 120. Both units 104 and 105 will be described in detail hereinafter.

According to the preferred embodiment of the invention, DTC 104 is implemented in 1.2 micron CMOS technology, and is packaged in a 169-terminal pin-grid-array (PGA) package, using 148 signal pins, 20 power and ground pins, and one alignment pin.

FIG. 2 depicts a pin-out diagram for DTC 104. Integrated circuit package 204 of FIG. 2 houses the novel DTC and facilitates its interconnection, in accordance with the preferred embodiment of the invention, to both the RISC system, depicted in FIG. 1, via Local Bus 110, and to a set of peripherals via Remote Bus 120. The Local Bus connections to and from the DTC are shown on the left hand side of dotted line A--A in FIG. 2, and the Remote Bus connections to and from the DTC are shown on the right hand side of dotted line A--A in FIG. 2.

Before proceeding with the description of how the interface may be utilized, a set of DTC input and output signals has, in accordance with the preferred embodiment of the invention, been defined to facilitate the communication of both substantive and control information between DTC 104 and the devices connected to it via Buses 110 and 120. These signals are in one to one correspondence with the pins shown in the pin-out block depicted in FIG. 2.

A description of the signals input to and output from DTC 104 via the integrated circuit depicted in FIG. 2, along with the description of how the DTC may be utilized to support communications between Local Bus 110 and Remote Bus 120 (to be described in detail hereinafter), will illustrate the DTC's operability and utility. One of ordinary skill in the art will readily appreciate that the same teaching of how to use and control the DTC as an interface between a RISC Processor attached to Bus 110 and devices attached to Bus 120, may be extended to teach how to use and control the DTC to facilitate communication between sets of devices having different performance characteristics, attached to buses which are interconnected via the DTC.

For the sake of illustration and consistency with the incorporated copending application, a 32 bit instruction and data word architecture for the RISC system is assumed. One of ordinary skill in the art will appreciate that the illustrative embodiment in no way limits the implementation or scope of the invention with respect to computer systems having different word lengths.

Reference should now be made to FIG. 2 which depicts each input and output, to and from DTC 104 of the preferred embodiment of the invention, in the pin-out block form.

Focusing on the Local Bus inputs and outputs first, (left hand side of FIG. 2) Address Bus 111 and Data Bus 112 of FIG. 1 are depicted interconnected to block 104 of FIG. 2 via a 64 pin bus interconnect comprised of two sets of 32 pins each. The first set of 32 pins serves to interconnect bus 111 of FIG. 1 to DTC 104 and is labeled "A0-A31" in FIG. 2. The second set of 32 pins, for the separate and independent data bus, bus 112 of FIG. 1, is labeled "D0-D31" in FIG. 2

Before proceeding with the FIG. 2 pin description, it should be noted that the term "three state" is used hereinafter to describe signals which may be placed in the high-impedance state during normal operation. All outputs (except MSERR) may be placed in the high impedance state by the *TEST input. Both MSERR and *TEST will be described hereinafter with reference to the FIG. 2 pin description.

Returning to the description of the Local Bus signals, it should noted that all Local-Bus signals are synchronous to SYSCLK. SYSCLK is described in the incorporated copending application.

The A0-A31 (Address Bus) pins are bidirectional, synchronous and three state. The Address Bus transfers the byte address for all Local-Bus accesses except burst-mode accesses. For burst-mode accesses, it transfers the address for the first access in the sequence.

The D0-D31 (Data Bus) pins are bidirectional, synchronous and three state. The Data Bus transfers data to and from DTC 104 on the DTC's Local Bus side.

All of the other pins and signals on the Local Bus side of line A--A of FIG. 2 are, with the exception of *CSEL, DP0-DP3 and *INTR, described in the incorporated copending application. However, for the sake of clarity and completeness, a review of the purpose of each of these pins and signals in the context of DTC 104 will now be set forth in addition to the description of the pins and signals not described elsewhere. All the pin and signal descriptions to follow are in accordance with the preferred embodiment of the invention.

SYSCLK (System Clock) is an input to DTC 104. The input is a clock signal operating at the frequency of the Local Bus. DTC 104 uses this signal to synchronize all Local-Bus accesses.

*BREQ (Bus Request) is a synchronous, active LOW, DTC 104 output which is used to arbitrate for the Local Bus.

*BGRT (Bus Grant) is a synchronous, active LOW, DTC 104 input that informs DTC 104 that it has control of the Local Bus. It may be asserted even though *BREQ is inactive. If DTC 104 cannot use a granted Local Bus, it asserts *BINV (to be described hereinafter) to create an idle Local-Bus cycle.

*CSEL (Chip Select) is a synchronous, active LOW, DTC 104 input. DTC 104 may, according to the preferred embodiment of the invention, be configured to recognize a Local-Bus request either as the result of an address decode or as the result of an active level on *CSEL. This input is relevant only for accesses to internal DTC 104 registers which, to the extent required to teach the invention, will be described hereinafter.

*BINV (Bus Invalid) is a synchronous, active LOW, DTC 104 output that indicates that Address Bus 111 and related controls are invalid. It defines an idle cycle for the Local Bus. The pin itself is bidirectional.

*DREQ (Data Request) is a bidirectional pin. The signal on this pin is synchronous, three state and active LOW. This signal indicates an active data access on the Local Bus. When it is asserted, the address for the access appears on Address Bus 111.

The DREQT0 - DREQTl (Data Request Type) signals are synchronous and three state. These signals specify the address-space for a data access on the Local Bus, as follows (the value "x" is a don't care):

______________________________________ DREQT1 DREQT0 Meaning ______________________________________ 0 0 Instruction/data memory access 0 1 Input/output access 1 x Coprocessor transfer (ignored by DTC 104) ______________________________________

R/*W (Read/Write) is a bidirectional, synchronous, three state signal. When the DTC 104 is a Local Bus slave, this signal indicates whether data is being transferred from the Local Bus processor to DTC 104 (R/*W LOW) or from DTC 104 to the processor (R/*W HIGH). When DTC 104 is the Local Bus master, this signal indicates whether data is being transferred from DTC 104 to the Local Bus memory (R/*W LOW), or from the Local Bus memory to DTC 104 (R/*W HIGH).

SUP/*US (Supervisor/User Mode) is a bidirectional pin. The signal output on this pin is synchronous and three state. This output indicates the program mode of the Local Bus processor (Supervisor mode or User mode) during an access. These modes are defined in the incorporated copending application. The internal registers of DTC 104 are protected from User-mode access (either read or write). DTC 104 I/O ports may be protected from User-mode access as an option.

The OPT0-OPTl (Option Control) signals are synchronous and three state. These signals specify the data length for Local Bus accesses. Byte and half-word accesses are valid only for accesses reflected on Remote Bus 120 via an I/O port. According to the embodiment of the invention being used for illustrative purposes, DTC 104 supports only 32-bit transfers on Remote Bus 120. The encoding of these signals is as follows:

______________________________________ OPT1 OPT0 Data Width ______________________________________ 0 0 32-bits 0 1 8-bits 1 0 16-bits 1 1 Invalid ______________________________________

*LOCK (Lock) is a bidirectional, synchronous, active LOW signal used to indicate that an atomic read-modify-write cycle is to be performed on Remote Bus 120. It is significant only for an I/O port access. DTC 104 drives this signal HIGH when it is a local-bus master.

DP0-DP3 (Data Parity) are synchronous, three state, odd byte-parity signals for data stored in the Local Bus memory. The DP0 signal is the byte parity for D0-D7, the DPl signal is the byte parity for D8-D15, and so on. During DMA transfers, DTC 104 allows parity to be transferred to Local Bus 110 from Remote Bus 120 and vice versa. DTC 104 can check for valid parity during either a DMA transfer or a remote-to-local transfer via an I/O port.

*DRDY (Data Ready) is a bidirectional signal that is synchronous and active LOW. For Local Bus reads, this input indicates that valid data is on Data Bus 111. For writes, it indicates that the access is complete, and that data need no longer be driven on Data Bus 112. When DTC 104 is the slave for a Local Bus access, it asserts *DRDY to indicate that it has successfully completed the access (unless *DERR is also asserted). When DTC 104 is the master for a Local Bus access, *DRDY indicates that the Local Bus memory has successfully completed the access (unless *DERR is also asserted).

The *DERR (Data Error) input is synchronous, active LOW and indicates that an error occurred during the current Local Bus access.

*DBREQ (Data Burst Request) is a bidirectional, synchronous, three state, active LOW signal used to establish a burst-mode data access on the Local Bus and to request data transfers during a burst-mode data access.

*DBACK (Data Burst Acknowledge) is a bidirectional, synchronous, active LOW signal that is active whenever a burst-mode data access has been established on the Local Bus (with DTC 104 as either a master or a slave for the access). It may be active even though no data are currently being accessed.

The *INTR (Interrupt Request) output is synchronous, active LOW and may be used by DTC 104 to signal interrupt or trap requests.

The *TEST (Test Mode) input is synchronous, active LOW and when active puts DTC 104 in a test mode. All output and bidirectional lines, except MSERR, are forced to the high-impedance state in this mode.

The MSERR (Master/Slave Error) output is synchronous, active HIGH and shows the result of the comparison of DTC 104 outputs with the signals provided internally to off-chip drivers. If there is a difference for any enabled driver, this signal is asserted.

Finally, for the Local Bus connections to DTC 104, the *RESET (Reset) input is an synchronous, active LOW signal that resets DTC 104.

On the Remote Bus side of the A--A line shown in FIG. 2 the pins and signals are for the following purposes.

It should be noted that all Remote Bus signals, according to the preferred embodiment of the invention, are synchronous to RCLK, which is a clock at the operating frequency of DTC 104's remote bus interface. RCLK is either an output generated at half the frequency of the ROSC input (to be explained hereinafter), or an input from an external clock generator. Remote Bus signals may be either synchronous or asynchronous to this clock.

The ROSC (Remote Oscillator) input is, when DTC 104 generates RCLK for the Remote Bus, an oscillator input at twice the frequency of RCLK. When RCLK is generated by an external clock generator, ROSC should be tied either HIGH or LOW.

The *RBREQ (Remote Bus Request) output is synchronous, active LOW and is used to arbitrate for Remote Bus 120.

The *RBGRT (Remote Bus Grant) input may be either asynchronous or synchronous, is active LOW and signals that DTC 104 has control of Remote Bus 120. It may be active even though *RBREQ is inactive. If DTC 104 has control