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The present invention relates to a stored-program controller having a
conditional branch facility designed to operate at high speed and, thus,
suitable for use in a real-time video signal processor.
In recent years, there has been considerable progress in the field of video
signal compression. Several methods have been developed for reducing the
redundancy in digitally encoded video signals to facilitate their
transmission or storage. Three methods are of particular interest in this
application, hereinafter referred to as absolute encoding, relative
encoding and differential pulse code modulation (DPCM) encoding. These
video compression techniques are described below.
An absolute encoded image is developed by partitioning an image into a
plurality of contiguous segments and then assigning a fill value to each
segment. This fill value may be a fixed luminance and/or chrominance value
or it may be a value that varies from pixel to pixel as a function of the
location of the pixel within the segment. When an absolute encoded image
is decoded and displayed, the result is a mosaic composed of the
reconstructed segments.
The absolute encoding technique produces a plurality of data records, each
one describing a different segment of the original image. Each of these
records includes several fields, where each field includes one or more
binary words. An exemplary record from an absolute encoded image is shown
in FIG. 1A. This record includes two one-byte fields, X POS, and Y POS,
which indicate the respective horizontal and vertical position of the
pixel in the upper left corner of a segment. The record further includes a
one-byte field W and a one-byte field H which indicate the number of
pixels in the respective horizontal and vertical directions that define
the segment. The last three fields in the absolute code record A, B and C,
determine how the segment is filled. These values are the coefficients of
a bilinear equation (1) which describes how the value, PV, of a particular
pixel is determined.
PV=AX+BY+C (1)
In the equation (1), C is a one-byte value representing, for example, the
luminance level in the upper left corner of the segment. A and B are each
two-byte values representing amounts by which the luminance value changes
between successive pixels in the horizontal and vertical directions,
respectively. X and Y are values which indicate the position of the pixel
within the segment relative to the upper left corner of the segment. This
example of an absolute code record assumes separate groups of records for
each of the luminance and/or color information signal components of the
video signal, and assumes that all of the segments are rectangular. A more
general example of an absolute encoding system may be found in an article
by M. Kocher and R. Leonardi entitled "Adaptive Region Growing Technique
Using Polynomial Functions For Image Approximation", Signal Processing
(Netherlands) Vol. 11, No. 1, July 1986, pp. 47-60, which is hereby
incorporated by reference.
The second video signal compression method set forth above, relative
encoding, involves partitioning the image into contiguous segments which
are defined in terms of corresponding segments from the previous image of
a multi-image sequence. This encoding method is appropriate for a set of
video fields that represent full motion video. An image encoded using this
method is represented by a plurality of data records. An exemplary record
is shown in FIG. 1B. The fields X POS, Y POS, W and H are the same as in
the absolute record. The two one-byte fields .DELTA.X and .DELTA.Y
indicate the pixel displacement in the horizontal and vertical directions,
respectively, of the segment in the current video field relative to its
corresponding segment in the previous video field. These displacement
values may be in units of a fraction of the distance between adjacent
pixels in the display image.
The fields A, B and C in the relative code record are similar to the
corresponding fields in the absolute code record. These values are used as
the coefficients of the bilinear equation (1) to develop values which are
added to the pixel values in the segment.
The record format for relative coded images also assumes that the segments
are rectangular and that only one of the luminance and color information
components of an image is described by a given record. A general
description of the complexities of relative encoding is presented in an
article by S. Brofferio and F. Rocca entitled "Interframe Redundancy
Reduction of Video Signal Generated by Translating Objects", IEEE
Transactions on Communications, April 1977 pp. 448-455, which is hereby
incorporated by reference.
The third encoding method listed above, DPCM, in general describes each
pixel in an image as the sum of a predicted pixel value and a differential
pixel value. This method is applied to segments in an image which are not
easily described by absolute or relative code records. An example of a
DPCM record is shown in FIG. 1C. The fields X POS, Y POS, W and H for this
record are the same as for the absolute code record and relative code
record set forth above. The remainder of the DPCM code record is a series
of N bytes where N is the product of the values held in the W and H field.
The first of these N bytes, DP.sub.0 is a differential value which, when
added to a fixed predicted value of, for example, 128, produces the pixel
in the upper left corner of the segment. The next byte, DP.sub.1, is a
difference value, which, when added to the sum 128+DP.sub.0, produces the
next successive pixel value on the top line of the segment. Similarly, the
value DP.sub.2 is a difference value which, when added to the accumulated
sum of 128, DP.sub.0 and DP.sub.1 produces the third pixel value on the
top line of the segment. The successive values in the DCPM code record
each describe a pixel value as the accumulation of the preceding values in
the record. An example of a video signal compression system which uses the
DPCM encoding technique may be found in U.S. Pat. 4,125,861 entitled
"Video Signal Encoding", which is hereby incorporated by reference.
If the DPCM data were stored or transmitted as shown in FIG. 1C, there
would be little or no advantage to using the DPCM encoding technique since
each of the values that describes a pixel occupies one data byte, the same
as a non-encoded pixel value. However, as set forth in the referenced
patent 4,125,861, the frequency of occurrence of encoded bytes having
relatively small values is much larger than the frequency of occurrence of
encoded bytes having relatively large values. This unequal distribution of
the encoded bytes is used in the referenced patent to further compress the
video data stream by encoding the smaller-valued samples in a smaller
number of bits than are used for the larger-valued samples. Variable
length statistical encoders which perform this type of compression are
known in the art. An algorithm for generating a code of this type, a
Huffman Code, is described in a section of a book by N. Abramson entitled
"Information Theory and Coding", McGraw Hill, 1963 pp. 77-85, which is
hereby incorporated by reference.
Each of the encoding methods described above work well on some types of
video information and poorly on others. The absolute encoding technique is
best for still images or for the first video field of a motion sequence,
when the image to be encoded includes relatively large areas of uniform or
linearly varying luminance or color information. The relative coding
technique is best for the second and subsequent video fields of a motion
sequence. The DPCM encoding technique is best for images containing areas
of finely detailed information.
Due to the different types of video information that are efficiently
represented by these codes, it may be desirable to combine two or more of
the codes to represent a single video image. For example, the combination
of absolute encoding and DPCM encoding would produce a compact
representation of an image that includes both low and high levels of
detail. For motion sequences, it may also be desirable to represent
portions of the image using the relative encoding techniques. As shown in
FIGS. 1A, 1B and 1C, these three encoding methods can be tailored to
produce compatible record formats.
Once so encoded, however, it would be desirable for the image to be decoded
rapidly so that the reproduced images may be displayed with natural detail
and motion.
The circuitry used to decode an encoded image of this type would desirably
include various processing elements which are conditioned to act in
concert under the control of a stored-program controller. One type of
stored-program controller which may be used is a microcode sequencer such
as is found in many current microprocessor integrated circuits. A general
discussion of microcode sequencer design may be found in a textbook by H.
W. Gschwind, entitled Design of Digital Computers, An Introduction,
Springer-Verlang, 1967, pp. 379-387, which is hereby incorporated by
reference. As set forth in this discussion, the implementation of a
conditional branch operation is an important consideration in designing a
microcode sequencer.
A conditional branch operation effects a change in the sequence of
microcode instructions provided by the microcode sequencer in response to
the occurrence of a particular condition in processing circuitry external
to the microcode sequencer. Such a condition may be, for example, that the
value held in a specified register is zero. If, when the conditional
branch operation is invoked, the specified condition is met, one sequence
of microcode instructions is provided by the microcode sequencer. If the
condition is not met, another independent sequence of instructions is
provided.
In a video signal processor which processes encoded data, such as that
described above, to produce a real-time full motion display, the speed of
the decoding processor is an important consideration. The implementation
of the conditional branch operation may significantly affect the
performance of the decoding processor. Each of the conditional branch
operations described in the above-referenced textbook, for example, may
require as much as one extra instruction cycle when the first instruction
in one of the alternate sequences of instructions is not the next
instruction scheduled to be provided. In this instance, the additional
instruction cycle may be needed to set up a new address value for the
random access memory which holds the microcode instructions and to read
the target instruction.
It would be desirable to provide a stored-program controller which did not
have a significant time penalty for either outcome of a conditional branch
operation.
SUMMARY OF THE INVENTION
The present invention is embodied in a stored-program controller of a data
processing system. The stored-program controller includes an addressable
memory for holding a plurality of instruction values and an instruction
decoder which, responsive to instruction values provided by said memory,
controls processing circuitry in the data processing system. In response
to an address value provided by the instruction decoding circuitry, two
instruction values are read from the memory by circuitry internal to the
stored-program controller. When the instruction held in the instruction
decoding circuitry invokes a conditional branch operation, the value of a
condition in processing circuitry external to the stored-program
controller determines which of the two instructions read from the memory
is the next instruction applied to the decoding circuitry.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A, 1B and 1C, referred to above, are diagrams showing the data
formats of records produced by three data compression methods.
FIG. 2 is a block diagram of video signal processing circuitry which
includes an embodiment of the present invention.
FIG. 3A is a block diagram showing circuitry, embodying the present
invention, suitable for use as the microcode RAM and sequencing circuitry
of the video signal processing circuitry shown in FIG. 2.
FIG. 3B is a timing diagram showing signal amplitudes as a function of time
for several signals that are useful in explaining the operation of the
circuitry shown in FIG. 3A.
FIG. 3C is a diagram showing the data format of a microcode control word
for the microcode RAM and sequencer used in the circuitry shown in FIG. 2.
FIG. 4A is a block diagram of the arithmetic and logic unit used with the
embodiment of the invention shown in FIG. 2.
FIG. 4B is a partial block diagram of the arithmetic and logic circuitry
shown in FIG. 4A.
FIG. 5 is a block diagram of the data path circuitry used in the embodiment
of the invention shown in FIG. 2.
FIG. 6 is a block diagram of the data RAM circuitry used with the
embodiment of the invention shown in FIG. 2.
FIGS. 7A, 7B, 7C, 7D and 7E are timing diagrams that are useful for
explaining the operation of the data RAM circuitry shown in FIG. 6.
FIG. 8A is a block diagram of the pixel interpolator used with the
embodiment of the invention shown in FIG. 2.
FIG. 8B is a block diagram of the multiplier used in the pixel interpolator
shown in FIG. 8A.
FIGS. 9A, 9B, 9C, 9D, 9E and 9F are diagrams that are useful to explain the
operation of the pixel interpolator shown in FIG. 8.
FIG. 10A is a block diagram of a statistical decoder suitable for use in
the video signal processing circuitry shown in FIG. 2.
FIG. 10B is a timing diagram that is useful for understanding the operation
of the circuitry shown in FIG. 10A.
FIG. 11A is a block diagram of input FIFO circuitry suitable for use in the
video signal processing circuitry shown in FIG. 2.
FIG. 11B is a timing diagram that is useful for understanding the operation
of the circuitry shown in FIG. 11A.
FIG. 12A is a block diagram of output FIFO circuitry suitable for use in
the video signal processing circuitry shown in FIG. 2.
FIG. 12B is a timing diagram that is useful for understanding the operation
of the circuitry shown in FIG. 12A.
FIGS. 13A and 13B are a block diagram of the VRAM control unit used with
the embodiment of the invention shown in FIG. 2.
FIG. 13C is a timing diagram that is useful for understanding the operation
of the circuitry shown in FIG. 13A.
FIG. 14 is a memory map diagram showing how the compressed data is stored
in the video random access memory of FIG. 2.
FIGS. 15 through 23 are control flow diagrams and other diagrams useful for
explaining the operation of the circuitry shown in FIGS. 2-13.
DETAILED DESCRIPTION
In the drawings, broad arrows represent busses for conveying multiple-bit
parallel digital signals and line arrows represent connections for
conveying analog signals or single bit digital signals. Depending on the
processing speed of the devices, compensating delays may be required in
certain of the signal paths. One skilled in the art of digital signal
processing circuit design would know where such delays would be needed in
a particular system.
FIG. 2 is a block diagram showing the video signal processing circuitry 210
and associated peripheral circuitry. In the present embodiment of the
invention, the circuitry 210 is implemented as a single integrated
circuit. The video signal processing system is described below briefly,
with reference to FIG. 2 only, and then in greater detail with reference
to FIGS. 2-13. A third section of this application refers to FIGS. 14-23
and describes how the various components of the system operate in parallel
to convert compressed video data in formats such as those shown in FIGS.
1A, 1B and 1C into pixel values.
In FIG. 2, a source of compressed video signal 212 provides video signal
data which has been compressed using one or more of the video signal
compression techniques set forth above and which includes data that has
been statistically encoded. In this embodiment of the invention, the data
provided by the source 212 is applied to a video random access memory
(VRAM) 216 under control of a VRAM control unit 238 that is internal to
the video signal processor 210. The source 212 used in this embodiment of
the invention is a compact disk read only memory (CD ROM). It continually
provides the compressed data to the VRAM 216 in blocks of, for example, 32
bits each. The VRAM control unit 238 coordinates data access requests to
the VRAM 216 from the source 212 and the circuitry 210 to ensure that all
of the data provided by source 212 is written into the VRAM 216.
The VRAM 216 used in this embodiment of the invention is composed of 128 of
the .mu.PD41264 64K by 4-bit dual port random access memory integrated
circuits manufactured by NEC Electronics Inc. The memory integrated
circuits are arranged in a matrix having 16 rows and eight columns. In
this configuration, the VRAM 216 provides 4 megabytes (MB) of storage,
arranged as 1,048,576 words of 32 bits each.
A display processor 218 accesses the VRAM 216 via a serial output port to
develop the active video portion of a displayed video signal. The video
signal processing circuitry 210 and source of compressed video signals 212
access the data cells of the VRAM 216 via the standard input-output bus.
All access to the VRAM 216 by the video signal processor 210 and display
processor 218 is controlled by the VRAM control unit 238 of the circuitry
210.
Data held in the VRAM 216 is provided to the processing circuitry 210 by
the statistical decoder 230 and by the input first-in-first-out (FIFO)
circuits 232 and 234. Data is provided by the circuitry 210 to the VRAM
216 via the output FIFO circuitry 236. The data values provided by the
statistical decoder 230 and the input FIFO's 232 and 234 are applied to
data path circuitry 242, an arithmetic and logic unit (ALU) 244 and a data
RAM 228 via a bidirectional data bus B BUS. The bus B BUS is also used to
provide address values to the VRAM control unit 238. A second
bidirectional bus, A BUS, is included in the circuitry 210 to provide an
alternate means for passing data values among the data path circuitry 242,
ALU 244 and data RAM 228, and to provide data to, and accept data from a
pixel interpolator 246. In addition to the coupling set forth above, the
data bus A BUS is connected to a microcode RAM and sequencer 226 and may
be coupled to a microprocessor 224.
In general terms, the circuitry shown in FIG. 2 operates as follows.
Compressed video signals, provided by the source 212, are written into the
VRAM 216. These compressed video signals are accessed via the statistical
decoder 230 and the input FIFO's 232 and 234 under control of the
sequencing circuitry 226. The values provided by the decoder 230 and the
FIFO's 232 and 234 are applied to the data path 242, ALU 244 and pixel
interpolator 246, also under control of the sequencing circuitry 226, to
expand the compressed video signals and generate pixel values that
describe the encoded image. The generated pixel values are written into
the VRAM 216 via the output FIFO 236 as a matrix having, for example, 240
rows and 256 columns. These correspond to 240 lines of a video signal
where each line has 256 pixel values. This matrix is hereinafter referred
to as a bit-map. The bit-map is read from the VRAM 216 by the display
processor 218 to reproduce an image. The display processor 218 used with
this embodiment of the invention converts the pixel values in the bit-map
into a video signal and adds the required horizontal and vertical
synchronization signals to enable the image to be reproduced on a raster
scan display device. To coordinate transfers of data from the VRAM 216 to
the display processor 218, a horizontal line synchronizing signal, HS, and
a vertical field synchronizing signal, VS, are provided to the processors
210 and 218 by respective signal sources 220 and 222. In a preferred
embodiment of the invention, these signals may be generated by the display
processor 218.
In the present embodiment of the invention, a source of clock signal 225
provides a 25 MHz clock signal, CLK, to the microcode RAM and sequencer
circuitry 226. The circuitry 226 generates signals CK and CK', each having
a frequency of 12.5 MHz, a signal CK.sub.A, having substantially the same
frequency and phase as the signal CK, and a signal CK.sub.B which is
substantially antiphasal to the signal CK. The clock signals CLK, CK.sub.A
and CK.sub.B are applied to the data RAM 228. The signals CK.sub.A and
CK.sub.B are applied to the data path 242, the ALU 244 and the pixel
interpolator 246. The signal CK is applied to the statistical decoder 230,
the input FIFO's 232 and 234, and to the output FIFO 236. The signal CK'
is applied to the VRAM control unit 238.
To simplify the explanation of the circuitry shown in FIG. 2, it is assumed
that the source of compressed video signals provides only encoded
luminance signals and, thus, that the circuitry 210 builds only one
bit-map, the luminance bit-map. In a practical system, additional bit-maps
for color information signals, for example the I and Q color-difference
signals, would be generated as well.
As set forth above, the central control element in the video signal
processing circuitry 210 is the microcode RAM and sequencer circuitry 226.
FIG. 3A is block diagram showing circuitry suitable for use as the
microcode RAM and sequencer 226. The microcode RAM 310 is a conventional
random access memory arranged as 128 words, each of which has 96 bits. In
normal operation, the microcode RAM 310 provides a 96-bit word, addressed
by the seven MSB's of an address value held in an address register 322, to
the input port of a register 312. The register 312 is conditioned by a
signal LD provided by control circuitry 308 to load the value applied to
its input port. Each of the 96-bit values provided by the microcode RAM
310 contains two 48-bit microcode control words or instructions. One of
these instructions, in the 48 MSB positions of the register 312, is
applied to one input port of a multiplexer 314 and the other instruction,
in the 48 LSB positions of the register 312, is applied to a second input
port of the multiplexer 314. The multiplexer 314 is conditioned by a
single-bit signal provided by a flip-flop 318 to pass one of the 48-bit
instructions to the input port of the instruction register 316. The
instruction register 316 loads the microcode control word applied to its
input port in response to a signal LI provided by the control circuitry
308.
The individual bits of the instruction register 316 are connected, via a
bus MCW, to control input terminals of each of the components of the video
signal processing circuitry 210. As the microcode control words provided
by the microcode RAM 310 sequence through the instruction register 316,
the individual components of the circuitry 210 are conditioned to perform
operations which, in concert, convert the compressed video data into
bit-map pixel data. The function of each bit of the microcode control word
is described below in reference to FIG. 3C.
The clock signals CK and CK' used by the video signal processor 210 are
generated by circuitry included in the microcode RAM and sequencer 226.
The 25 MHz clock signal CLK provided by the source 225 is applied to
frequency dividing circuitry 304 which divides the frequency of the signal
CLK by two to produce the 12.5 MHz clock signal CK'. The signal CLK is
further applied to one input terminal of an AND gate 306, the other input
terminal of which is coupled to an inverter 302 to receive an inverted
version of a signal HALT, provided by the microprocessor 224. The output
signal of the AND gate 306 is applied to frequency dividing circuitry 307
which divides its frequency by two to produce the 12.5 MHz clock signal
CK. When the signal HALT has a logic zero value, the signal CK is a 12.5
MHz square-wave oscillatory signal. When the signal HALT changes to a
logic one, however, the state of the signal CK is frozen at logic-one or
logic-zero, its state when the change in the signal HALT occurred.
As set forth below, the eight LSB's of the microcode control word define
the NEXT ADDRESS field. In any microcode control word, this field contains
the address, in the microcode RAM 310, of the next microcode control word
to be loaded into the instruction register 316. The value held in the NEXT
ADDRESS field is applied to the address register 322 via a multiplexer
320. The LSB of the NEXT ADDRESS value is applied to the input terminal D
of the flip-flop 318. The address register 322 and the flip-flop 318 are
conditioned, by the signal CK, to load the values applied to their
respective input ports.
A signal CD, provided by the data path circuitry 242, as set forth below,
is coupled to the reset input terminal, R, of the flip-flop 318. The value
of the signal CD is controlled by the condition code select (COND CODE
SEL) field (described below) of the microcode control word. This signal is
used in the microcode RAM and sequencing circuitry 226 to conditionally
change the sequence of microcode control words applied to the instruction
register 316. The signal CD represents a condition that occurred earlier
in the signal processing, for example, that the output value of the ALU
244 is zero. When the selected condition is true the output signal, Q,
provided by the flip-flop 318 becomes a logic-zero. This value conditions
the multiplexer 314 to pass the value held in the 48 LSB positions of the
register 312 to the instruction register 316.
To understand how this circuitry may be used to conditionally change the
control flow of the microcode RAM and sequencer circuitry 226, in other
words to perform a conditional branch operation, assume that a microcode
control word A has a non-zero value in its COND CODE SEL field and a value
of 81 in its NEXT ADDRESS field. When this microcode control word is
loaded into the instruction register 316, the eight-bit value in the NEXT
ADDRESS field is applied to the address register 322 and the microcode
control words at addresses 80 and 81 in the microcode RAM 310 are loaded
into the register 312. If the value of the condition signal, CD, is
logic-zero, the microcode control word occupying the 48 MSB positions
(address 81) of the register 312 is the next to be used. Otherwise, the
microcode control word occupying the 48 LSB positions (address 80) of the
register 213 is next. Each of these instructions has a distinct NEXT
ADDRESS field and, so, each defines a different sequence of microcode
control words, that is to say, a different functioning of the video signal
processor 210. Since the microcode RAM 310 provides the next instruction
for both possible values of the condition code, no time is lost in
fetching the next microcode control word once the value of the condition
is determined.
The microcode RAM and sequencer circuitry 226 is able to load microcode
control words, supplied via the bus A BUS, into the microcode RAM 310.
Three 16-bit values, each representing one-third of a microcode control
word, are successively applied to three registers 324. The first 16-bit
value is stored into the register MRO, the second, into the register MR1
and the third, into the register MR2. Next, an address value, which may
also be provided by the VRAM 216 via the input FIFO 232 and data RAM 228,
is applied to the address register 322. The LSB of this address value, the
signal DXC, conditions a demultiplexer 326 to apply the 48-bit value
provided by the three registers MR0, MR1 and MR2 either to the 48 MSB
positions or to 48LSB positions of the I/O bus for the microcode RAM 310.
At the same time, a write enable signal, WE, is pulsed to condition the
RAM 310 to store the 48-bit value into the addressed memory cell.
The microcode control words written into the microcode RAM 310 by these
operations are provided from the VRAM 216 via, for example, the input FIFO
232 and data RAM circuitry 228. This ability to load microcode
instructions from the VRAM 216 allows the source of compressed video 212
to provide both compressed data and the instructions needed to decompress
it to the video signal processor 210. Initially, a bootstrap program may
be loaded into the microcode RAM 310 by the microprocessor 224 which may
take control of the processor 210 as set forth below. Responsive to the
instructions in this bootstrap program, the microcode RAM and sequencer
circuitry 226 loads the instructions from the VRAM 216 which enable the
processor 210 to decode the compressed video data.
FIG. 3B is a timing diagram which illustrates the operation of the
microcode RAM and sequencing circuitry 226 when a microcode control word,
MC, is stored into the microcode RAM 310. In the timing diagram, the
symbols T.sub.0 through T.sub.5 represent six microcode instruction
cycles. Each instruction cycle begins and ends on a positive-going
transition of the signal CK.sub.A.
During the instruction cycle T.sub.0, the microcode control word held in
the instruction register 316 has a value (e.g. 8) in its A DST field
indicating that the 16-bit value conveyed by the bus A BUS is to be stored
into the register MRO. In this instruction cycle, the value MCO, the 16
LSB's of the microcode control word MC, is gated onto the bus A BUS by,
for example, the data RAM circuitry 228. During the instruction cycle
T.sub.0, the register MRO is conditioned by the value of the signal A DST
to store the 16-bit value MCO provided by the bus A BUS. The store
operation occurs coincident with the negative-going transition of the
signal CK.sub.A, at the midpoint of the instruction cycle T.sub.0. At
substantially the same time that the value MCO is stored into the register
MRO, the value in the NEXT ADDRESS field of the microcode control word in
the instruction register 316 is stored into the address register 322 and
the LSB of this address value is stored into the flip-flop 318. The value
stored in the address register 322 conditions the microcode RAM 310 to
apply a 96-bit value, which includes the next instruction, to the register
312. This 96-bit value is loaded into the register 312 coincident with the
negative-going transition of the signal LD which occurs slightly after the
midpoint of the instruction cycle T.sub.0. Responsive to the single-bit
value held in the flip-flop 318, the addressed 48-bit microcode control
word is applied to the input port of the instruction register 316. This
microcode control word is loaded into the instruction register 316
coincident with the negative-going edge of the signal LI, occurring at the
end of the instruction cycle T.sub.0. During the instruction cycle
T.sub.1, the newly loaded microcode control word conditions the register
MR1 to load a value MC1, representing the middle 16-bits of the microcode
control word MC. In the same manner, a microcode control word loaded into
the instruction register 316 at the end of the instruction cycle T.sub.1,
conditions the register MR2 to load the 16 MSB's of the microcode control
word MC during the instruction cycle T.sub.2.
The microcode control word loaded into the instruction register 316 at the
end of the instruction cycle T.sub.2 controls the transfer of the
microcode control word MC from the registers 324 to the microcode RAM 310.
The address used to store the microcode control word MC is provided via
the bus A BUS. At the start of the instruction cycle T.sub.3, the A DST
field of the microcode control word in the instruction register 316 has a
value of 11, indicating that the 16-bit value provided by the bus A BUS is
to be loaded into the address register 322. Responsive to this value in
the A DST field, the control circuitry 308 applies a logic-one value, as
the signal MXC to the multiplexer 320 for approximately one cycle of the
signal CK. This signal conditions the multiplexer 320 to apply the 8 LSB's
of the value provided by the bus A BUS to the input port of the address
register 322. This address value is loaded into the register 322
coincident with the first negative-going transition of the signal CK in
the instruction cycle T.sub.3. The LSB of the value held in the address
register 322, the signal DXC, is applied to a control input terminal of a
demultiplexer 326. The demultiplexer 326 is conditioned by the signal DXC
having values of logic-one or logic-zero to gate the 48-bit value provided
by the registers 324 onto the respective 48 MSB positions or 48 LSB
positions of the I/O bus.
The signal DXC is also used to generate a separate write enable signal, via
AND gates 311 and 313, for each half of the microcode RAM 310. As set
forth above, the microcode RAM 310 is configured as 128 words where each
word has 96 bits. This memory is divided into two halves. The left half
contains the 48 MSB's of the 128 words and the right half contains the 48
LSB's of the 128 words. The signal DXC is combined, in the AND gate 313,
with the write enable signal WE, provided by the control circuitry 308 to
generate the write enable signal for the left half of the microcode RAM
310. The signal DXC is inverted and then logically ANDed with the signal
WE by the gate 311 to produce the write enable signal for the right half
of the microcode RAM 310.
In the present example, the signal DXC has a value of logic one for
approximately one period of the signal CK at the start of the instruction
cycle T.sub.3. Consequently, the microcode control word MC is written into
the 48 MSB positions of the cell in the microcode RAM 310 that has the
address value represented by the seven MSB's value held in the address
register 322. The microcode control word is written into the microcode RAM
310 coincident with the signal WE shown in FIG. 3B.
Since the instruction cycle T.sub.3 performs a memory write operation, the
next microcode control word is not loaded into the instruction register
316 during the first period of the signal CK. This operation occurs during
the second period of the signal CK in the instruction cycle T.sub.3.
Coincident with the second positive-going transition of the signal CK
during the instruction cycle T.sub.3, the value of the signal MXC is
changed to logic zero, and an instruction fetch operation proceeds as set
forth in reference to the instruction cycle T.sub.0. The microcode RAM and
sequencing circuitry 226 operates in the manner described in reference to
the instruction interval T.sub.0 for the instruction cycles T.sub.4 and
T.sub.5.
In the example set forth in FIG. 3B, the signals LD and LI are inhibited
during the first half of the instruction cycle T.sub.3 to prevent
erroneous microcode control words from being loaded into the registers 312
and 316. In addition, the signals CK.sub.A and CK.sub.B are frozen by the
control circuitry 308 during the second half of the instruction cycle
T.sub.3 to put the video signal processing circuitry in a paused state.
This is done to maintain synchronous operation among the ALU 244, data RAM
228 and pixel interpolator 246. Since the clock signals CK.sub.A and
CK.sub.B are disabled during the second half of the instruction cycle
T.sub.3, the internal states of the ALU 244, data RAM 228 and pixel
interpolator 246 do not change in this time period.
In the present embodiment of the invention, a data read operation and a
data write operation for the microcode RAM 310 occur during separate
periods of the signal CK. Alternatively, the microcode RAM and sequencing
circuitry 226 may be designed to perform both operations in a single
period of the signal CK.
The control circuitry 308 is also responsive to a signal PAUSE provided by
the pause logic 240 to freeze the clock signals CK.sub.A and CK.sub.B. In
addition, the control circuitry 308 is responsive to a signal, HALT,
provided by the microprocessor 224 to inhibit the signal CK, effectively
freezing the internal state of the entire video signal processor 210
except for the VRAM control unit 238.
Using the signal HALT, the microprocessor 224 may effectively assume the
control functions of the video signal processor 210. The signal HALT is
applied to the instruction register 316 to condition that register to
accept data from the bus MCW, provided by the microprocessor 224 via the
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