A programmable logic integrated circuit device utilizes volatile memory elements such as SRAM for retaining configuration information. A circuit is provided as part of the device for detecting loss of power on a supply input pin. When power loss is detected, a backup voltage supply, packaged with the programmable logic device as a unit, is connected thereto. The backup power is used to supply voltage only to those portions of the device having volatile memory elements containing configuration information. Backup power is not provided to input and output buffers of the device, thereby preventing excess loads being placed upon the backup device because of events which may occur external to the programmable logic device.

A large scale integrated circuit device includes a plurality of internal devices, an address decoding circuit, a bus control circuit, a first tristate buffer, and an output buffer. The internal devices are connected to an internal data bus and selectively perform data input/output operations. The address decoding circuit decodes an address signal from an address bus of a system to deliver an internal device select signal to one of the internal devices and an internal device select indication signal indicating that one of the internal devices is selected. The bus control circuit delivers an output control signal and an input control signal upon receiving the internal device select indication signal and one of a data write signal and a data read signal. The first tristate buffer controls data input to the internal data bus in accordance with the input control signal. The output buffer controls data output from the internal data bus in accordance with the output control signal.

The present invention includes an input buffer circuit (10) having sleep mode and bus hold capability. An input section (11) of the buffer circuit is operated from an operating voltage which is lower than a supply voltage of the buffer circuit thereby minimizing the static power dissipation. Sleep mode circuitry (15, 36, 38) is included for effectively disconnecting an input signal from the rest of the buffer circuit thereby minimizing dynamic power dissipation. Bus hold circuitry (40) is included for holding the logic state appearing at an output of the input buffer circuit when the input signal is removed thereby further reducing the static power dissipation.

A power reduction circuit for selectively providing power to circuitry associated with and coupled to the power reduction circuit, which includes two transistors having current paths coupled in parallel and a nonvolatile programmable storage device having a current path coupled in series with the current paths of the two transistors. A control transistor which is also part of the power reduction circuit includes a current path between a power supply and the circuitry associated with and coupled to the power reduction circuit to selectively provide power to the associated circuitry. The control transistor has a control gate electrode which is coupled between the current path of the nonvolatile programmable storage device and the current paths of the two transistors. The state of the storage device controls the state of the control gate electrode of the control transistor and accordingly controls whether the power is supplied to the associated circuitry. The power reduction circuitry consumes essentially zero power during normal operation because either the programmable storage device or the two transistors coupled in series with the current path of this storage device are off, thereby drawing essentially zero power.

Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.