 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic musical instrument, and more
particularly to an electronic musical instrument which can store key
operation data corresponding to a musical performance played by using a
keyboard and which can also transfer the stored key operation data to an
external memory.
2. Prior Art
Conventionally, a recent electronic technology develops an electronic
musical instrument which can store performance data corresponding to a
keyboard performance in an internal memory so that an automatic
performance will be played by use of the stored performance data. Such
electronic musical instrument can transfer the performance data stored in
the internal memory to an external memory as disclosed in an automatic
performance apparatus of Japanese Patent Laid-Open No. 59-139093.
If a storage capacity of the external memory is set smaller than a quantity
of the performance data stored in the internal memory (hereinafter, simply
referred to as "an internal data quantity") in the conventional electronic
musical instrument capable of executing a data transfer to the external
memory, the stored performance data are inhibited from being transferred
to the external memory, i.e., the data transfer is not executed at all. In
this case, the conventional electronic musical instrument wastes the whole
musical performance which is played in order to transfer the performance
data to the external memory.
In the above-mentioned case, by lighting up a light emitting diode (LED) or
by displaying a predetermined message on a liquid crystal display device
or the like, a player can be informed that the data transfer is inhibited
from being executed.
By using the above-mentioned LED or the liquid crystal display device, the
player can know that the data transfer is inhibited from being executed,
but the player can not know how much is the storage capacity of the
external memory short of a desirable storage capacity. Therefore, it is
impossible for the player to know how much the performance quantity (or
the data quantity) can be transferred to the external memory. In other
words, the conventional electronic musical instrument cannot give the
player the information about how much of the performance quantity can be
transferred to the external memory.
SUMMARY OF THE INVENTION
It is accordingly a primary object of the present invention to provide an
electronic musical instrument which does not waste the whole musical
performance for the external memory when the storage capacity of the
external memory is smaller than the internal data quantity and which can
transfer the minimum performance data within the allowable storage
capacity of the external memory.
It is another object of the present invention to provide an electronic
musical instrument which can inform the player of a data quantity of the
performance data to be overflowed in the external memory when the storage
capacity of the external memory is smaller than the internal data
quantity.
In a first aspect of the invention, there is provided an electronic musical
instrument comprising: (a) input keys; (b) internal memory means; (c)
writing control means for writing operation data corresponding to an
operation of the input keys into the internal memory means; (d) musical
tone signal generating means for generating a musical tone signal
corresponding to the operation data; (e) external memory means which can
be freely attached to and detached from a main body of the electronic
musical instrument; and (f) transfer control means for comparing operation
data quantity of the operation data stored in the internal memory means
with a storage capacity of the external memory means when the operation
data stored in the internal memory means are to be transferred to the
external memory means, all of the operation data being transferred to the
external memory means when the storage capacity is larger than the
operation data quantity, a certain part of the operation data being
transferred to the external memory means when the storage capacity is
smaller than the operation data quantity.
In a second aspect of the invention, there is provided an electronic
musical instrument comprising: (a) input keys; (b) internal memory means;
(c) writing control means for writing operation data corresponding to an
operation of the input keys into the internal memory means; (d) musical
tone signal generating means for generating a musical tone signal
corresponding to the operation data; (e) external memory means which can
be freely attached to and detached from a main body of the electronic
musical instrument; and (f) alarm means for comparing operation data
quantity of the operation data stored in the internal memory means with a
storage capacity of the external memory means when the operation data
stored in the internal memory means are to be transferred to the external
memory means, the alarm means informing a player of overflow data quantity
of the operation data to be overflowed from the external memory means when
the storage capacity is smaller than the operation data quantity.
In a third aspect of the invention, there is provided an automatic
performance data recording and reproducing apparatus for an electronic
musical instrument comprising: (a) first memory means for storing
performance data; (b) second memory means for recording the performance
data transferred from the first memory means; and (c) transfer means for
transferring the performance data to the second memory means from the
first memory means based on data quantity of the performance data and
storage capacity of the second memory means in a recording mode, whereas
the performance data are reproduced from the second memory means so that
musical tones corresponding to the reproduced performance data are to be
generated in a reproducing mode.
BRIEF DESCRIPTION OF THE DRAWINGS
Further objects and advantages of the present invention will be apparent
from the following description, reference being had to the accompanying
drawings wherein a preferred embodiment of the present invention is
clearly shown.
In the drawings:
FIG. 1 is a block diagram showing an electric constitution of an embodiment
of the present invention;
FIG. 2 is a front view showing a panel face of the embodiment of FIG. 1;
FIG. 3 shows a memory map of a performance data memory shown in FIG. 1;
FIG. 4 is a flowchart showing a switch scanning process;
FIG. 5 is a flowchart showing a check processing routine;
FIG. 6 is a flowchart showing a RAM pack capacity checking process;
FIGS. 7A and 7B show a flowchart of a data transferring process;
FIG. 8 is a flowchart showing another check processing routine employed in
a first modified example of the present embodiment;
FIG. 9 is a flowchart showing still another check processing routine
employed in a second modified example of the present embodiment;
FIG. 10 shows a memory map of an end address data memory employed in the
second modified example of the present embodiment;
FIG. 11 shows another memory map of the performance data memory employed in
a third modified example of the present embodiment; and
FIGS. 12A and 12B show a flowchart of a save process employed in the third
modified example of the present embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[I] Electric Constitution of an Embodiment of the Present Invention
Referring now to the drawings, wherein like reference characters designate
like or corresponding parts throughout the several views, FIG. 1 is a
block diagram showing an electric constitution of an embodiment of the
present invention. In FIG. 1, 1 designates a central processing unit (CPU)
for controlling several sections of the electronic musical instrument
shown in FIG. 1, and this CPU 1 operates based on programs stored in a
program memory 2. In addition, 3 designates a working area capable of
storing several kinds of data in accordance with the process of the CPU 1,
and several registers will be set in this working area 3 as described
later.
A key switch section 5 consists of upper keys UK, lower keys LK, pedal keys
PK and solo keys SK. On/off data of each key within the key switch section
5 are supplied to the CPU 1 via a key switch interface 6. The solo keys SK
are used in a solo performance. More specifically, each of the solo keys
SK selectively enables one musical tone effective in accordance with a
process of a later arrival priority or a maximum tone pitch priority.
Normally, the solo keys SK are arranged on an upper stage position of the
upper keys UK.
In FIG. 1, 4 designates a display section consisting of the liquid crystal
display device and its drive circuit. This display section 4 displays
several kinds of messages under the control of the CPU 1.
A panel switch section 8 consists of several switches provided on an
operation panel (not shown), i.e., switches for selecting tone colors,
tone effects and rhythms; switches for controlling the performance data
and other switches. The on/off data (or the on/off information) of each
switch within the panel switch section 8 are supplied to the CPU 1 via a
panel switch interface 9.
The switches shown in FIG. 2 are the above-mentioned switches for
controlling the performance data in the panel switch section 8, and
detailed description thereof will be given below.
(a) SWITCH FMP-REC
When the switch FMP-REC is depressed, the CPU 1 stores the performance data
corresponding to the musical performance played by the player in a
performance data memory 10. Such performance data consist of the tone
pitch and on/off data of each key within the key switch section 5 and
other on/off data (or registration data) of each of the tone color
selecting switches and the rhythm selecting switches within the panel
switch section 8. If a switch U is depressed while the switch FMP-REC is
turned on, the performance data memory 10 is supplied with the performance
data other than the on/off data of the upper keys UK. In other words, if
the switch U is depressed while the switch FMP-REC is turned on, the
on/off data of the upper keys UK are excluded from the performance data
supplied to the performance data memory 10. Similarly, if each of a switch
L, a switch P and a switch S is depressed, each on/off data of the lower
keys LK, the pedal keys PK and the solo keys SK are excluded from the
performance data respectively. Further, if a switch R is depressed, the
registration data are excluded from the performance data. Thus, the player
can select a data kind of the performance data to be stored in the
performance data memory 10.
FIG. 3 shows a data format (or a memory map) of the performance data memory
10. In FIG. 3, FMP-Mu designates an upper key area for storing key data of
the upper keys UK. This key data can be defined as data composed of the
tone pitch data and the on/off data. In addition, FMP-Ml designates a
lower key area for storing key data of the lower keys LK, FMP-Mp
designates a pedal key area for storing key data of the pedal keys PK,
FMP-Ms designates a solo key area for storing key data of the solo keys
SK, and FMP-Mr designates a registration data area for storing the
registration data. In this case, the upper key area FMP-Mu has a storage
capacity of 8 kilo-byte, and each of other areas has a storage capacity of
6 kilo-byte. Hence, the total storage capacity of the performance data
memory 10 is 32 kilo-byte.
The CPU 1 allows the access to an address designated by each of pointers
Pu, Pl, Pp, Ps and Pr in each of the upper key area FMP-Mu, the lower key
area FMP-Ml, the pedal key area FMP-Mp, the solo key area FMP-Ms and the
registration data area FMP-Mr. As shown in FIG. 3, the start addresses of
these areas are designated by "0", "n1", "n2", "n3" and "n4" respectively.
(b) SWITCH FMP-PLY
The switch FMP-PLY is operated so as to execute the automatic performance
based on the performance data stored in the performance data memory 10.
When the switch FMP-PLY is depressed, the CPU 1 sequentially reads out the
performance data from the performance data memory 10 so as to supply such
read performance data to a musical tone generating circuit 12 and a rhythm
tone generating circuit 13. The musical tone generating circuit 12
generates musical tones corresponding to the on/off data of each key (such
as each of the upper keys UK, the lower keys LK etc.) and other on/off
data of the tone color selecting switch and the like. On the other hand,
the rhythm tone generating circuit 13 generates a rhythm accompaniment in
accordance with a rhythm designated by a rhythm selecting switch and a
tempo designated by a tempo designating volume and the like. The output
signals of the musical tone generating circuit 12 and the rhythm tone
generating circuit 13 are amplified by an amplifier 14 and then applied to
a speaker 15.
(c) SWITCH SAVE
The switch SAVE is operated so as to transfer the performance data stored
in the performance data memory 10 to an external RAM 20 (hereinafter,
referred to as a RAM pack 20). When the switch SAVE is depressed, the CPU
1 executes a data transfer in according to the processes which will be
described later. This RAM pack 20 can be freely attached to and detach
from a main body of the electronic musical instrument, this RAM pack 20
consists of a non-volatile random access memory (RAM) using a back-up
battery. The present embodiment can employ two kinds of RAM packs, i.e.,
the RAM packs of 8 kilo-byte and 32 kilo-byte.
(d) SWITCH LOAD
The switch LOAD is operated so as to write the performance data stored in
the RAM pack 20 into the performance data memory 10. When the switch LOAD
is depressed, the CPU 1 sequentially transfer the performance data stored
in the RAM pack 20 to the performance data memory 10.
In addition, a LED 7 is arranged in the vicinity of each of the switches in
the panel switch section 8 shown in FIG. 2. Each LED 7 is lighted up while
each switch is turned on.
[II] Operations of an Embodiment of the Present Invention
Next, description will be given with respect to the operations of the
present embodiment.
(A) SWITCH SCANNING PROCESS
As shown in FIG. 4, the CPU 1 starts operation thereof in a step SP1, then
the CPU 1 initializes the memories and registers in a step SP2.
Subsequently, the CPU 1 checks whether the switching FMP-REC, FMP-PLY,
FMP-SAVE and FMP-LOAD have been sequentially depressed or not in steps SP3
to SP6. In none of these switches have been depressed, other processes are
executed in a step SP7, and the present process returns to the step SP3.
Thereafter, processes in a loop consisting of the steps SP3 to SP7 are
repeatedly executed until one of these switches is depressed.
Once the switch FMP-REC is depressed during an execution of the above loop,
the CPU 1 lights up the LED 7 provided near the switch FMP-REC, and then
the CPU 1 executes a FMP-REC process in a routine LU1 wherein the
performance data corresponding to the performance actually played by the
player are stored in the performance data memory 10.
Similarly, the CPU 1 lights up the LED 7 provided near each of the switches
FMP-PLY, FMP-SAVE and FMP-LOAD when each of these switches is depressed.
Thereafter, the CPU 1 executes each of a FMP-PLY process in a routine LU2,
a SAVE process in a routine LU3 and a LOAD process in a routine LU4.
Next, detailed description will be given with respect to each of these
routines LU1 to LU4.
(B) FMP-REC PROCESS ROUTINE LU1
According to timing data generated by a timer circuit (not shown) or a
timer function for executing a software process, one musical bar is
divided into n parts (where n denotes as an integral number) including a
head part having a number "0" and a last part having a number "n-1". If
the number n equals to "192", the timing data are generated based on the
head part number "0" and the last part number "191".
When the key is depressed or released, a variation of the key operation is
occurred. Hereinafter, such variation will be referred to as an "event".
In this case, the timing data of the key are stored in the storing area
thereof (such as the areas FMP-Mu, FMP-Ml and the like) when the above
event is occurred on such key. Further, the value of the pointer is
increased by one so that the key data of such key are written in the area
thereof. For example, if the event is occurred in one of the upper keys
UK, the timing data are written at address of the upper key area FMP-Mu
designated by the pointer Pu. Subsequently, the value of the pointer Pu is
increased by one, and the key data (consisting of the tone pitch data and
the on/off data) are written at an address next to the above-mentioned
address.
The above-mentioned process is executed on each of the keys and each
registration data, and the performance data are stored in the performance
data memory 10. As shown in FIG. 3, data END representative of the end of
the performance data are added to the performance data stored in each
storing area.
Incidentally, vertical lines each indicating the end of each part of the
musical bar is stored as a part of the performance data.
(C) FMP-PLY PROCESS ROUTINE LU2
This routine LU2 is executed for reading out the performance data from the
performance data memory 10 so as to generate the musical tones
corresponding to the read performance data. The performance data are
sequentially read out from the start address of each area within the
performance data memory 10. More specifically, this routine LU2 is
executed in the manner as described below.
First, the timing data are read from the address designated by each pointer
(such as the pointers Pu, Pl, . . . ), and the read timing data are
fetched to a timing register set in the working area 3. Next, the value of
such pointer is increased by one, and the key data are read out and then
fetched to a key data register set in the working area 3. At a time when
the count value of the timer counter for counting a tempo clock coincides
with the value of the timing data stored in the timing register, the key
data are read from the key data register and then the read key data are
supplied to the musical tone generating circuit 12 wherein the musical
tone corresponding to the supplied key data is generated.
After the value of the pointer is increased by one, next timing data and
key data are read out and then fetched to the timing register and the key
data register respectively. Such key data are supplied to the musical tone
generating circuit 12 at a time when the count value of the timer counter
becomes equal to the value of the timing register. Thereafter, each pair
of the timing data and the key data are read from the performance data
memory 10 in the same manner as described above. At a time when the value
of the timer counter becomes equal to the value of the timing register, a
musical tone generating process is executed.
(D) SAVE PROCESS ROUTINE LU3
This SAVE process routine LU3 consists of a check process LU3a and a data
transfer process LU3b. First, description will be given with respect to
the check process LU3a.
(1) CHECK PROCESS ROUTINE LU3a
FIG. 5 is a flowchart of the check process routine LU3a. When the switch
SAVE is operated, the CPU 1 lights up the LED 7 near the switch SAVE.
Thereafter, the CPU 1 initializes the pointers Pu, Pl, Pp, Ps and Pr
respectively. In other words, the values "0", "n1", "n2", "n3" and "n4"
are respectively set to the pointers Pu, Pl, Pp, Ps and Pr. In addition,
the CPU 1 clears a register DSP and a flag OVER both set in the working
area 3 in a step SP10. Next, the present process advances to a step SP11
wherein the CPU 1 checks the storage capacity of the RAM pack 20 connected
to the main body. At a first stage of such capacity checking process shown
in FIG. 6, the CPU 1 judges whether the RAM pack 20 is connected to the
main body in a good manner or not in a step SP12. Such judgment is
executed by examining the terminal voltage of the RAM pack 20. If an
imperfect connection is occurred, the present process advances to a next
step SP13 wherein the CPU 1 controls the display section 4 (shown in FIG.
1) so that a message representing the imperfect connection of the RAM pack
20 will be displayed. Thereafter, the present process returns to the
switch scanning process shown in FIG. 4 again. On the other hand, if the
RAM pack 20 is connected to the main body in a normal manner, the present
process advances to a step SP14 wherein the CPU 1 discriminates whether
the storage capacity of the RAM pack 20 is represented by S1 or S2. In the
present embodiment, S1 is set equal to 8 kilo-bytes, and S2 is set equal
to 32 kilo-bytes. Such storage capacity is discriminated by examining the
voltage at a predetermined terminal of the RAM pack 20. If the storage
capacity is identical to S2, the value S2 is stored in a register S in a
step SP15. If the storage capacity is identical to S1, the present process
advances to a step SP16 wherein the value S1 is stored in the register S.
After the process in the step SP15 and SP16 is executed, the present
process advances to a step SP17 of the check process shown in FIG. 5.
In the step SP17, the CPU 1 judges whether the data in the upper key area
FMP-Mu designated by the pointer Pu are identical to the end data END or
not. If such data are not identical to the end data END, the present
process advances to a step SP18 wherein the value of the pointer Pu is
increased by one, and then the process in the step SP17 is executed again.
Thereafter, processes in a loop consisting of steps SP17 and SP18 are
executed until the end data END are detected in the step SP17. When the
end data END are detected in the step SP17, a value (Pu+1) is written into
the register DSP in a step SP19. Since the start address of the upper key
area FMP-Mu is represented by the value "0", the result of the step SP19
indicates the data quantity (or a number of bytes) of the data stored in
the upper key area FMP-Mu (hereinafter, simply referred to as the data
quantity of the upper key area FMP-Mu). In other words, when the process
in the step SP19 is completely executed, a value representative of the
data quantity of the upper key area FMP-Mu is written in the register DSP.
In steps SP20 and SP21, the value of the pointer Pl is increased by one
until the data stored in the lower key area FMP-Ml designated by the
pointer Pl becomes identical to the end data END in the processes of the
steps SP17 and SP18. When the end data END are detected in the step SP20,
the present process advances to a step SP22 wherein an operation
represented by [DSP+(Pl-n1+1)] is performed and the result of such
operation is written in the register DSP. As is clear from FIG. 3, the
value (Pl-n1+1) indicates the data quantity of the data stored in the
lower key area FMP-Ml (hereinafter, simply referred to as the data
quantity of the lower key area FMP-Ml). Therefore, certain value is stored
in the register DSP after the process in the step SP22 is executed, and
such certain value indicates the sum of the two data quantity of the upper
key area FMP-Mu and the lower key area FMP-Ml.
Next, in processes in a loop consisting of steps SP23 and SP24, the data
quantity of the pedal key area FMP-Mp is detected in the manner similar to
the data quantity of the upper key area FMP-Mu and the lower key area
FMP-Ml. The detected data quantity of the pedal key area FMP-Mp is added
to the value of the register DSP in a step SP25. In processes in a loop
consisting of steps SP26 and SP27, the data quantity of the solo key area
FMP-Ms is detected and the detected data quantity is further added to the
value of the register DSP in a step SP28. In processes in a loop
consisting of steps SP29 and SP30, the data quantity of the registration
data area FMP-Mr is detected and the detected data quantity is added to
the value of the register DSP in a step SP31. As a result, certain value
must be stored in the register DSP after the process in the step SP31 is
executed, and such certain value indicates the sum of all data quantity of
the all areas. Such total sum can be visually shown by an area De in FIG.
3.
In a step SP31, the value of the register DSP, i.e., the sum of the
performance data is displayed by the display section 4.
In a step SP32, the CPU 1 judges whether the value of the register DSP is
larger than the vaue of the register S. At this time, either S1 (i.e., 8
kilo-bytes) and S2 (i.e., 32 kilo-bytes) has been assigned to the register
S as a result for executing the processes in the steps SP15 and SP16. In
addition, the value of the register DSP represents the data value of the
performance data. If such value of the register DSP is larger than the
value of the register S, the present process advances to a step SP33
wherein the following processes (a) to (d) are executed as described
below.
(a) The value "1" is set to the flag OVER. In the case where the answer of
the step SP32 is "YES", the performance data stored in the performance
data memory 10 will be overflowed from the RAM pack 20 if such performance
data are transferred to the RAM pack 20. Hence, the value "1" is set to
the flag OVER for indicating such overflowing.
(b) An operation of [(DSP-S)/S]*100 is performed, and the result thereof is
stored in the register DSP. Such operation result indicates the percentage
of the overflow ratio of the overflowing data quantity against the storage
capacity of the RAM pack 20.
(c) The display section 4 displays the above overflow ratio. This overflow
ratio and the sum of the performance data are alternately displayed by an
interval of one second. Incidentally, if the displaying space of the
display section 4 is big enough, both of the overflow ratio and the sum of
the performance data are displayed by the display section 4 simultaneously
and statically.
(d) An alarm is produced. By this alarm, the player can know that it is
impossible to save all of the performance data in the RAM pack 20.
After the above-mentioned processes are executed in the step SP33, the
present process advances to the main routine via a step SP34, in other
words, the present process advances to the data transfer process routine
LU3b.
Meanwhile, if the answer of the step SP32 is "NO", the process in the step
SP33 is skipped and then the present process advances to the data transfer
process routine LU3b via the step SP34 from the step SP32, because the
performance data are not overflowed from the RAM pack 20.
(2) DATA TRANSFER PROCESS ROUTINE LU3b
Next, description will be given with respect to the data transfer process
routine LU3b in conjunction with FIGS. 7A and 7B.
In this data transfer process routine LU3b, the CPU 1 initializes the
pointers Pu, Pl, Pp, Ps and Pr, and then the CPU 1 clears the pointer P
set in the working area 3 for indicating a data transfer destination in
steps SP40 and SP41 shown in FIG. 7A. In a next step SP42, the performance
data memory 10 is set to a read mode, and the RAM pack 20 is set to a
write mode. In a step SP34, the CPU 1 judges whether the data designated
by the pointer Pu are identical to the end data END or not. If the answer
of this step SP43 is "NO", the present process advances to a step SP44
wherein the data designated by the pointer Pu within the performance data
memory 10 (i.e., the data stored in the upper key area FMP-Mu) are
transferred to an address of the RAM pack 20 designated by the pointer P.
After such data are transferred to the RAM pack 20, each of the values of
the pointers Pu and P is increased by one, then the CPU 1 repeatedly
executes the process in the step SP43 again. Thereafter, the processes in
a loop consisting of the steps SP43 and SP44 are repeatedly executed until
the answer of the step SP43 becomes "YES". By repeatedly executing the
processes in the above loop, the RAM pack 20 is transferred with data
having the address "0" to the data having an address just before the
address of the end data END. When the answer of the step SP43 is turned to
"YES", the present process advances to a step SP45 wherein the end data
END are transferred to an address in the RAM pack 20 designated by the
pointer P and then the value of the pointer P is increased by one.
Thereafter, the present process advances to a next step SP46.
In the step SP46, the CPU 1 judges whether the data designated by the
pointer Pl within the lower key area FMP-Ml are identical to the end data
END or not. If the answer of this step SP46 is "NO", the present process
advances to a step SP47 wherein the data designated by the pointer Pl are
transferred to an address in the RAM pack 20 designated by the pointer P.
After such data are transferred to the RAM pack 20, the values of the
pointers Pl and P are increased by one, and then the present process
advances to a step SP48 wherein the CPU 1 judges whether the RAM pack 20
becomes full or not. Such judgment is necessary because there is the
possibility in that the RAM pack 20 becomes full in the middle of the data
transfer of the data stored in the lower key area F | | |
