Electrically-programmable low-impedance anti-fuse element

What is claimed is:

1. An electrically-programmable, low-impedance anti-fuse element, including:

a p-type semiconductor substrate,

a first electrode comprising a diffusion region in said substrate,

a dielectric layer over said diffusion region, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion,

a second electrode over said dielectric layer,

wherein at least one of said first and said second electrodes is heavily doped or implanted with arsenic such that a high concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode, and a controlled radius conductive filament in said dielectric layer electrically connecting said first and second electrodes.

2. The electrically-programmable, low-impedance anti-fuse element of claim 1, wherein the arsenic doping level is from 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3.

3. The electrically-programmable, low-impedance anti-fuse element of claim 1 wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10,000 angstroms.

4. The electrically-programmable, low-impedance anti-fuse element of claim 3 wherein said layer of polysilicon is heavily doped with arsenic such that a high concentration of arsenic exists at the interface between said second electrode and said dielectric layer.

5. The electrically-programmable, low-impedance anti-fuse element of claim 4, wherein the arsenic doping level in said polysilicon is from 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3.

6. The electrically-programmable, low-impedance anti-fuse element of claim 1, wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms, and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

7. The electrically-programmable, low-impedance anti-fuse element of claim 1 wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion.

8. The electrically-programmable low-impedance anti-fuse element of claim 6, wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion having a thickness of from 0 to 50 angstroms.

9. An electrically-programmable, low-impedance anti-fuse element, including:

a p-type semiconductor substrate,

a first electrode comprising a diffusion region in said substrate, said region heavily doped with arsenic such that a high concentration of arsenic exists at the surface of said region,

a dielectric layer over said diffusion region, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, and

a second electrode over said dielectric layer, and a controlled radius conductive filament in said dielectric layer electrically connecting said first and second electrodes.

10. The electrically-programmable low-impedance anti-fuse element of claim 9, wherein the arsenic doping level of said diffusion region is from 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3.

11. The electrically-programmable low-impedance anti-fuse element of claim 9 wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10,000 angstroms and is doped with arsenic to a level of from 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3 such that a high concentration of arsenic exists at the interface between said second electrode and said dielectric layer.

12. The electrically-programmable low-impedance anti-fuse element of claim 9 wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms, and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

13. The electrically-programmable low-impedance anti-fuse element of claim 9 wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion.

14. The electrically-programmable, low-impedance anti-fuse element of claim 12, wherein said dielectric layer further includes a third silicon dioxide portion having a thickness of from 0 to 50 angstroms.

15. An electrically-programmable, low-impedance anti-fuse element, including:

a semiconductor substrate,

an insulating layer over said semiconductor substrate,

a first electrode formed from a conducting material, over said insulating layer,

a dielectric layer over said first electrode, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, second electrode over said dielectric layer,

wherein at least one of said first and second electrodes is heavily doped with arsenic such that a high concentration of arsenic atoms exists at the interface of said dielectric layer and said heavily doped one of said first or second electrodes and a controlled radius conductive filament in said dielectric layer electrically connecting said first and second electrodes.

16. The electrically-programmable low-impedance anti-fuse element of claim 15 wherein at least one of said first and second electrodes includes a layer of polysilicon heavily doped with arsenic such that a high concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode.

17. The electrically-programmable, low-impedance anti-fuse element of claim 16 wherein said layer of polysilicon has a thickness of from 500 to 10,000 angstrom and is doped with arsenic to a level of from 1.times.10.sup..multidot. to 1.times.10.sup.22 atoms/cm.sup.3.

18. The electrically-programmable, low-impedance anti-fuse element of claim 15 wherein both of said first and second electrodes include a layer of polysilicon having a thickness of from 500 to 10,000 angstroms and doped with arsenic to a level of from 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3.

19. The electrically-programmable low-impedance anti-fuse element of claim 15 wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms, and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

20. The electrically-programmable, low-impedance anti-fuse element of claim 15 wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion.

21. The electrically-programmable, low-impedance anti-fuse element of claim 19, wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion having a thickness of from 0 to 50 angstroms.

22. A semiconductor structure disposed in an integrated circuit, including:

a plurality of electrically-programmable low-impedance anti-fuses, each of said anti-fuses including a first electrode formed from a conductive material, a dielectric layer over said first electrode, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, and a second electrode formed of a conductive material over said dielectric layer, wherein at least one of said first and second electrodes is heavily doped with arsenic such that a heavy concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode,

at least one of said electrically-programmable low impedance anti-fuse element including a controlled-radius filament in said dielectric layer electrically connecting said first and second electrodes.

23. The semiconductor structure of claim 22, wherein at least one of said first and second electrodes includes a layer of polysilicon heavily doped with arsenic to a level of 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3 having a thickness of from 500 to 10,000 angstroms.

24. The semiconductor structure of claim 22, wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

25. The semiconductor structure of claim 22 further including a third silicon dioxide portion over said second silicon nitride portion in said dielectric layer.

26. The semiconductor structure of claim 24 further including a third silicon dioxide portion over said second silicon nitride portion in said dielectric layer, having a thickness from 0 to 50 angstroms.

27. The semiconductor structure of claim 22, wherein both of said first and said second electrodes of each of said plurality of electrically-programmable low-impedance anti-fuse elements include a layer of polysilicon heavily doped with arsenic such that a high concentration of arsenic atoms exists at the interface between said dielectric layer and each of said first and second electrodes.

28. The semiconductor structure of claim 27 wherein said first and second electrodes include a layer of polysilicon having a thickness of from 500 to 10,000 angstroms doped with arsenic to a level of from 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3.

29. The semiconductor structure of claim 22, wherein said controlled-radium filament has a resistance of less than 300 ohms.

30. A semiconductor structure disposed in an integrated circuit, including:

a plurality of electrically-programmable low-impedance anti-fuses, each of said anti-fuses including a first electrode comprising an n-type diffusion region in a p-type semiconductor substrate of said semiconductor structure, a dielectric layer over said first electrode, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, and a second electrode formed of a conductive material over said dielectric layer, wherein at least one of said first and second electrodes is heavily doped with arsenic such that a heavy concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode,

at least one of said electrically-programmable low impedance anti-fuse elements including a controlled-radius filament in said dielectric layer electrically connecting said first and second electrodes.

31. The semiconductor structure of claim 30, wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10,000 angstroms.

32. The semiconductor structure of claim 30, wherein each of said n-type diffusion regions are doped with arsenic to a concentration of from between 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3.

33. The semiconductor structure of claim 32, wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10,000 angstroms doped with arsenic to a concentration of from 1.times.10.sup.19 to 1.times.10.sup.22 atoms/cm.sup.3.

34. The semiconductor structure of claim 30, wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

35. The semiconductor structure of claim 30, further including a third silicon dioxide portion over said second silicon nitride portion in said dielectric layer.

36. The semiconductor structure of claim 34, wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion, said third silicon dioxide portion having a thickness of from 0 to 50 angstroms.

37. The semiconductor of any one of claims 22, 23, 24, 26, 28, 29, 30-33, 34-36, further including:

means for applying a programming voltage to said first and second electrodes of selected ones of said anti-fuses from input/output pins of said integrated circuit.

38. A user-programmable read-only-memory array, including:

a plurality of bit lines,

a plurality of word lines, forming intersections with bit lines,

a plurality of memory cells, one of said memory cells located at each of said intersections, each of said memory cells including an electrically-programmable, low-impedance anti-fuse according to any of claims 1-5, 7, 10-11, 13-18, 20, 22-25, 27-29, each of said memory cells further including a transistor having a source, a drain, and a gate, one end of said anti-fuse connected to the one of said bit lines associated with said intersection, the other end of said anti-fuse connected to the drain of said transistor, the source of said transistor being connected to a fixed voltage potential, and the gate of said transistor being connected to the one of said word lines associated with said intersection,

a Y-address decoder having a plurality of Y-address inputs, and a set of outputs, each of said outputs corresponding to one of said word lines in said array, said Y-address decoder operating to activate only one of said word lines for unique combination of said data on said Y-address inputs,

an X-address decoder, having a plurality of X-address inputs, a set of outputs, and a data output, each one of said outputs connected to one of said bit lines, such that only one of said bit lines is connected to said data output when a unique combination of data appears on said X-address inputs,

means for applying a programming voltage to a selected one of said bit lines at a selected time, and,

means for applying said programming voltage to a selected one of said word lines at said selected time.

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BACKGROUND

1. Field of the Invention

The present invention relates to the field of integrated electronic circuit technology. More particularly, the invention relates to a reliable and manufacturable capacitor-like, electrically-programmable interconnect device to be used in integrated circuits.

2. The Prior Art

Integrated electronic circuits are usually made with all internal connections set during the manufacturing process. However, because of high development costs, long lead times, and high manufacturing tooling costs of such circuits, users often desire circuits which can be configured or programmed in the field. Such circuits are called programmable circuits and they usually contain programmable links. Programmable links are electrical interconnects which are either broken or created at selected electronic nodes by the user after the integrated device has been fabricated and packaged in order to activate or deactivate respectfully the selected electronic nodes.

Programmable links have been used extensively in programmable read only memory devices (PROMs). Probably the most common form of programmable link is a fusible link. When a user receives a PROM device from a manufacturer, it usually consists of an X-Y matrix or lattice of conductors or semiconductors. At each cross-over point of the lattice a conducting link, called a fusible link, connects a transistor or other electronic node to this lattice network. The PROM is programmed by blowing the fusible links to selected nodes and creating an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data which the user wishes to store in the PROM.

Such fusible link PROM systems present certain disadvantages. For instance, because of the nature of the conducting material in the link, relatively high voltage and high current levels are needed during programming to guarantee the complete blowing of the fusible links. Since the link is usually conductive, it needs large amounts of power dissipation to blow it. Also, the shape and size of the fusible link must be precise so that the link will function effectively as a conductor if it is not blown and will be a completely open circuit if it is blown. Therefore, very critical photolithographic steps and controlled etch techniques ar required during the manufacturing process of fusible link PROMs. Finally, a large gap must be blown in the link in order to prevent it from later becoming closed through the accumulation of the conducting material near the blown gap. Fusible link memory cells are relatively large in order to accommodate the link and its associated selection transistor and, therefore, fusible link PROM systems have high manufacturing and material costs and take up large amounts of chip real estate space.

In recent years, a second type of programmable links, called anti-fuse links, have been developed for use in integrated circuit applications. Instead of the programming mechanism causing an open circuit as is the case with fusible links, the programming mechanism in anti-fuse circuits creates a short circuit o relatively low resistance link. Anti-fuse links consist of two conductor and/or semiconductor materials having some kind of a dielectric or insulating material between them. During programming, the dielectric at selected points in between the conductive materials is broken down by predetermined applied voltages, thereby electrically connecting the conducting or semiconducting materials together.

Various materials have been suggested for the both the conducting layers and the dielectric or insulating layer. Some of the suggested dielectric materials require a relatively high current and voltage during programming, require complex manufacturing techniques and have low reliability during programming because it is difficult to control the reproducibility of the conductive state due to the nature of the crystalline structures of the materials involved. In addition, the programming process results in a link having a finite resistance in the order of several hundred to several thousand ohms. This characteristic of the known anti-fuse elements renders them relatively unsuitable for use in high speed circuits.

Some of the proposed dielectric insulators are doped amorphous silicon alloys, polycrystalline resistors, oxides, titanates of transition metals, oxides of silicon, aluminum oxide and cadmium sulfide. The problems with approaches utilizing these materials, have been related to the need of a high current and voltage to program or the difficulty to repeatably manufacture and control their reliability in both the on and off states. Materials such as cadmium sulfide, aluminum oxide and titanate present complicated technological problems because they are difficult to integrate into standard semiconductor processing.

Examples of known anti-fuse elements are found in the prior art using various insulating materials. Reference is made to: U.S. Pat. No. 3,423,646 which uses aluminum oxide, cadmium sulfide; U.S. Pat. No. 3,634,929 which uses single film of Al.sub.2 O.sub.3, SiO.sub.2, and Si.sub.3 N.sub.4 ; U.S. Pat. No. 4,322,822 which uses SiO.sub.2 ; U.S. Pat. No. 4,488,262 which uses oxide or titanate of a transition metal; U.S. Pat. No. 4,499,557 which uses doped amorphous silicon alloy; U.S. Pat. No. 4,502,208 which uses SiO.sub.2 ; U.S. Pat. No. 4,507,757 which uses SiO.sub.2 ; U.S. Pat. No. 4,543,594 which uses SiO.sub.2.

Most of the above patents either describe complicated technologies or need high breakdown voltages and currents, and or are difficult to manufacture or do not meet the reliability requirements of state-of-the-art integrated circuits in both the on and off states. The prior art does not disclose the creation of controllable-radius conductive filaments with low resistance after programming or the need of specific electrode material or composition which would flow into the dielectric and create the required filament.

Other problems associated with existing anti-fuse links include large memory cells, and complex manufacturing processes for the unblown anti-fuse elements.

OBJECTS AND ADVANTAGES

An object of the present invention is to provide an electrically-programmable low-impedance interconnect element.

Another object of the present invention is to provide an electrically-programmable interconnect element which may be programmed with sufficiently low voltages and currents compatible with state-of-the-art semiconductor technology, resulting in a low impedance in the on-state.

Another object of the present invention is to provide an electrically-programmable interconnect element which is manufacturable using standard semiconductor processing and has high reliability in both the on and off states.

Yet another object of the present invention is t provide a reliable, electrically-programmable interconnect element, a plurality of which may be disposed in a integrated circuit for making selectable low-impedance interconnections.

Advantages associated with the present invention in some or all of its embodiments include an interconnect which can be made with standard semiconductor manufacturing techniques, having a small size, a high reading current after programming, may be fabricated using manufacturing process with a minimal number of steps, and having a controlled radius interconnect filament through the dielectric after programming resulting in a repeatably manufacturable controlled low resistance link after programming. Furthermore, the present invention is characterized by high reliability in both the programmed and unprogrammed state. Other and further advantages of the present invention will appear hereinafter.

SUMMARY OF THE INVENTION

An electrically-programmable anti-fuse, having a low impedance after programming, is disclosed. It consists of a capacitor-like structure having a first electrode and a second electrode with a dielectric layer disposed therebetween, characterized by a high impedance and very low leakage current before programming and a low-resistance after programming. A plurality of such anti-fuses may be disposed in a semiconductor integrated circuit, and may be selectively blown to create low-impedance interconnects at selected locations within the integrated circuit. The anti-fuses may be blown either before or after packaging of the integrated circuit die.

In accordance with the present invention, it is contemplated that a plurality of such anti-fuses is disposed in an integrated circuit, having means, such as contacts, polysilicon and metal lines, or combinations of the foregoing, for applying a programming voltage between the two electrodes of selected anti-fuses, from a signal originating at input/output (I/O) pads of the completed integrated circuit, for the purpose of creating a controlled-radius conductive filament through the dielectric layer and for connecting the anti-fuse of other circuitry.

The low impedance anti-fuse element of the present invention includes a dielectric between two conductive electrodes formed of an arsenic-containing material which will form the filament, such as arsenic-doped silicon or polysilicon. In a preferred embodiment, the first electrode may be made of a high electromigration immunity material and may be formed from either a diffusion region, heavily doped with arsenic, to provide for material which will form the filament, in a semiconductor substrate, polysilicon heavily doped with arsenic to provide the material which will form the filament, or single crystal silicon heavily doped with arsenic to provide the material which will form the filament.

The polysilicon may have a metal layer adjacent to it, on the side opposite to the side interfacing with the dielectric layer. Those of ordinary skill in the art will recognize that the metal may be any substance used to provide interconnect in integrated circuits or is used as a diffusion barrier. In addition, it is believed that combinations of the above materials will function in the present invention.

The second electrode may be formed of a conductor material such as a polysilicon layer heavily doped with arsenic to provide an arsenic-containing material which will be the material which will form the filament, an aluminum layer or an aluminum alloy layer. In other embodiments, lower electromigration immunity materials may be used as long as the current passed through the low impedance anti-fuse after programming is appropriately limited to assure proper lifetime.

In a preferred embodiment wherein the two electrodes are silicon or polysilicon layers heavily doped with arsenic, the concentration of the arsenic dopant should be highest at the interfaces between each of the electrode and the dielectric layer, since this will provide a large concentration of arsenic atoms which will flow to form the arsenic-containing filament.

The dielectric layer between the two electrodes may be either a singe layer or a composite, and is such that when it is disrupted by a high electric field, it will facilitate the flow of arsenic material comprising one or both of the two electrodes to produce a controlled-radius conductive filament during its breakdown. A "controlled-radius" filament refers to the fact that approximately the same radius may be repeatably achieved from instance to instance if the same programming parameters are employed on substantially identical structures. Such a dielectric requires a low amount of charge fluence to breakdown at the higher programming voltage with practically-used voltages and currents in integrated circuits. It also has a large enough charge fluence to breakdown at normal operating voltages to be a reliable circuit element during operation in its unprogrammed state.

After the formation of the filament, and during its formation, arsenic will flow from both electrodes and heavily dope the filament material with arsenic atoms. This will reduce the filament resistance and make its value more controllable.

During programming, as the applied voltage reaches the dielectric breakdown value, a localized weak spot in the dielectric starts to carry most of the leaking current and heats up, which, in turn, increases the leakage current. A thermal runaway condition develops which results in localized heating and melting of the dielectric and adjacent electrode material which includes arsenic. The arsenic-containing conductive material will flow from one of the two electrodes and form a conductive filament shorting both electrodes. The thickness of the electrodes should be sufficient not to cause any discontinuity or pits during the filament formation. The surface concentration and amount of arsenic should be sufficient to obtain the required low impedance filament. The final radius of the filament depend on the composition and thickness of the dielectric, the electrode conductive material melting temperature, the amount of arsenic in the electrodes, and the energy dissipated during programming.

Lower final resistance of this element after its programming can be obtained with a larger radius and a lower resistivity of the formed filament by addition of large quantities of arsenic atoms in the electrodes at the electrode-dielectric interface and a lower spreading resistance of both electrodes. A larger filament radius and higher electromigration immunity of the arsenic-containing conductive electrode material or composition which flows to form the filament result in higher current carrying capacity of the programmed element without the potential for creating a later open circuit due to electromigration. As the current which is applied across a filament increases, the larger the filament gets and the material which flows from both electrodes into the filament contains more arsenic thus lowering the anti-fuse resistance and preventing the electromigration of the filament.

In a preferred embodiment, one of the conductors, the top electrode, is formed of heavily doped polysilicon or is a sandwich of said polysilicon and a metal above it. The polysilicon layer should be heavily doped with arsenic, preferably to a concentration of between approximately 1.times.10.sup.19 and 1.times.10.sup.22 atoms/cm.sup.3. Larger arsenic dopant concentrations result in lower filament resistances.

The other conductor, the lower electrode, is formed of heavily-doped diffusion region in a substrate or a well. This diffusion should be, preferably, heavily doped with arsenic to a concentration in the range of that of the top electrode. The arsenic doping profile should be such that the heaviest concentration of arsenic is present at the interfaces between the electrodes and the dielectric.

The dielectric in one presently-preferred embodiment is a three-layer sandwich formed of a bottom oxide layer of 20 A-50 A, a central silicon nitride (Si.sub.3 N.sub.4) layer of 40 A-100 A, and a top oxide layer of 0 A to 50 A. In alternate preferred embodiments, the dieleotric may be either a single layer of silicon dioxide, having a thickness of between approximately 60 and 150 angstroms, or a single layer of silicon nitride, Si.sub.3 N.sub.4, having a thickness of between approximately 60 and 200 angstroms.

The low impedance anti-fuse element in the preferred embodiment is programmed by applying a current-controlled voltage source across the two electrodes. The composition of the composite dielectric is such that the structure provides an on-resistance of less than 300 ohms after programming and an off-resistance of more than 100 Mohms before programming. The structure requires a programming pulse of magnitude less than 30 volts, a time duration of less than 100 msec while supplying a current of less than 10 mA. The size of the conductive filament is a function of the voltage and current of the programming pulse and the composition of the composite dielectric structure. The resistance of the conductive filament is a function of the duration, voltage and current of the programming pulse and the amount of arsenic at the interfaces.

In a second and third embodiment of the low impedance anti-fuse element, the first and second electrodes may be formed from polysilicon lines doped with arsenic. This facilitates the interconnect between two conductors without using the silicon substrate as a path. Hence, the substrate can be used for active devices independent of the anti-fuses in the integrated circuit.

Those of ordinary skill in the art will recognize that the technology of this invention is compatible with and may be applied to any semiconductor structure or process to provide user-selectable interconnections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-section of a first preferred embodiment of both a programmed and an unprogrammed low impedance anti-fuse element of the present invention, wherein the first electrode is a diffusion region in a semiconductor substrate material and the second electrode is a polysilicon layer.

FIG. 2 is a cross-section of a second preferred embodiment of both a programmed and an unprogrammed low impedance anti-fuse element according to the present invention wherein both electrodes of each anti-fuse are polysilicon layers above and insulated from the substrate.

FIG. 3 is a cross-section of an alternative embodiment of both a programmed and an unprogrammed low impedance anti-fuse element according to the present invention, wherein the first electrode for each anti-fuse is a polysilicon electrode above and insulated from the substrate and the second electrode for each anti-fuse is a metal layer over a barrier metal layer covering the dielectric layer.

FIG. 4 is a schematic diagram illustrating how the electrically-programmable low-impedance anti-fuse of the present invention may be programmed using the external input/output pins of the integrated circuit in which it is contained.

FIG. 5a is a circuit diagram showing an application of the electrically programmable low-impedance anti-fuse of the present invention as a read-only-memory.

FIG. 5b is a schematic showing a first alternate embodiment for a cell of a read-only-memory constructed using the electrically-programmable low-impedance anti-fuse of the present invention.

FIG. 5c is a second alternate embodiment of a cell of a read-only-memory constructed using the electrically-programmable low-impedance anti-fuse of the present invention.

FIG. 6 is a semiconductor profile drawing showing a cross-section of a memory cell from the array of FIG. 5a.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring first to FIG. 1, a preferred embodiment of the present invention is fabricated on a semiconductor substrate 10. Those of ordinary skill in the art will readily recognize that substrate 10 may in fact be a well region of one conductivity type fabricated in a semiconductor substrate of opposite conductivity type as is common in a CMOS process or a heavily doped contact point having the same polarity as substrate 10. In the embodiment of FIG. 1, the first electrode 12a and 12b of unprogrammed anti-fuse 13 and programmed anti-fuse 15, respectively, are formed of a heavily-doped diffusion area in substrate 10. First electrodes 12a and 12b may, for example be ion-implanted to a concentration of from approximately 1.times.10.sup.19 to 1.times.10.sup.22 atom/cm.sup.3 with arsenic at an energy of from approximately 30 to 120 KeV, preferably 50 KeV. Although ion implantation is presently preferred, those of ordina