A multiprocessor which includes a plurality of processing units interconnected by a global bus. Each processing unit has the capability for initiating control instructions including notification instructions and for selectively transmitting the control instructions over the global bus to the plurality of processing units and trigger device for initiating execution of the control instructions as a destination processing unit. A multiprocessor so constructed is capable of executing blocks of instructions sequentially or concurrently or both at required by a single program to reduce program execution time to a minimum.
This application is a continuation, of application Ser. No. 07/022,501, filed Mar. 6, 1987, now abandoned which is a continuation of 06/611,298, filed May 17, 1984, now abandoned.
A digital processing system including a central processing unit (CPU) and a digital signal processor (DSP) is optimized for digital signal processing applications, providing the central processing unit and digital signal processor with equal access to system resources such as system memory and connected I/O devices. The digital processing system includes two high-performance processor busses: one processor bus providing connection for one to four CPUs; the other processor bus providing connection for up to four DSPs. An advanced multi-ported memory controller interconnects the two processor busses with system memory and a system I/O bus, providing the CPUs and DSPs with equal and uniform access to all system memory and I/O resources.
A data distribution device transfers digitized audio and digital data between memories of processors in a multi-processor communications system on a sample bus without protocols or handshaking between the source and destination processors. The device is capable of dynamic reconfiguration of its distribution pattern when peripherally commanded and has individual control over all memory read, chip select and write lines. Through an indirect register addressing scheme the present system has the ability to read from an address within any single memory and then write to an address within any or all other memories of the processors within the communications system.
A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routing a signal command generated by the device to a signal dispatch logic and a second switch for receiving signals generated by the signal dispatch logic and routing the signals to the selected device. The signal dispatch logic receiving the signal command, decodes the destination select value and generates a signal to be sent to the selected device. The signal command includes a destination select value representing a device selectably determined by the device. The signaling mechanism also includes an arbitration mechanism connected to the signal dispatch logic and the first switch for resolving simultaneous conflicting signal commands issued by two or more devices. The signal generated by the signal dispatch logic may include a plurality of bits representing one or more types of predefined signals to be acted upon by the device.
A fast interrupt mechanism is capable of simultaneously interrupting a community of associated processors in a multiprocessor system. The fast interrupt mechanism enables the more effective debugging of software executing on a multiprocessor system by allowing all of the processors in a community associated with a parallel process to be halted within a limited number of clock cycles following a hardware exception or processor breakpoint. The fast interrupt mechanism consists of a set of registers that are used to identify associations among multiple processors, a comparison matrix that is used to select processors to be interrupted, a network of interconnections that transmit interrupt events to and from the processors, and elements in the processors that create and respond to fast interrupt events.
This invention provides an electronic safety break device and method for protecting an electrical circuit. In a preferred embodiment, the electronic safety break device of this invention includes switching means for making and breaking an electrical connection, current measuring means for measuring the magnitude and direction of the current flowing through the connection, voltage measuring means for measuring voltage on each side of the electrical connection, and means responsive to the current and voltage measuring means for controlling the switching means. The electronic safety break device and method of the present invention thus provide for a bidirectional safety break for an electrical connection between a rechargeable battery and a load and other external circuitry, protecting the battery from excessive charge and discharge currents and from undervoltage and overvoltage conditions, or any combination of these conditions.
