A data decoding system includes a data retrieval device which retrieves encoded data from a mass-storage device and transmits the data to a serial-to-parallel shift register. The shift register, operating at the data transfer rate, converts the encoded data to a parallel stream of bit-pairs. The bit-pairs are then transmitted, over parallel lines, to a second shift register which is operating at one-half the data transfer rate. The second shift register stores a sufficient number of the bit-pairs to constitute a byte of binary data when decoded. Once enough bit-pairs are stored, a ROM, operating at a rate which is slower than the data transfer rate, decodes the information to form a byte of binary data. The system utilizes a data retrieval system with a high data transfer rate and processing circuitry with a reduced bandwidth requirement to produce decoded data at a rate which is comparable to the data transfer rate.
A decoder for decoding a serial data stream employs an extracted base clock signal, synchronous with an input, coded, serial data stream, a first fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary frequency clock signal for synthesizing a pre-decoded value, produced by a first combinative logic network, within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop. In a decoder according to the present invention, a pipelined operation is implemented by momentarily storing the bits (part of the bits handled by the decoder) that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock signal the processing, by said first combinative network, of the total n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the rising front of the output sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating speed may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.
A decoder of a coded serial stream of digital data in a stream of decoded NRZ data has re-timing (BB, AA) flip-flops and a 2.times.1 multiplexer (MUX OUT) selectably providing a single-bit NRZ output stream or a dual-bit (NRZ0 and NRZ1) output streams, by exploiting the predecoded values (ND0 and ND1) produced by two decoding combinative logic networks (RC1 and RC2) that compose the decoder.
